AG903ライブラリリファレンス
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AG903_spcreg.h
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1: 9: 10: 14: 15:
#ifndef
_AG903_SPC_REGMAP_H_ 16:
#define
_AG903_SPC_REGMAP_H_ 17: 18: 19:
#include
"AG903_regmap.h" 20: 21:
#ifndef
__I
22: 23:
#define
__I
volatile
const
24:
#endif
25:
#ifndef
__O
26: 27:
#define
__O
volatile
28:
#endif
29:
#ifndef
__IO
30: 31:
#define
__IO
volatile
32:
#endif
33: 34: 35:
typedef
struct
{ 36: 37:
union
{ 38:
__IO
uint32_t BOOTUP_STATUS; 39: 40:
struct
{ 41: uint32_t : 8; 42:
__IO
uint32_t HWR : 1; 43:
__IO
uint32_t WDR : 1; 44: uint32_t : 6; 45:
__IO
uint32_t PWR : 1; 46: } BOOTUP_STATUS_bits; 47: }; 48: 49:
__I
uint32_t RESERVED1[7]; 50: 51:
union
{ 52:
__IO
uint32_t FCS_CTRL; 53: 54:
struct
{ 55: uint32_t : 6; 56:
__IO
uint32_t FCS : 1; 57: uint32_t : 3; 58:
__IO
uint32_t SW_RST : 1; 59: uint32_t : 1; 60:
__IO
uint32_t CPU_MASK : 1; 61:
__IO
uint32_t CPU_MASK2 : 1; 62: uint32_t : 14; 63:
__IO
uint32_t FCS_PLL0_RSTn : 1; 64: uint32_t : 2; 65:
__IO
uint32_t SELFR_CMD_OFF : 1; 66: } FCS_CTRL_bits; 67: }; 68: 69:
union
{ 70:
__IO
uint32_t INT_STATUS; 71: 72:
struct
{ 73: uint32_t : 6; 74:
__IO
uint32_t INT_FCS : 1; 75: } INT_STATUS_bits; 76: }; 77: 78:
union
{ 79:
__IO
uint32_t INT_ENABLE; 80: 81:
struct
{ 82:
__IO
uint32_t EINT_R0 : 1; 83:
__IO
uint32_t EINT_R1 : 1; 84: uint32_t : 1; 85:
__IO
uint32_t EINT_R3 : 1; 86:
__IO
uint32_t EINT_R4 : 1; 87:
__IO
uint32_t EINT_R5 : 1; 88:
__IO
uint32_t EINT_FCS : 1; 89: uint32_t : 1; 90:
__IO
uint32_t EINT_R8 : 1; 91: } INT_ENABLE_bits; 92: }; 93: 94:
union
{ 95:
__IO
uint32_t SOFTRESET_SETUP; 96: 97:
struct
{ 98:
__IO
uint32_t SWRST_ACTIVE : 5; 99: uint32_t : 11; 100:
__IO
uint32_t SWRST_WAIT : 5; 101: } SOFTRESET_SETUP_bits; 102: }; 103: 104:
union
{ 105:
__IO
uint32_t PLL0_CTRL; 106: 107:
struct
{ 108:
__IO
uint32_t EN : 1; 109:
__IO
uint32_t STB : 1; 110: uint32_t : 2; 111:
__IO
uint32_t MUX : 4; 112:
__IO
uint32_t DIV : 3; 113: uint32_t : 5; 114:
__IO
uint32_t MS : 5; 115: uint32_t : 3; 116:
__IO
uint32_t NS : 6; 117: } PLL0_CTRL_bits; 118: }; 119: 120:
__I
uint32_t RESERVED2[3]; 121: 122:
union
{ 123:
__IO
uint32_t DDRPHY_PLLSETUP; 124: 125:
struct
{ 126:
__IO
uint32_t PLLEN : 1; 127: } DDRPHY_PLLSETUP_bits; 128: }; 129: 130:
union
{ 131:
__IO
uint32_t DDRPHY_DLLSETUP; 132: 133:
struct
{ 134:
__IO
uint32_t DLLEN : 1; 135: uint32_t : 7; 136:
__IO
uint32_t FRANGE : 3; 137: } DDRPHY_DLLSETUP_bits; 138: }; 139: 140:
__I
uint32_t RESERVED3[2]; 141: 142:
union
{ 143:
__IO
uint32_t AHB_CLK_CTRL; 144: }; 145: 146:
__I
uint32_t RESERVED4[3]; 147: 148:
union
{ 149:
__IO
uint32_t APB_CLK_CTRL; 150: }; 151: 152:
__I
uint32_t RESERVED5[7]; 153: 154:
union
{ 155:
__IO
uint32_t AXI_CLK_CTRL1; 156: }; 157: 158:
union
{ 159:
__IO
uint32_t AXI_CLK_CTRL2; 160: 161:
struct
{ 162:
__IO
uint32_t ACLK_EN2 : 13; 163: } AXI_CLK_CTRL2_bits; 164: }; 165: 166:
__I
uint32_t RESERVED6[162]; 167: 168:
union
{ 169:
__IO
uint32_t PLL1_CTRL; 170: 171:
struct
{ 172:
__IO
uint32_t MS : 6; 173: uint32_t : 2; 174:
__IO
uint32_t NS : 6; 175: uint32_t : 2; 176:
__IO
uint32_t FR : 2; 177: uint32_t : 2; 178:
__IO
uint32_t SRC : 2; 179: uint32_t : 2; 180:
__IO
uint32_t DIV : 3; 181: uint32_t : 1; 182:
__IO
uint32_t EN : 1; 183: } PLL1_CTRL_bits; 184: }; 185: 186:
union
{ 187:
__IO
uint32_t PLL2_CTRL; 188: 189:
struct
{ 190:
__IO
uint32_t MS : 6; 191: uint32_t : 2; 192:
__IO
uint32_t NS : 6; 193: uint32_t : 2; 194:
__IO
uint32_t FR : 2; 195: uint32_t : 2; 196:
__IO
uint32_t SRC : 2; 197: uint32_t : 2; 198:
__IO
uint32_t DIV : 3; 199: uint32_t : 1; 200:
__IO
uint32_t EN : 1; 201: } PLL2_CTRL_bits; 202: }; 203: 204:
union
{ 205:
__IO
uint32_t PLL3_CTRL; 206: 207:
struct
{ 208:
__IO
uint32_t MS : 6; 209: uint32_t : 2; 210:
__IO
uint32_t NS : 6; 211: uint32_t : 2; 212:
__IO
uint32_t FR : 2; 213: uint32_t : 2; 214:
__IO
uint32_t SRC : 2; 215: uint32_t : 2; 216:
__IO
uint32_t DIV : 3; 217: uint32_t : 1; 218:
__IO
uint32_t EN : 1; 219: } PLL3_CTRL_bits; 220: }; 221: 222:
union
{ 223:
__IO
uint32_t PLLA_CTRL; 224: 225:
struct
{ 226:
__IO
uint32_t MS : 4; 227:
__IO
uint32_t CC : 3; 228: uint32_t : 1; 229:
__IO
uint32_t NS : 8; 230:
__IO
uint32_t FR : 2; 231: uint32_t : 2; 232:
__IO
uint32_t SRC : 2; 233: uint32_t : 2; 234:
__IO
uint32_t DIV : 3; 235: uint32_t : 1; 236:
__IO
uint32_t EN : 1; 237: } PLLA_CTRL_bits; 238: }; 239: 240:
union
{ 241:
__IO
uint32_t SOFTRESET_MASK1; 242: }; 243: 244:
union
{ 245:
__IO
uint32_t SOFTRESET_MASK2; 246: }; 247: 248:
union
{ 249:
__IO
uint32_t SOFTRESET_MASK3; 250: }; 251: 252:
union
{ 253:
__IO
uint32_t SOFTRESET_MASK4; 254: }; 255: 256:
union
{ 257:
__IO
uint32_t SOFTRESET_MASK5; 258: }; 259: 260:
__I
uint32_t RESERVED7[4]; 261: 262:
union
{ 263:
__IO
uint32_t APB_SDMC_CLK_CTRL; 264: 265:
struct
{ 266:
__IO
uint32_t PCLK_EN : 24; 267:
__IO
uint32_t SDMCCLK_EN : 8; 268: } APB_SDMC_CLK_CTRL_bits; 269: }; 270: 271:
union
{ 272:
__IO
uint32_t MISC_CLK_CTRL; 273: }; 274: 275:
union
{ 276:
__I
uint32_t PIN_STATUS; 277: 278:
struct
{ 279:
__I
uint32_t MODE : 4; 280:
__I
uint32_t TEST : 4; 281: } PIN_STATUS_bits; 282: }; 283: 284:
__I
uint32_t RESERVED8[4]; 285: 286:
union
{ 287:
__IO
uint32_t SDMC_MISC_CTRL; 288: 289:
struct
{ 290:
__IO
uint32_t CLK_SEL : 1; 291: uint32_t : 7; 292:
__IO
uint32_t SREF_REQ : 1; 293: uint32_t : 3; 294:
__I
uint32_t SREF_ACK : 1; 295: uint32_t : 3; 296:
__IO
uint32_t WCLK_SEL : 4; 297:
__IO
uint32_t RCLK_SEL : 4; 298:
__IO
uint32_t HCLK_SEL : 4; 299: } SDMC_MISC_CTRL_bits; 300: }; 301: 302:
union
{ 303:
__IO
uint32_t DDR_MISC_CTRL; 304: 305:
struct
{ 306:
__IO
uint32_t REFRESH : 1; 307: uint32_t : 7; 308:
__I
uint32_t INIT_OK : 1; 309: } DDR_MISC_CTRL_bits; 310: }; 311: 312:
union
{ 313:
__IO
uint32_t SPIROM_MISC_CTRL; 314: 315:
struct
{ 316:
__IO
uint32_t ADDR_CYC : 1; 317: } SPIROM_MISC_CTRL_bits; 318: }; 319: 320:
union
{ 321:
__IO
uint32_t CLK_SEL1; 322: 323:
struct
{ 324:
__IO
uint32_t HDACLK_SEL : 2; 325: uint32_t : 2; 326:
__IO
uint32_t DT0CLK_SEL : 1; 327: uint32_t : 3; 328:
__IO
uint32_t DT1CLK_SEL : 2; 329: uint32_t : 2; 330:
__IO
uint32_t LVDSCLK_SEL : 1; 331: uint32_t : 3; 332:
__IO
uint32_t CP0CLK_SEL : 2; 333: uint32_t : 2; 334:
__IO
uint32_t CP1CLK_SEL : 2; 335: } CLK_SEL1_bits; 336: }; 337: 338:
__I
uint32_t RESERVED9[1]; 339: 340:
union
{ 341:
__IO
uint32_t CLK_SSP_SEL; 342: 343:
struct
{ 344:
__IO
uint32_t SSP0CLK_SEL : 3; 345: uint32_t : 1; 346:
__IO
uint32_t SSP1CLK_SEL : 3; 347: uint32_t : 1; 348:
__IO
uint32_t SSP2CLK_SEL : 3; 349: uint32_t : 1; 350:
__IO
uint32_t SSP3CLK_SEL : 3; 351: uint32_t : 1; 352:
__IO
uint32_t PLL3CLK_SEL : 2; 353: } CLK_SSP_SEL_bits; 354: }; 355: 356:
union
{ 357:
__IO
uint32_t CLK_SSP_DIV; 358: 359:
struct
{ 360:
__IO
uint32_t SSP0CLK_DIV : 5; 361: uint32_t : 3; 362:
__IO
uint32_t SSP1CLK_DIV : 5; 363: uint32_t : 3; 364:
__IO
uint32_t SSP2CLK_DIV : 5; 365: uint32_t : 3; 366:
__IO
uint32_t SSP3CLK_DIV : 5; 367: } CLK_SSP_DIV_bits; 368: }; 369: 370:
union
{ 371:
__IO
uint32_t ETH_PHY_SEL; 372: 373:
struct
{ 374:
__IO
uint32_t RMII : 1; 375: } ETH_PHY_SEL_bits; 376: }; 377: 378:
union
{ 379:
__IO
uint32_t CA5_MISC_CTRL1; 380: 381:
struct
{ 382:
__IO
uint32_t dbgen : 4; 383:
__IO
uint32_t dbgrestart : 4; 384:
__IO
uint32_t dbgromaddrv : 1; 385: uint32_t : 3; 386:
__IO
uint32_t dbgselfaddrv : 1; 387: } CA5_MISC_CTRL1_bits; 388: }; 389: 390:
union
{ 391:
__IO
uint32_t CA5_MISC_CTRL2; 392: 393:
struct
{ 394: uint32_t : 12; 395:
__IO
uint32_t dbgromaddr : 20; 396: } CA5_MISC_CTRL2_bits; 397: }; 398: 399:
union
{ 400:
__IO
uint32_t CA5_MISC_CTRL3; 401: 402:
struct
{ 403: uint32_t : 12; 404:
__IO
uint32_t dbgselfaddr : 20; 405: } CA5_MISC_CTRL3_bits; 406: }; 407: 408:
union
{ 409:
__IO
uint32_t CA5_MISC_CTRL4; 410: 411:
struct
{ 412: uint32_t : 13; 413:
__IO
uint32_t periphbase : 19; 414: } CA5_MISC_CTRL4_bits; 415: }; 416: 417:
union
{ 418:
__IO
uint32_t CA5_MISC_CTRL5; 419: 420:
struct
{ 421:
__IO
uint32_t L2waysize : 3; 422: uint32_t : 1; 423:
__IO
uint32_t L2associativity : 1; 424: uint32_t : 3; 425:
__IO
uint32_t L2spniden : 1; 426: uint32_t : 3; 427:
__IO
uint32_t L2filteren : 1; 428: } CA5_MISC_CTRL5_bits; 429: }; 430: 431:
union
{ 432:
__IO
uint32_t CA5_MISC_CTRL6; 433: 434:
struct
{ 435: uint32_t : 12; 436:
__IO
uint32_t L2periphbase : 20; 437: } CA5_MISC_CTRL6_bits; 438: }; 439: 440:
union
{ 441:
__IO
uint32_t CA5_MISC_CTRL7; 442: 443:
struct
{ 444:
__IO
uint32_t L2filterstart : 12; 445: uint32_t : 4; 446:
__IO
uint32_t L2filterend : 12; 447: } CA5_MISC_CTRL7_bits; 448: }; 449: 450:
union
{ 451:
__IO
uint32_t CA5_MISC_CTRL8; 452: 453:
struct
{ 454:
__IO
uint32_t portconnected : 8; 455:
__IO
uint32_t portenabled : 8; 456:
__IO
uint32_t srstconnected : 8; 457:
__IO
uint32_t CP15Sdisable : 4; 458:
__IO
uint32_t L1rstdisable : 4; 459: } CA5_MISC_CTRL8_bits; 460: }; 461: 462:
union
{ 463:
__IO
uint32_t CA5_MISC_CTRL9; 464: 465:
struct
{ 466:
__IO
uint32_t pwrctli0 : 2; 467: uint32_t : 2; 468:
__IO
uint32_t pwrctli1 : 2; 469: uint32_t : 2; 470:
__IO
uint32_t pwrctli2 : 2; 471: uint32_t : 2; 472:
__IO
uint32_t pwrctli3 : 2; 473: uint32_t : 2; 474:
__IO
uint32_t atb_csysreq : 4; 475:
__IO
uint32_t atb_mstclamp : 4; 476:
__IO
uint32_t atb_slvclamp : 4; 477: } CA5_MISC_CTRL9_bits; 478: }; 479: 480:
union
{ 481:
__IO
uint32_t CA5_MISC_CTRL10; 482: 483:
struct
{ 484:
__IO
uint32_t eventi : 1; 485: uint32_t : 3; 486:
__IO
uint32_t maxextin : 3; 487: uint32_t : 1; 488:
__IO
uint32_t maxextout : 2; 489: uint32_t : 2; 490:
__IO
uint32_t niden : 4; 491:
__IO
uint32_t spiden : 4; 492:
__IO
uint32_t spniden : 4; 493: } CA5_MISC_CTRL10_bits; 494: }; 495: 496:
union
{ 497:
__IO
uint32_t CA5_MISC_CTRL11; 498: 499:
struct
{ 500:
__IO
uint32_t ARusers : 1; 501: uint32_t : 7; 502:
__IO
uint32_t AWusers : 1; 503: uint32_t : 7; 504:
__IO
uint32_t ARprots : 3; 505: uint32_t : 1; 506:
__IO
uint32_t AWprots : 3; 507: } CA5_MISC_CTRL11_bits; 508: }; 509: 510:
__I
uint32_t RESERVED10[1]; 511: 512:
union
{ 513:
__IO
uint32_t VIDEOADC_MISC_CTRL1; 514: 515:
struct
{ 516:
__IO
uint32_t ENABLE : 1; 517: uint32_t : 3; 518:
__IO
uint32_t CLAMP_EN0 : 1; 519: uint32_t : 3; 520:
__IO
uint32_t CLAMP_EN1 : 1; 521: uint32_t : 3; 522:
__IO
uint32_t CLAMP_EN2 : 1; 523: uint32_t : 3; 524:
__IO
uint32_t CLAMP_EN3 : 1; 525: } VIDEOADC_MISC_CTRL1_bits; 526: }; 527: 528:
union
{ 529:
__IO
uint32_t VIDEOADC_MISC_CTRL2; 530: 531:
struct
{ 532: uint32_t : 1; 533:
__IO
uint32_t CH0_ENABLE : 1; 534:
__IO
uint32_t CH1_ENABLE : 1; 535:
__IO
uint32_t CH2_ENABLE : 1; 536:
__IO
uint32_t CH3_ENABLE : 1; 537: uint32_t : 1; 538:
__IO
uint32_t CLAMP_IMP : 2; 539:
__IO
uint32_t CH0_CLAMP : 8; 540:
__IO
uint32_t CH1_CLAMP : 8; 541:
__IO
uint32_t CH2_CLAMP : 8; 542: } VIDEOADC_MISC_CTRL2_bits; 543: }; 544: 545:
union
{ 546:
__IO
uint32_t VIDEOADC_MISC_CTRL3; 547: 548:
struct
{ 549:
__IO
uint32_t CH3_CLAMP : 8; 550:
__IO
uint32_t CH0_GAIN : 4; 551: uint32_t : 4; 552:
__IO
uint32_t CH1_GAIN : 4; 553: uint32_t : 4; 554:
__IO
uint32_t CH2_GAIN : 4; 555: } VIDEOADC_MISC_CTRL3_bits; 556: }; 557: 558:
union
{ 559:
__IO
uint32_t VIDEOADC_MISC_CTRL4; 560: 561:
struct
{ 562:
__IO
uint32_t CH3_GAIN : 4; 563: uint32_t : 14; 564:
__IO
uint32_t QUAN_BIAS_UP : 2; 565: uint32_t : 4; 566:
__IO
uint32_t AAF_CTRL : 6; 567: } VIDEOADC_MISC_CTRL4_bits; 568: }; 569: 570:
union
{ 571:
__IO
uint32_t VIDEOADC_MISC_CTRL5; 572: 573:
struct
{ 574: uint32_t : 2; 575:
__IO
uint32_t REF_BIAS_UP : 2; 576: uint32_t : 14; 577:
__IO
uint32_t INPUT_RANGE : 2; 578: } VIDEOADC_MISC_CTRL5_bits; 579: }; 580: 581:
__I
uint32_t RESERVED11[1]; 582: 583:
union
{ 584:
__IO
uint32_t LVDS_TX_SETUP; 585: 586:
struct
{ 587:
__IO
uint32_t RF_0 : 1; 588: uint32_t : 3; 589:
__IO
uint32_t RF_1 : 1; 590: } LVDS_TX_SETUP_bits; 591: }; 592: 593:
__I
uint32_t RESERVED12[1]; 594: 595:
union
{ 596:
__IO
uint32_t USB_MISC_CTRL1; 597: 598:
struct
{ 599:
__IO
uint32_t CLK_SEL : 1; 600: uint32_t : 3; 601:
__IO
uint32_t CLK_DIV : 1; 602: uint32_t : 3; 603:
__I
uint32_t VPRTCT_state : 1; 604: uint32_t : 3; 605:
__I
uint32_t VBUS_outen : 1; 606: } USB_MISC_CTRL1_bits; 607: }; 608: 609:
union
{ 610:
__IO
uint32_t USB_MISC_CTRL2; 611: 612:
struct
{ 613:
__IO
uint32_t OSCOUTEN : 1; 614: uint32_t : 3; 615:
__IO
uint32_t XTLSEL : 1; 616: uint32_t : 3; 617:
__IO
uint32_t PLLALIV : 1; 618: uint32_t : 3; 619:
__IO
uint32_t OUTCLKSEL : 1; 620: uint32_t : 3; 621:
__IO
uint32_t TC_TB_TA : 3; 622: uint32_t : 5; 623:
__IO
uint32_t wakeup : 1; 624: uint32_t : 3; 625:
__IO
uint32_t suspendm : 1; 626: } USB_MISC_CTRL2_bits; 627: }; 628: 629:
union
{ 630:
__IO
uint32_t DDR_PHY_SETUP; 631: 632:
struct
{ 633:
__IO
uint32_t AFL_GAIN : 2; 634: uint32_t : 2; 635:
__IO
uint32_t PD_GAIN : 3; 636: } DDR_PHY_SETUP_bits; 637: }; 638: 639:
union
{ 640:
__IO
uint32_t BOOT_SWAP_CTRL; 641: 642:
struct
{ 643:
__IO
uint32_t BOOTSWAP : 1; 644: } BOOT_SWAP_CTRL_bits; 645: }; 646: 647:
union
{ 648:
__IO
uint32_t IDE_CLK_SEL; 649: 650:
struct
{ 651:
__IO
uint32_t IDECLK_SEL : 1; 652: } IDE_CLK_SEL_bits; 653: }; 654: 655: 656: }
AG903_SPC_Type
; 657: 658:
#define
AG903_SPC
((
volatile
AG903_SPC_Type
*)
AG903_SPC_BASE
) 659: 660: 661:
#define
AG903_SPC_BOOTUP_STATUS_HWR_POS
8 662:
#define
AG903_SPC_BOOTUP_STATUS_HWR_MSK
(0x1UL <<
AG903_SPC_BOOTUP_STATUS_HWR_POS
) 663:
#define
AG903_SPC_BOOTUP_STATUS_WDR_POS
9 664:
#define
AG903_SPC_BOOTUP_STATUS_WDR_MSK
(0x1UL <<
AG903_SPC_BOOTUP_STATUS_WDR_POS
) 665:
#define
AG903_SPC_BOOTUP_STATUS_PWR_POS
16 666:
#define
AG903_SPC_BOOTUP_STATUS_PWR_MSK
(0x1UL <<
AG903_SPC_BOOTUP_STATUS_PWR_POS
) 667: 668:
#define
AG903_SPC_FCS_CTRL_FCS_POS
6 669:
#define
AG903_SPC_FCS_CTRL_FCS_MSK
(0x1UL <<
AG903_SPC_FCS_CTRL_FCS_POS
) 670:
#define
AG903_SPC_FCS_CTRL_SW_RST_POS
10 671:
#define
AG903_SPC_FCS_CTRL_SW_RST_MSK
(0x1UL <<
AG903_SPC_FCS_CTRL_SW_RST_POS
) 672:
#define
AG903_SPC_FCS_CTRL_CPU_MASK_POS
12 673:
#define
AG903_SPC_FCS_CTRL_CPU_MASK_MSK
(0x1UL <<
AG903_SPC_FCS_CTRL_CPU_MASK_POS
) 674:
#define
AG903_SPC_FCS_CTRL_CPU_MASK2_POS
13 675:
#define
AG903_SPC_FCS_CTRL_CPU_MASK2_MSK
(0x1UL <<
AG903_SPC_FCS_CTRL_CPU_MASK2_POS
) 676:
#define
AG903_SPC_FCS_CTRL_FCS_PLL0_RSTn_POS
28 677:
#define
AG903_SPC_FCS_CTRL_FCS_PLL0_RSTn_MSK
(0x1UL <<
AG903_SPC_FCS_CTRL_FCS_PLL0_RSTn_POS
) 678:
#define
AG903_SPC_FCS_CTRL_SELFR_CMD_OFF_POS
31 679:
#define
AG903_SPC_FCS_CTRL_SELFR_CMD_OFF_MSK
(0x1UL <<
AG903_SPC_FCS_CTRL_SELFR_CMD_OFF_POS
) 680: 681:
#define
AG903_SPC_INT_STATUS_INT_FCS_POS
6 682:
#define
AG903_SPC_INT_STATUS_INT_FCS_MSK
(0x1UL <<
AG903_SPC_INT_STATUS_INT_FCS_POS
) 683: 684:
#define
AG903_SPC_INT_ENABLE_EINT_R0_POS
0 685:
#define
AG903_SPC_INT_ENABLE_EINT_R0_MSK
(0x1UL <<
AG903_SPC_INT_ENABLE_EINT_R0_POS
) 686:
#define
AG903_SPC_INT_ENABLE_EINT_R1_POS
1 687:
#define
AG903_SPC_INT_ENABLE_EINT_R1_MSK
(0x1UL <<
AG903_SPC_INT_ENABLE_EINT_R1_POS
) 688:
#define
AG903_SPC_INT_ENABLE_EINT_R3_POS
3 689:
#define
AG903_SPC_INT_ENABLE_EINT_R3_MSK
(0x1UL <<
AG903_SPC_INT_ENABLE_EINT_R3_POS
) 690:
#define
AG903_SPC_INT_ENABLE_EINT_R4_POS
4 691:
#define
AG903_SPC_INT_ENABLE_EINT_R4_MSK
(0x1UL <<
AG903_SPC_INT_ENABLE_EINT_R4_POS
) 692:
#define
AG903_SPC_INT_ENABLE_EINT_R5_POS
5 693:
#define
AG903_SPC_INT_ENABLE_EINT_R5_MSK
(0x1UL <<
AG903_SPC_INT_ENABLE_EINT_R5_POS
) 694:
#define
AG903_SPC_INT_ENABLE_EINT_FCS_POS
6 695:
#define
AG903_SPC_INT_ENABLE_EINT_FCS_MSK
(0x1UL <<
AG903_SPC_INT_ENABLE_EINT_FCS_POS
) 696:
#define
AG903_SPC_INT_ENABLE_EINT_R8_POS
8 697:
#define
AG903_SPC_INT_ENABLE_EINT_R8_MSK
(0x1UL <<
AG903_SPC_INT_ENABLE_EINT_R8_POS
) 698: 699:
#define
AG903_SPC_SOFTRESET_SETUP_SWRST_ACTIVE_POS
0 700:
#define
AG903_SPC_SOFTRESET_SETUP_SWRST_ACTIVE_MSK
(0x1fUL <<
AG903_SPC_SOFTRESET_SETUP_SWRST_ACTIVE_POS
) 701:
#define
AG903_SPC_SOFTRESET_SETUP_SWRST_WAIT_POS
16 702:
#define
AG903_SPC_SOFTRESET_SETUP_SWRST_WAIT_MSK
(0x1fUL <<
AG903_SPC_SOFTRESET_SETUP_SWRST_WAIT_POS
) 703: 704:
#define
AG903_SPC_PLL0_CTRL_EN_POS
0 705:
#define
AG903_SPC_PLL0_CTRL_EN_MSK
(0x1UL <<
AG903_SPC_PLL0_CTRL_EN_POS
) 706:
#define
AG903_SPC_PLL0_CTRL_STB_POS
1 707:
#define
AG903_SPC_PLL0_CTRL_STB_MSK
(0x1UL <<
AG903_SPC_PLL0_CTRL_STB_POS
) 708:
#define
AG903_SPC_PLL0_CTRL_MUX_POS
4 709:
#define
AG903_SPC_PLL0_CTRL_MUX_MSK
(0xfUL <<
AG903_SPC_PLL0_CTRL_MUX_POS
) 710:
#define
AG903_SPC_PLL0_CTRL_DIV_POS
8 711:
#define
AG903_SPC_PLL0_CTRL_DIV_MSK
(0x7UL <<
AG903_SPC_PLL0_CTRL_DIV_POS
) 712:
#define
AG903_SPC_PLL0_CTRL_MS_POS
16 713:
#define
AG903_SPC_PLL0_CTRL_MS_MSK
(0x1fUL <<
AG903_SPC_PLL0_CTRL_MS_POS
) 714:
#define
AG903_SPC_PLL0_CTRL_NS_POS
24 715:
#define
AG903_SPC_PLL0_CTRL_NS_MSK
(0x3fUL <<
AG903_SPC_PLL0_CTRL_NS_POS
) 716: 717:
#define
AG903_SPC_DDRPHY_PLLSETUP_PLLEN_POS
0 718:
#define
AG903_SPC_DDRPHY_PLLSETUP_PLLEN_MSK
(0x1UL <<
AG903_SPC_DDRPHY_PLLSETUP_PLLEN_POS
) 719: 720:
#define
AG903_SPC_DDRPHY_DLLSETUP_DLLEN_POS
0 721:
#define
AG903_SPC_DDRPHY_DLLSETUP_DLLEN_MSK
(0x1UL <<
AG903_SPC_DDRPHY_DLLSETUP_DLLEN_POS
) 722:
#define
AG903_SPC_DDRPHY_DLLSETUP_FRANGE_POS
8 723:
#define
AG903_SPC_DDRPHY_DLLSETUP_FRANGE_MSK
(0x7UL <<
AG903_SPC_DDRPHY_DLLSETUP_FRANGE_POS
) 724: 725:
#define
AG903_SPC_AHB_CLK_CTRL_HCLK_EN_POS
0 726:
#define
AG903_SPC_AHB_CLK_CTRL_HCLK_EN_MSK
(0xffffffffUL <<
AG903_SPC_AHB_CLK_CTRL_HCLK_EN_POS
) 727: 728:
#define
AG903_SPC_APB_CLK_CTRL_PCLK_EN_POS
0 729:
#define
AG903_SPC_APB_CLK_CTRL_PCLK_EN_MSK
(0xffffffffUL <<
AG903_SPC_APB_CLK_CTRL_PCLK_EN_POS
) 730: 731:
#define
AG903_SPC_AXI_CLK_CTRL1_ACLK_EN1_POS
0 732:
#define
AG903_SPC_AXI_CLK_CTRL1_ACLK_EN1_MSK
(0xffffffffUL <<
AG903_SPC_AXI_CLK_CTRL1_ACLK_EN1_POS
) 733: 734:
#define
AG903_SPC_AXI_CLK_CTRL2_ACLK_EN2_POS
0 735:
#define
AG903_SPC_AXI_CLK_CTRL2_ACLK_EN2_MSK
(0x1fffUL <<
AG903_SPC_AXI_CLK_CTRL2_ACLK_EN2_POS
) 736: 737:
#define
AG903_SPC_PLL1_CTRL_MS_POS
0 738:
#define
AG903_SPC_PLL1_CTRL_MS_MSK
(0x3fUL <<
AG903_SPC_PLL1_CTRL_MS_POS
) 739:
#define
AG903_SPC_PLL1_CTRL_NS_POS
8 740:
#define
AG903_SPC_PLL1_CTRL_NS_MSK
(0x3fUL <<
AG903_SPC_PLL1_CTRL_NS_POS
) 741:
#define
AG903_SPC_PLL1_CTRL_FR_POS
16 742:
#define
AG903_SPC_PLL1_CTRL_FR_MSK
(0x3UL <<
AG903_SPC_PLL1_CTRL_FR_POS
) 743:
#define
AG903_SPC_PLL1_CTRL_SRC_POS
20 744:
#define
AG903_SPC_PLL1_CTRL_SRC_MSK
(0x3UL <<
AG903_SPC_PLL1_CTRL_SRC_POS
) 745:
#define
AG903_SPC_PLL1_CTRL_DIV_POS
24 746:
#define
AG903_SPC_PLL1_CTRL_DIV_MSK
(0x7UL <<
AG903_SPC_PLL1_CTRL_DIV_POS
) 747:
#define
AG903_SPC_PLL1_CTRL_EN_POS
28 748:
#define
AG903_SPC_PLL1_CTRL_EN_MSK
(0x1UL <<
AG903_SPC_PLL1_CTRL_EN_POS
) 749: 750:
#define
AG903_SPC_PLL2_CTRL_MS_POS
0 751:
#define
AG903_SPC_PLL2_CTRL_MS_MSK
(0x3fUL <<
AG903_SPC_PLL2_CTRL_MS_POS
) 752:
#define
AG903_SPC_PLL2_CTRL_NS_POS
8 753:
#define
AG903_SPC_PLL2_CTRL_NS_MSK
(0x3fUL <<
AG903_SPC_PLL2_CTRL_NS_POS
) 754:
#define
AG903_SPC_PLL2_CTRL_FR_POS
16 755:
#define
AG903_SPC_PLL2_CTRL_FR_MSK
(0x3UL <<
AG903_SPC_PLL2_CTRL_FR_POS
) 756:
#define
AG903_SPC_PLL2_CTRL_SRC_POS
20 757:
#define
AG903_SPC_PLL2_CTRL_SRC_MSK
(0x3UL <<
AG903_SPC_PLL2_CTRL_SRC_POS
) 758:
#define
AG903_SPC_PLL2_CTRL_DIV_POS
24 759:
#define
AG903_SPC_PLL2_CTRL_DIV_MSK
(0x7UL <<
AG903_SPC_PLL2_CTRL_DIV_POS
) 760:
#define
AG903_SPC_PLL2_CTRL_EN_POS
28 761:
#define
AG903_SPC_PLL2_CTRL_EN_MSK
(0x1UL <<
AG903_SPC_PLL2_CTRL_EN_POS
) 762: 763:
#define
AG903_SPC_PLL3_CTRL_MS_POS
0 764:
#define
AG903_SPC_PLL3_CTRL_MS_MSK
(0x3fUL <<
AG903_SPC_PLL3_CTRL_MS_POS
) 765:
#define
AG903_SPC_PLL3_CTRL_NS_POS
8 766:
#define
AG903_SPC_PLL3_CTRL_NS_MSK
(0x3fUL <<
AG903_SPC_PLL3_CTRL_NS_POS
) 767:
#define
AG903_SPC_PLL3_CTRL_FR_POS
16 768:
#define
AG903_SPC_PLL3_CTRL_FR_MSK
(0x3UL <<
AG903_SPC_PLL3_CTRL_FR_POS
) 769:
#define
AG903_SPC_PLL3_CTRL_SRC_POS
20 770:
#define
AG903_SPC_PLL3_CTRL_SRC_MSK
(0x3UL <<
AG903_SPC_PLL3_CTRL_SRC_POS
) 771:
#define
AG903_SPC_PLL3_CTRL_DIV_POS
24 772:
#define
AG903_SPC_PLL3_CTRL_DIV_MSK
(0x7UL <<
AG903_SPC_PLL3_CTRL_DIV_POS
) 773:
#define
AG903_SPC_PLL3_CTRL_EN_POS
28 774:
#define
AG903_SPC_PLL3_CTRL_EN_MSK
(0x1UL <<
AG903_SPC_PLL3_CTRL_EN_POS
) 775: 776:
#define
AG903_SPC_PLLA_CTRL_MS_POS
0 777:
#define
AG903_SPC_PLLA_CTRL_MS_MSK
(0xfUL <<
AG903_SPC_PLLA_CTRL_MS_POS
) 778:
#define
AG903_SPC_PLLA_CTRL_CC_POS
4 779:
#define
AG903_SPC_PLLA_CTRL_CC_MSK
(0x7UL <<
AG903_SPC_PLLA_CTRL_CC_POS
) 780:
#define
AG903_SPC_PLLA_CTRL_NS_POS
8 781:
#define
AG903_SPC_PLLA_CTRL_NS_MSK
(0xffUL <<
AG903_SPC_PLLA_CTRL_NS_POS
) 782:
#define
AG903_SPC_PLLA_CTRL_FR_POS
16 783:
#define
AG903_SPC_PLLA_CTRL_FR_MSK
(0x3UL <<
AG903_SPC_PLLA_CTRL_FR_POS
) 784:
#define
AG903_SPC_PLLA_CTRL_SRC_POS
20 785:
#define
AG903_SPC_PLLA_CTRL_SRC_MSK
(0x3UL <<
AG903_SPC_PLLA_CTRL_SRC_POS
) 786:
#define
AG903_SPC_PLLA_CTRL_DIV_POS
24 787:
#define
AG903_SPC_PLLA_CTRL_DIV_MSK
(0x7UL <<
AG903_SPC_PLLA_CTRL_DIV_POS
) 788:
#define
AG903_SPC_PLLA_CTRL_EN_POS
28 789:
#define
AG903_SPC_PLLA_CTRL_EN_MSK
(0x1UL <<
AG903_SPC_PLLA_CTRL_EN_POS
) 790: 791:
#define
AG903_SPC_SOFTRESET_MASK1_SWRST_MASK1_POS
0 792:
#define
AG903_SPC_SOFTRESET_MASK1_SWRST_MASK1_MSK
(0xffffffffUL <<
AG903_SPC_SOFTRESET_MASK1_SWRST_MASK1_POS
) 793: 794:
#define
AG903_SPC_SOFTRESET_MASK2_SWRST_MASK2_POS
0 795:
#define
AG903_SPC_SOFTRESET_MASK2_SWRST_MASK2_MSK
(0xffffffffUL <<
AG903_SPC_SOFTRESET_MASK2_SWRST_MASK2_POS
) 796: 797:
#define
AG903_SPC_SOFTRESET_MASK3_SWRST_MASK3_POS
0 798:
#define
AG903_SPC_SOFTRESET_MASK3_SWRST_MASK3_MSK
(0xffffffffUL <<
AG903_SPC_SOFTRESET_MASK3_SWRST_MASK3_POS
) 799: 800:
#define
AG903_SPC_SOFTRESET_MASK4_SWRST_MASK4_POS
0 801:
#define
AG903_SPC_SOFTRESET_MASK4_SWRST_MASK4_MSK
(0xffffffffUL <<
AG903_SPC_SOFTRESET_MASK4_SWRST_MASK4_POS
) 802: 803:
#define
AG903_SPC_SOFTRESET_MASK5_SWRST_MASK5_POS
0 804:
#define
AG903_SPC_SOFTRESET_MASK5_SWRST_MASK5_MSK
(0xffffffffUL <<
AG903_SPC_SOFTRESET_MASK5_SWRST_MASK5_POS
) 805: 806:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_PCLK_EN_POS
0 807:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_PCLK_EN_MSK
(0xffffffUL <<
AG903_SPC_APB_SDMC_CLK_CTRL_PCLK_EN_POS
) 808:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_SDMCCLK_EN_POS
24 809:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_SDMCCLK_EN_MSK
(0xffUL <<
AG903_SPC_APB_SDMC_CLK_CTRL_SDMCCLK_EN_POS
) 810: 811:
#define
AG903_SPC_MISC_CLK_CTRL_SCLK_EN_POS
0 812:
#define
AG903_SPC_MISC_CLK_CTRL_SCLK_EN_MSK
(0xffffffffUL <<
AG903_SPC_MISC_CLK_CTRL_SCLK_EN_POS
) 813: 814:
#define
AG903_SPC_PIN_STATUS_MODE_POS
0 815:
#define
AG903_SPC_PIN_STATUS_MODE_MSK
(0xfUL <<
AG903_SPC_PIN_STATUS_MODE_POS
) 816:
#define
AG903_SPC_PIN_STATUS_TEST_POS
4 817:
#define
AG903_SPC_PIN_STATUS_TEST_MSK
(0xfUL <<
AG903_SPC_PIN_STATUS_TEST_POS
) 818: 819:
#define
AG903_SPC_SDMC_MISC_CTRL_CLK_SEL_POS
0 820:
#define
AG903_SPC_SDMC_MISC_CTRL_CLK_SEL_MSK
(0x1UL <<
AG903_SPC_SDMC_MISC_CTRL_CLK_SEL_POS
) 821:
#define
AG903_SPC_SDMC_MISC_CTRL_SREF_REQ_POS
8 822:
#define
AG903_SPC_SDMC_MISC_CTRL_SREF_REQ_MSK
(0x1UL <<
AG903_SPC_SDMC_MISC_CTRL_SREF_REQ_POS
) 823:
#define
AG903_SPC_SDMC_MISC_CTRL_SREF_ACK_POS
12 824:
#define
AG903_SPC_SDMC_MISC_CTRL_SREF_ACK_MSK
(0x1UL <<
AG903_SPC_SDMC_MISC_CTRL_SREF_ACK_POS
) 825:
#define
AG903_SPC_SDMC_MISC_CTRL_WCLK_SEL_POS
16 826:
#define
AG903_SPC_SDMC_MISC_CTRL_WCLK_SEL_MSK
(0xfUL <<
AG903_SPC_SDMC_MISC_CTRL_WCLK_SEL_POS
) 827:
#define
AG903_SPC_SDMC_MISC_CTRL_RCLK_SEL_POS
20 828:
#define
AG903_SPC_SDMC_MISC_CTRL_RCLK_SEL_MSK
(0xfUL <<
AG903_SPC_SDMC_MISC_CTRL_RCLK_SEL_POS
) 829:
#define
AG903_SPC_SDMC_MISC_CTRL_HCLK_SEL_POS
24 830:
#define
AG903_SPC_SDMC_MISC_CTRL_HCLK_SEL_MSK
(0xfUL <<
AG903_SPC_SDMC_MISC_CTRL_HCLK_SEL_POS
) 831: 832:
#define
AG903_SPC_DDR_MISC_CTRL_REFRESH_POS
0 833:
#define
AG903_SPC_DDR_MISC_CTRL_REFRESH_MSK
(0x1UL <<
AG903_SPC_DDR_MISC_CTRL_REFRESH_POS
) 834:
#define
AG903_SPC_DDR_MISC_CTRL_INIT_OK_POS
8 835:
#define
AG903_SPC_DDR_MISC_CTRL_INIT_OK_MSK
(0x1UL <<
AG903_SPC_DDR_MISC_CTRL_INIT_OK_POS
) 836: 837:
#define
AG903_SPC_SPIROM_MISC_CTRL_ADDR_CYC_POS
0 838:
#define
AG903_SPC_SPIROM_MISC_CTRL_ADDR_CYC_MSK
(0x1UL <<
AG903_SPC_SPIROM_MISC_CTRL_ADDR_CYC_POS
) 839: 840:
#define
AG903_SPC_CLK_SEL1_HDACLK_SEL_POS
0 841:
#define
AG903_SPC_CLK_SEL1_HDACLK_SEL_MSK
(0x3UL <<
AG903_SPC_CLK_SEL1_HDACLK_SEL_POS
) 842:
#define
AG903_SPC_CLK_SEL1_DT0CLK_SEL_POS
4 843:
#define
AG903_SPC_CLK_SEL1_DT0CLK_SEL_MSK
(0x1UL <<
AG903_SPC_CLK_SEL1_DT0CLK_SEL_POS
) 844:
#define
AG903_SPC_CLK_SEL1_DT1CLK_SEL_POS
8 845:
#define
AG903_SPC_CLK_SEL1_DT1CLK_SEL_MSK
(0x3UL <<
AG903_SPC_CLK_SEL1_DT1CLK_SEL_POS
) 846:
#define
AG903_SPC_CLK_SEL1_LVDSCLK_SEL_POS
12 847:
#define
AG903_SPC_CLK_SEL1_LVDSCLK_SEL_MSK
(0x1UL <<
AG903_SPC_CLK_SEL1_LVDSCLK_SEL_POS
) 848:
#define
AG903_SPC_CLK_SEL1_CP0CLK_SEL_POS
16 849:
#define
AG903_SPC_CLK_SEL1_CP0CLK_SEL_MSK
(0x3UL <<
AG903_SPC_CLK_SEL1_CP0CLK_SEL_POS
) 850:
#define
AG903_SPC_CLK_SEL1_CP1CLK_SEL_POS
20 851:
#define
AG903_SPC_CLK_SEL1_CP1CLK_SEL_MSK
(0x3UL <<
AG903_SPC_CLK_SEL1_CP1CLK_SEL_POS
) 852: 853:
#define
AG903_SPC_CLK_SSP_SEL_SSP0CLK_SEL_POS
0 854:
#define
AG903_SPC_CLK_SSP_SEL_SSP0CLK_SEL_MSK
(0x7UL <<
AG903_SPC_CLK_SSP_SEL_SSP0CLK_SEL_POS
) 855:
#define
AG903_SPC_CLK_SSP_SEL_SSP1CLK_SEL_POS
4 856:
#define
AG903_SPC_CLK_SSP_SEL_SSP1CLK_SEL_MSK
(0x7UL <<
AG903_SPC_CLK_SSP_SEL_SSP1CLK_SEL_POS
) 857:
#define
AG903_SPC_CLK_SSP_SEL_SSP2CLK_SEL_POS
8 858:
#define
AG903_SPC_CLK_SSP_SEL_SSP2CLK_SEL_MSK
(0x7UL <<
AG903_SPC_CLK_SSP_SEL_SSP2CLK_SEL_POS
) 859:
#define
AG903_SPC_CLK_SSP_SEL_SSP3CLK_SEL_POS
12 860:
#define
AG903_SPC_CLK_SSP_SEL_SSP3CLK_SEL_MSK
(0x7UL <<
AG903_SPC_CLK_SSP_SEL_SSP3CLK_SEL_POS
) 861:
#define
AG903_SPC_CLK_SSP_SEL_PLL3CLK_SEL_POS
16 862:
#define
AG903_SPC_CLK_SSP_SEL_PLL3CLK_SEL_MSK
(0x3UL <<
AG903_SPC_CLK_SSP_SEL_PLL3CLK_SEL_POS
) 863: 864:
#define
AG903_SPC_CLK_SSP_DIV_SSP0CLK_DIV_POS
0 865:
#define
AG903_SPC_CLK_SSP_DIV_SSP0CLK_DIV_MSK
(0x1fUL <<
AG903_SPC_CLK_SSP_DIV_SSP0CLK_DIV_POS
) 866:
#define
AG903_SPC_CLK_SSP_DIV_SSP1CLK_DIV_POS
8 867:
#define
AG903_SPC_CLK_SSP_DIV_SSP1CLK_DIV_MSK
(0x1fUL <<
AG903_SPC_CLK_SSP_DIV_SSP1CLK_DIV_POS
) 868:
#define
AG903_SPC_CLK_SSP_DIV_SSP2CLK_DIV_POS
16 869:
#define
AG903_SPC_CLK_SSP_DIV_SSP2CLK_DIV_MSK
(0x1fUL <<
AG903_SPC_CLK_SSP_DIV_SSP2CLK_DIV_POS
) 870:
#define
AG903_SPC_CLK_SSP_DIV_SSP3CLK_DIV_POS
24 871:
#define
AG903_SPC_CLK_SSP_DIV_SSP3CLK_DIV_MSK
(0x1fUL <<
AG903_SPC_CLK_SSP_DIV_SSP3CLK_DIV_POS
) 872: 873:
#define
AG903_SPC_ETH_PHY_SEL_RMII_POS
0 874:
#define
AG903_SPC_ETH_PHY_SEL_RMII_MSK
(0x1UL <<
AG903_SPC_ETH_PHY_SEL_RMII_POS
) 875: 876:
#define
AG903_SPC_CA5_MISC_CTRL1_dbgen_POS
0 877:
#define
AG903_SPC_CA5_MISC_CTRL1_dbgen_MSK
(0xfUL <<
AG903_SPC_CA5_MISC_CTRL1_dbgen_POS
) 878:
#define
AG903_SPC_CA5_MISC_CTRL1_dbgrestart_POS
4 879:
#define
AG903_SPC_CA5_MISC_CTRL1_dbgrestart_MSK
(0xfUL <<
AG903_SPC_CA5_MISC_CTRL1_dbgrestart_POS
) 880:
#define
AG903_SPC_CA5_MISC_CTRL1_dbgromaddrv_POS
8 881:
#define
AG903_SPC_CA5_MISC_CTRL1_dbgromaddrv_MSK
(0x1UL <<
AG903_SPC_CA5_MISC_CTRL1_dbgromaddrv_POS
) 882:
#define
AG903_SPC_CA5_MISC_CTRL1_dbgselfaddrv_POS
12 883:
#define
AG903_SPC_CA5_MISC_CTRL1_dbgselfaddrv_MSK
(0x1UL <<
AG903_SPC_CA5_MISC_CTRL1_dbgselfaddrv_POS
) 884: 885:
#define
AG903_SPC_CA5_MISC_CTRL2_dbgromaddr_POS
12 886:
#define
AG903_SPC_CA5_MISC_CTRL2_dbgromaddr_MSK
(0xfffffUL <<
AG903_SPC_CA5_MISC_CTRL2_dbgromaddr_POS
) 887: 888:
#define
AG903_SPC_CA5_MISC_CTRL3_dbgselfaddr_POS
12 889:
#define
AG903_SPC_CA5_MISC_CTRL3_dbgselfaddr_MSK
(0xfffffUL <<
AG903_SPC_CA5_MISC_CTRL3_dbgselfaddr_POS
) 890: 891:
#define
AG903_SPC_CA5_MISC_CTRL4_periphbase_POS
13 892:
#define
AG903_SPC_CA5_MISC_CTRL4_periphbase_MSK
(0x7ffffUL <<
AG903_SPC_CA5_MISC_CTRL4_periphbase_POS
) 893: 894:
#define
AG903_SPC_CA5_MISC_CTRL5_L2waysize_POS
0 895:
#define
AG903_SPC_CA5_MISC_CTRL5_L2waysize_MSK
(0x7UL <<
AG903_SPC_CA5_MISC_CTRL5_L2waysize_POS
) 896:
#define
AG903_SPC_CA5_MISC_CTRL5_L2associativity_POS
4 897:
#define
AG903_SPC_CA5_MISC_CTRL5_L2associativity_MSK
(0x1UL <<
AG903_SPC_CA5_MISC_CTRL5_L2associativity_POS
) 898:
#define
AG903_SPC_CA5_MISC_CTRL5_L2spniden_POS
8 899:
#define
AG903_SPC_CA5_MISC_CTRL5_L2spniden_MSK
(0x1UL <<
AG903_SPC_CA5_MISC_CTRL5_L2spniden_POS
) 900:
#define
AG903_SPC_CA5_MISC_CTRL5_L2filteren_POS
12 901:
#define
AG903_SPC_CA5_MISC_CTRL5_L2filteren_MSK
(0x1UL <<
AG903_SPC_CA5_MISC_CTRL5_L2filteren_POS
) 902: 903:
#define
AG903_SPC_CA5_MISC_CTRL6_L2periphbase_POS
12 904:
#define
AG903_SPC_CA5_MISC_CTRL6_L2periphbase_MSK
(0xfffffUL <<
AG903_SPC_CA5_MISC_CTRL6_L2periphbase_POS
) 905: 906:
#define
AG903_SPC_CA5_MISC_CTRL7_L2filterstart_POS
0 907:
#define
AG903_SPC_CA5_MISC_CTRL7_L2filterstart_MSK
(0xfffUL <<
AG903_SPC_CA5_MISC_CTRL7_L2filterstart_POS
) 908:
#define
AG903_SPC_CA5_MISC_CTRL7_L2filterend_POS
16 909:
#define
AG903_SPC_CA5_MISC_CTRL7_L2filterend_MSK
(0xfffUL <<
AG903_SPC_CA5_MISC_CTRL7_L2filterend_POS
) 910: 911:
#define
AG903_SPC_CA5_MISC_CTRL8_portconnected_POS
0 912:
#define
AG903_SPC_CA5_MISC_CTRL8_portconnected_MSK
(0xffUL <<
AG903_SPC_CA5_MISC_CTRL8_portconnected_POS
) 913:
#define
AG903_SPC_CA5_MISC_CTRL8_portenabled_POS
8 914:
#define
AG903_SPC_CA5_MISC_CTRL8_portenabled_MSK
(0xffUL <<
AG903_SPC_CA5_MISC_CTRL8_portenabled_POS
) 915:
#define
AG903_SPC_CA5_MISC_CTRL8_srstconnected_POS
16 916:
#define
AG903_SPC_CA5_MISC_CTRL8_srstconnected_MSK
(0xffUL <<
AG903_SPC_CA5_MISC_CTRL8_srstconnected_POS
) 917:
#define
AG903_SPC_CA5_MISC_CTRL8_CP15Sdisable_POS
24 918:
#define
AG903_SPC_CA5_MISC_CTRL8_CP15Sdisable_MSK
(0xfUL <<
AG903_SPC_CA5_MISC_CTRL8_CP15Sdisable_POS
) 919:
#define
AG903_SPC_CA5_MISC_CTRL8_L1rstdisable_POS
28 920:
#define
AG903_SPC_CA5_MISC_CTRL8_L1rstdisable_MSK
(0xfUL <<
AG903_SPC_CA5_MISC_CTRL8_L1rstdisable_POS
) 921: 922:
#define
AG903_SPC_CA5_MISC_CTRL9_pwrctli0_POS
0 923:
#define
AG903_SPC_CA5_MISC_CTRL9_pwrctli0_MSK
(0x3UL <<
AG903_SPC_CA5_MISC_CTRL9_pwrctli0_POS
) 924:
#define
AG903_SPC_CA5_MISC_CTRL9_pwrctli1_POS
4 925:
#define
AG903_SPC_CA5_MISC_CTRL9_pwrctli1_MSK
(0x3UL <<
AG903_SPC_CA5_MISC_CTRL9_pwrctli1_POS
) 926:
#define
AG903_SPC_CA5_MISC_CTRL9_pwrctli2_POS
8 927:
#define
AG903_SPC_CA5_MISC_CTRL9_pwrctli2_MSK
(0x3UL <<
AG903_SPC_CA5_MISC_CTRL9_pwrctli2_POS
) 928:
#define
AG903_SPC_CA5_MISC_CTRL9_pwrctli3_POS
12 929:
#define
AG903_SPC_CA5_MISC_CTRL9_pwrctli3_MSK
(0x3UL <<
AG903_SPC_CA5_MISC_CTRL9_pwrctli3_POS
) 930:
#define
AG903_SPC_CA5_MISC_CTRL9_atb_csysreq_POS
16 931:
#define
AG903_SPC_CA5_MISC_CTRL9_atb_csysreq_MSK
(0xfUL <<
AG903_SPC_CA5_MISC_CTRL9_atb_csysreq_POS
) 932:
#define
AG903_SPC_CA5_MISC_CTRL9_atb_mstclamp_POS
20 933:
#define
AG903_SPC_CA5_MISC_CTRL9_atb_mstclamp_MSK
(0xfUL <<
AG903_SPC_CA5_MISC_CTRL9_atb_mstclamp_POS
) 934:
#define
AG903_SPC_CA5_MISC_CTRL9_atb_slvclamp_POS
24 935:
#define
AG903_SPC_CA5_MISC_CTRL9_atb_slvclamp_MSK
(0xfUL <<
AG903_SPC_CA5_MISC_CTRL9_atb_slvclamp_POS
) 936: 937:
#define
AG903_SPC_CA5_MISC_CTRL10_eventi_POS
0 938:
#define
AG903_SPC_CA5_MISC_CTRL10_eventi_MSK
(0x1UL <<
AG903_SPC_CA5_MISC_CTRL10_eventi_POS
) 939:
#define
AG903_SPC_CA5_MISC_CTRL10_maxextin_POS
4 940:
#define
AG903_SPC_CA5_MISC_CTRL10_maxextin_MSK
(0x7UL <<
AG903_SPC_CA5_MISC_CTRL10_maxextin_POS
) 941:
#define
AG903_SPC_CA5_MISC_CTRL10_maxextout_POS
8 942:
#define
AG903_SPC_CA5_MISC_CTRL10_maxextout_MSK
(0x3UL <<
AG903_SPC_CA5_MISC_CTRL10_maxextout_POS
) 943:
#define
AG903_SPC_CA5_MISC_CTRL10_niden_POS
12 944:
#define
AG903_SPC_CA5_MISC_CTRL10_niden_MSK
(0xfUL <<
AG903_SPC_CA5_MISC_CTRL10_niden_POS
) 945:
#define
AG903_SPC_CA5_MISC_CTRL10_spiden_POS
16 946:
#define
AG903_SPC_CA5_MISC_CTRL10_spiden_MSK
(0xfUL <<
AG903_SPC_CA5_MISC_CTRL10_spiden_POS
) 947:
#define
AG903_SPC_CA5_MISC_CTRL10_spniden_POS
20 948:
#define
AG903_SPC_CA5_MISC_CTRL10_spniden_MSK
(0xfUL <<
AG903_SPC_CA5_MISC_CTRL10_spniden_POS
) 949: 950:
#define
AG903_SPC_CA5_MISC_CTRL11_ARusers_POS
0 951:
#define
AG903_SPC_CA5_MISC_CTRL11_ARusers_MSK
(0x1UL <<
AG903_SPC_CA5_MISC_CTRL11_ARusers_POS
) 952:
#define
AG903_SPC_CA5_MISC_CTRL11_AWusers_POS
8 953:
#define
AG903_SPC_CA5_MISC_CTRL11_AWusers_MSK
(0x1UL <<
AG903_SPC_CA5_MISC_CTRL11_AWusers_POS
) 954:
#define
AG903_SPC_CA5_MISC_CTRL11_ARprots_POS
16 955:
#define
AG903_SPC_CA5_MISC_CTRL11_ARprots_MSK
(0x7UL <<
AG903_SPC_CA5_MISC_CTRL11_ARprots_POS
) 956:
#define
AG903_SPC_CA5_MISC_CTRL11_AWprots_POS
20 957:
#define
AG903_SPC_CA5_MISC_CTRL11_AWprots_MSK
(0x7UL <<
AG903_SPC_CA5_MISC_CTRL11_AWprots_POS
) 958: 959:
#define
AG903_SPC_VIDEOADC_MISC_CTRL1_ENABLE_POS
0 960:
#define
AG903_SPC_VIDEOADC_MISC_CTRL1_ENABLE_MSK
(0x1UL <<
AG903_SPC_VIDEOADC_MISC_CTRL1_ENABLE_POS
) 961:
#define
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN0_POS
4 962:
#define
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN0_MSK
(0x1UL <<
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN0_POS
) 963:
#define
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN1_POS
8 964:
#define
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN1_MSK
(0x1UL <<
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN1_POS
) 965:
#define
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN2_POS
12 966:
#define
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN2_MSK
(0x1UL <<
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN2_POS
) 967:
#define
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN3_POS
16 968:
#define
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN3_MSK
(0x1UL <<
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN3_POS
) 969: 970:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_ENABLE_POS
1 971:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_ENABLE_MSK
(0x1UL <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_ENABLE_POS
) 972:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_ENABLE_POS
2 973:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_ENABLE_MSK
(0x1UL <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_ENABLE_POS
) 974:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_ENABLE_POS
3 975:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_ENABLE_MSK
(0x1UL <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_ENABLE_POS
) 976:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH3_ENABLE_POS
4 977:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH3_ENABLE_MSK
(0x1UL <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH3_ENABLE_POS
) 978:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CLAMP_IMP_POS
6 979:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CLAMP_IMP_MSK
(0x3UL <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CLAMP_IMP_POS
) 980:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_CLAMP_POS
8 981:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_CLAMP_MSK
(0xffUL <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_CLAMP_POS
) 982:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_CLAMP_POS
16 983:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_CLAMP_MSK
(0xffUL <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_CLAMP_POS
) 984:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_CLAMP_POS
24 985:
#define
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_CLAMP_MSK
(0xffUL <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_CLAMP_POS
) 986: 987:
#define
AG903_SPC_VIDEOADC_MISC_CTRL3_CH3_CLAMP_POS
0 988:
#define
AG903_SPC_VIDEOADC_MISC_CTRL3_CH3_CLAMP_MSK
(0xffUL <<
AG903_SPC_VIDEOADC_MISC_CTRL3_CH3_CLAMP_POS
) 989:
#define
AG903_SPC_VIDEOADC_MISC_CTRL3_CH0_GAIN_POS
8 990:
#define
AG903_SPC_VIDEOADC_MISC_CTRL3_CH0_GAIN_MSK
(0xfUL <<
AG903_SPC_VIDEOADC_MISC_CTRL3_CH0_GAIN_POS
) 991:
#define
AG903_SPC_VIDEOADC_MISC_CTRL3_CH1_GAIN_POS
16 992:
#define
AG903_SPC_VIDEOADC_MISC_CTRL3_CH1_GAIN_MSK
(0xfUL <<
AG903_SPC_VIDEOADC_MISC_CTRL3_CH1_GAIN_POS
) 993:
#define
AG903_SPC_VIDEOADC_MISC_CTRL3_CH2_GAIN_POS
24 994:
#define
AG903_SPC_VIDEOADC_MISC_CTRL3_CH2_GAIN_MSK
(0xfUL <<
AG903_SPC_VIDEOADC_MISC_CTRL3_CH2_GAIN_POS
) 995: 996:
#define
AG903_SPC_VIDEOADC_MISC_CTRL4_CH3_GAIN_POS
0 997:
#define
AG903_SPC_VIDEOADC_MISC_CTRL4_CH3_GAIN_MSK
(0xfUL <<
AG903_SPC_VIDEOADC_MISC_CTRL4_CH3_GAIN_POS
) 998:
#define
AG903_SPC_VIDEOADC_MISC_CTRL4_QUAN_BIAS_UP_POS
18 999:
#define
AG903_SPC_VIDEOADC_MISC_CTRL4_QUAN_BIAS_UP_MSK
(0x3UL <<
AG903_SPC_VIDEOADC_MISC_CTRL4_QUAN_BIAS_UP_POS
) 1000:
#define
AG903_SPC_VIDEOADC_MISC_CTRL4_AAF_CTRL_POS
24 1001:
#define
AG903_SPC_VIDEOADC_MISC_CTRL4_AAF_CTRL_MSK
(0x3fUL <<
AG903_SPC_VIDEOADC_MISC_CTRL4_AAF_CTRL_POS
) 1002: 1003:
#define
AG903_SPC_VIDEOADC_MISC_CTRL5_REF_BIAS_UP_POS
2 1004:
#define
AG903_SPC_VIDEOADC_MISC_CTRL5_REF_BIAS_UP_MSK
(0x3UL <<
AG903_SPC_VIDEOADC_MISC_CTRL5_REF_BIAS_UP_POS
) 1005:
#define
AG903_SPC_VIDEOADC_MISC_CTRL5_INPUT_RANGE_POS
18 1006:
#define
AG903_SPC_VIDEOADC_MISC_CTRL5_INPUT_RANGE_MSK
(0x3UL <<
AG903_SPC_VIDEOADC_MISC_CTRL5_INPUT_RANGE_POS
) 1007: 1008:
#define
AG903_SPC_LVDS_TX_SETUP_RF_0_POS
0 1009:
#define
AG903_SPC_LVDS_TX_SETUP_RF_0_MSK
(0x1UL <<
AG903_SPC_LVDS_TX_SETUP_RF_0_POS
) 1010:
#define
AG903_SPC_LVDS_TX_SETUP_RF_1_POS
4 1011:
#define
AG903_SPC_LVDS_TX_SETUP_RF_1_MSK
(0x1UL <<
AG903_SPC_LVDS_TX_SETUP_RF_1_POS
) 1012: 1013:
#define
AG903_SPC_USB_MISC_CTRL1_CLK_SEL_POS
0 1014:
#define
AG903_SPC_USB_MISC_CTRL1_CLK_SEL_MSK
(0x1UL <<
AG903_SPC_USB_MISC_CTRL1_CLK_SEL_POS
) 1015:
#define
AG903_SPC_USB_MISC_CTRL1_CLK_DIV_POS
4 1016:
#define
AG903_SPC_USB_MISC_CTRL1_CLK_DIV_MSK
(0x1UL <<
AG903_SPC_USB_MISC_CTRL1_CLK_DIV_POS
) 1017:
#define
AG903_SPC_USB_MISC_CTRL1_VPRTCT_state_POS
8 1018:
#define
AG903_SPC_USB_MISC_CTRL1_VPRTCT_state_MSK
(0x1UL <<
AG903_SPC_USB_MISC_CTRL1_VPRTCT_state_POS
) 1019:
#define
AG903_SPC_USB_MISC_CTRL1_VBUS_outen_POS
12 1020:
#define
AG903_SPC_USB_MISC_CTRL1_VBUS_outen_MSK
(0x1UL <<
AG903_SPC_USB_MISC_CTRL1_VBUS_outen_POS
) 1021: 1022:
#define
AG903_SPC_USB_MISC_CTRL2_OSCOUTEN_POS
0 1023:
#define
AG903_SPC_USB_MISC_CTRL2_OSCOUTEN_MSK
(0x1UL <<
AG903_SPC_USB_MISC_CTRL2_OSCOUTEN_POS
) 1024:
#define
AG903_SPC_USB_MISC_CTRL2_XTLSEL_POS
4 1025:
#define
AG903_SPC_USB_MISC_CTRL2_XTLSEL_MSK
(0x1UL <<
AG903_SPC_USB_MISC_CTRL2_XTLSEL_POS
) 1026:
#define
AG903_SPC_USB_MISC_CTRL2_PLLALIV_POS
8 1027:
#define
AG903_SPC_USB_MISC_CTRL2_PLLALIV_MSK
(0x1UL <<
AG903_SPC_USB_MISC_CTRL2_PLLALIV_POS
) 1028:
#define
AG903_SPC_USB_MISC_CTRL2_OUTCLKSEL_POS
12 1029:
#define
AG903_SPC_USB_MISC_CTRL2_OUTCLKSEL_MSK
(0x1UL <<
AG903_SPC_USB_MISC_CTRL2_OUTCLKSEL_POS
) 1030:
#define
AG903_SPC_USB_MISC_CTRL2_TC_TB_TA_POS
16 1031:
#define
AG903_SPC_USB_MISC_CTRL2_TC_TB_TA_MSK
(0x7UL <<
AG903_SPC_USB_MISC_CTRL2_TC_TB_TA_POS
) 1032:
#define
AG903_SPC_USB_MISC_CTRL2_wakeup_POS
24 1033:
#define
AG903_SPC_USB_MISC_CTRL2_wakeup_MSK
(0x1UL <<
AG903_SPC_USB_MISC_CTRL2_wakeup_POS
) 1034:
#define
AG903_SPC_USB_MISC_CTRL2_suspendm_POS
28 1035:
#define
AG903_SPC_USB_MISC_CTRL2_suspendm_MSK
(0x1UL <<
AG903_SPC_USB_MISC_CTRL2_suspendm_POS
) 1036: 1037:
#define
AG903_SPC_DDR_PHY_SETUP_AFL_GAIN_POS
0 1038:
#define
AG903_SPC_DDR_PHY_SETUP_AFL_GAIN_MSK
(0x3UL <<
AG903_SPC_DDR_PHY_SETUP_AFL_GAIN_POS
) 1039:
#define
AG903_SPC_DDR_PHY_SETUP_PD_GAIN_POS
4 1040:
#define
AG903_SPC_DDR_PHY_SETUP_PD_GAIN_MSK
(0x7UL <<
AG903_SPC_DDR_PHY_SETUP_PD_GAIN_POS
) 1041: 1042:
#define
AG903_SPC_BOOT_SWAP_CTRL_BOOTSWAP_POS
0 1043:
#define
AG903_SPC_BOOT_SWAP_CTRL_BOOTSWAP_MSK
(0x1UL <<
AG903_SPC_BOOT_SWAP_CTRL_BOOTSWAP_POS
) 1044: 1045:
#define
AG903_SPC_IDE_CLK_SEL_IDECLK_SEL_POS
0 1046:
#define
AG903_SPC_IDE_CLK_SEL_IDECLK_SEL_MSK
(0x1UL <<
AG903_SPC_IDE_CLK_SEL_IDECLK_SEL_POS
) 1047: 1048: 1049:
#endif
1050:
Copyright (c) 2017-2025 Axell Corporation. All rights reserved.
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