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AG903_vidreg.h

VID Register Definition

VID Register Definition

none

AXELL CORPORATION

2017_10_20 Auto-generated.

1: 8: 9: 13: 14: #ifndef _AG903_VID_REGMAP_H_ 15: #define _AG903_VID_REGMAP_H_ 16: 17: 18: #include "AG903_regmap.h" 19: 20: #ifndef __I 21: 22: #define __I volatile const 23: #endif 24: #ifndef __O 25: 26: #define __O volatile 27: #endif 28: #ifndef __IO 29: 30: #define __IO volatile 31: #endif 32: 33: 34: typedef struct { 35: 36: union { 37: __IO uint32_t CTRL; 38: 39: struct { 40: __IO uint32_t ON : 1; 41: } CTRL_bits; 42: }; 43: 44: union { 45: __IO uint32_t FMT; 46: 47: struct { 48: __IO uint32_t FMT : 3; 49: } FMT_bits; 50: }; 51: 52: 53: }AG903_VID_Type; 54: 55: 56: typedef struct { 57: 58: union { 59: __IO uint32_t CTRL; 60: 61: struct { 62: __IO uint32_t SOE : 1; 63: } CTRL_bits; 64: }; 65: 66: union { 67: __IO uint32_t MOD; 68: 69: struct { 70: __IO uint32_t CPOL : 1; 71: __IO uint32_t FPOL : 1; 72: __IO uint32_t DPOL : 1; 73: __IO uint32_t HPOL : 1; 74: __IO uint32_t VPOL : 1; 75: } MOD_bits; 76: }; 77: 78: union { 79: __IO uint32_t OHPRM0; 80: 81: struct { 82: __IO uint32_t HPW : 12; 83: } OHPRM0_bits; 84: }; 85: 86: union { 87: __IO uint32_t OHPRM1; 88: 89: struct { 90: __IO uint32_t HBP : 12; 91: uint32_t : 4; 92: __IO uint32_t HFP : 12; 93: } OHPRM1_bits; 94: }; 95: 96: union { 97: __IO uint32_t OVPRM0; 98: 99: struct { 100: __IO uint32_t VPW : 12; 101: } OVPRM0_bits; 102: }; 103: 104: union { 105: __IO uint32_t OVPRM1; 106: 107: struct { 108: __IO uint32_t VBP : 12; 109: uint32_t : 4; 110: __IO uint32_t VFP : 12; 111: } OVPRM1_bits; 112: }; 113: 114: union { 115: __IO uint32_t OSIZE; 116: 117: struct { 118: __IO uint32_t HFS : 12; 119: uint32_t : 4; 120: __IO uint32_t VFS : 12; 121: } OSIZE_bits; 122: }; 123: 124: union { 125: __I uint32_t STAT; 126: 127: struct { 128: __I uint32_t CWT : 1; 129: } STAT_bits; 130: }; 131: 132: 133: }AG903_VIDIOn_Type; 134: 135: 136: typedef struct { 137: 138: union { 139: __IO uint32_t MOD; 140: 141: struct { 142: __IO uint32_t TRSDEC : 1; 143: uint32_t : 15; 144: __IO uint32_t DELAY : 1; 145: uint32_t : 7; 146: __IO uint32_t TDMTRS : 1; 147: __IO uint32_t TDMBLK : 1; 148: } MOD_bits; 149: }; 150: 151: union { 152: __IO uint32_t TRSPRM; 153: 154: struct { 155: __IO uint32_t HFP : 12; 156: __IO uint32_t HREF : 1; 157: uint32_t : 3; 158: __IO uint32_t VFP : 12; 159: __IO uint32_t OFP : 1; 160: __IO uint32_t EFP : 1; 161: } TRSPRM_bits; 162: }; 163: 164: union { 165: __IO uint32_t SDPRM; 166: 167: struct { 168: __IO uint32_t HMAX : 13; 169: uint32_t : 3; 170: __IO uint32_t VMAX : 13; 171: } SDPRM_bits; 172: }; 173: 174: union { 175: __I uint32_t STAT; 176: 177: struct { 178: __I uint32_t TDMCH : 3; 179: uint32_t : 5; 180: __I uint32_t HBLANK : 1; 181: __I uint32_t VBLANK : 1; 182: uint32_t : 6; 183: __I uint32_t TRSVAL : 8; 184: __I uint32_t BLKVAL : 8; 185: } STAT_bits; 186: }; 187: 188: union { 189: __I uint32_t HST0; 190: 191: struct { 192: __I uint32_t HPW : 13; 193: } HST0_bits; 194: }; 195: 196: union { 197: __I uint32_t HST1; 198: 199: struct { 200: __I uint32_t HBP : 13; 201: uint32_t : 3; 202: __I uint32_t HFP : 13; 203: } HST1_bits; 204: }; 205: 206: union { 207: __I uint32_t VST0; 208: 209: struct { 210: __I uint32_t VPW : 13; 211: uint32_t : 3; 212: __I uint32_t OFP : 1; 213: __I uint32_t OBP : 1; 214: __I uint32_t EFP : 1; 215: __I uint32_t EBP : 1; 216: __I uint32_t SCAN : 1; 217: } VST0_bits; 218: }; 219: 220: union { 221: __I uint32_t VST1; 222: 223: struct { 224: __I uint32_t VBP : 13; 225: uint32_t : 3; 226: __I uint32_t VFP : 13; 227: } VST1_bits; 228: }; 229: 230: union { 231: __I uint32_t FST; 232: 233: struct { 234: __I uint32_t HFS : 13; 235: uint32_t : 3; 236: __I uint32_t VFS : 13; 237: } FST_bits; 238: }; 239: 240: 241: }AG903_VIDCOn_Type; 242: 243: #define AG903_VIDIOn(ch) ((volatile AG903_VIDIOn_Type *)(AG903_VIDIO0_BASE + 0x40 * ch)) 244: #define AG903_VIDIOn_CTRL(ch) AG903_VIDIOn(ch)->CTRL 245: #define AG903_VIDIOn_MOD(ch) AG903_VIDIOn(ch)->MOD 246: #define AG903_VIDIOn_OHPRM0(ch) AG903_VIDIOn(ch)->OHPRM0 247: #define AG903_VIDIOn_OHPRM1(ch) AG903_VIDIOn(ch)->OHPRM1 248: #define AG903_VIDIOn_OVPRM0(ch) AG903_VIDIOn(ch)->OVPRM0 249: #define AG903_VIDIOn_OVPRM1(ch) AG903_VIDIOn(ch)->OVPRM1 250: #define AG903_VIDIOn_OSIZE(ch) AG903_VIDIOn(ch)->OSIZE 251: #define AG903_VIDIOn_STAT(ch) AG903_VIDIOn(ch)->STAT 252: 253: #define AG903_VIDCOn(ch) ((volatile AG903_VIDCOn_Type *)(AG903_VIDCO0_BASE + 0x40 * ch)) 254: #define AG903_VIDCOn_MOD(ch) AG903_VIDCOn(ch)->MOD 255: #define AG903_VIDCOn_TRSPRM(ch) AG903_VIDCOn(ch)->TRSPRM 256: #define AG903_VIDCOn_SDPRM(ch) AG903_VIDCOn(ch)->SDPRM 257: #define AG903_VIDCOn_STAT(ch) AG903_VIDCOn(ch)->STAT 258: #define AG903_VIDCOn_HST0(ch) AG903_VIDCOn(ch)->HST0 259: #define AG903_VIDCOn_HST1(ch) AG903_VIDCOn(ch)->HST1 260: #define AG903_VIDCOn_VST0(ch) AG903_VIDCOn(ch)->VST0 261: #define AG903_VIDCOn_VST1(ch) AG903_VIDCOn(ch)->VST1 262: #define AG903_VIDCOn_FST(ch) AG903_VIDCOn(ch)->FST 263: 264: #define AG903_VID ((volatile AG903_VID_Type *) AG903_VID_BASE) 265: #define AG903_VIDIO0 ((volatile AG903_VIDIOn_Type *) AG903_VIDIO0_BASE) 266: #define AG903_VIDIO1 ((volatile AG903_VIDIOn_Type *) AG903_VIDIO1_BASE) 267: #define AG903_VIDCO0 ((volatile AG903_VIDCOn_Type *) AG903_VIDCO0_BASE) 268: #define AG903_VIDCO1 ((volatile AG903_VIDCOn_Type *) AG903_VIDCO1_BASE) 269: #define AG903_VIDCO2 ((volatile AG903_VIDCOn_Type *) AG903_VIDCO2_BASE) 270: #define AG903_VIDCO3 ((volatile AG903_VIDCOn_Type *) AG903_VIDCO3_BASE) 271: 272: 273: #define AG903_VID_CTRL_ON_POS 0 274: #define AG903_VID_CTRL_ON_MSK (0x1UL << AG903_VID_CTRL_ON_POS) 275: 276: #define AG903_VID_FMT_FMT_POS 0 277: #define AG903_VID_FMT_FMT_MSK (0x7UL << AG903_VID_FMT_FMT_POS) 278: 279: #define AG903_VIDIOn_CTRL_SOE_POS 0 280: #define AG903_VIDIOn_CTRL_SOE_MSK (0x1UL << AG903_VIDIOn_CTRL_SOE_POS) 281: 282: #define AG903_VIDIOn_MOD_CPOL_POS 0 283: #define AG903_VIDIOn_MOD_CPOL_MSK (0x1UL << AG903_VIDIOn_MOD_CPOL_POS) 284: #define AG903_VIDIOn_MOD_FPOL_POS 1 285: #define AG903_VIDIOn_MOD_FPOL_MSK (0x1UL << AG903_VIDIOn_MOD_FPOL_POS) 286: #define AG903_VIDIOn_MOD_DPOL_POS 2 287: #define AG903_VIDIOn_MOD_DPOL_MSK (0x1UL << AG903_VIDIOn_MOD_DPOL_POS) 288: #define AG903_VIDIOn_MOD_HPOL_POS 3 289: #define AG903_VIDIOn_MOD_HPOL_MSK (0x1UL << AG903_VIDIOn_MOD_HPOL_POS) 290: #define AG903_VIDIOn_MOD_VPOL_POS 4 291: #define AG903_VIDIOn_MOD_VPOL_MSK (0x1UL << AG903_VIDIOn_MOD_VPOL_POS) 292: 293: #define AG903_VIDIOn_OHPRM0_HPW_POS 0 294: #define AG903_VIDIOn_OHPRM0_HPW_MSK (0xfffUL << AG903_VIDIOn_OHPRM0_HPW_POS) 295: 296: #define AG903_VIDIOn_OHPRM1_HBP_POS 0 297: #define AG903_VIDIOn_OHPRM1_HBP_MSK (0xfffUL << AG903_VIDIOn_OHPRM1_HBP_POS) 298: #define AG903_VIDIOn_OHPRM1_HFP_POS 16 299: #define AG903_VIDIOn_OHPRM1_HFP_MSK (0xfffUL << AG903_VIDIOn_OHPRM1_HFP_POS) 300: 301: #define AG903_VIDIOn_OVPRM0_VPW_POS 0 302: #define AG903_VIDIOn_OVPRM0_VPW_MSK (0xfffUL << AG903_VIDIOn_OVPRM0_VPW_POS) 303: 304: #define AG903_VIDIOn_OVPRM1_VBP_POS 0 305: #define AG903_VIDIOn_OVPRM1_VBP_MSK (0xfffUL << AG903_VIDIOn_OVPRM1_VBP_POS) 306: #define AG903_VIDIOn_OVPRM1_VFP_POS 16 307: #define AG903_VIDIOn_OVPRM1_VFP_MSK (0xfffUL << AG903_VIDIOn_OVPRM1_VFP_POS) 308: 309: #define AG903_VIDIOn_OSIZE_HFS_POS 0 310: #define AG903_VIDIOn_OSIZE_HFS_MSK (0xfffUL << AG903_VIDIOn_OSIZE_HFS_POS) 311: #define AG903_VIDIOn_OSIZE_VFS_POS 16 312: #define AG903_VIDIOn_OSIZE_VFS_MSK (0xfffUL << AG903_VIDIOn_OSIZE_VFS_POS) 313: 314: #define AG903_VIDIOn_STAT_CWT_POS 0 315: #define AG903_VIDIOn_STAT_CWT_MSK (0x1UL << AG903_VIDIOn_STAT_CWT_POS) 316: 317: #define AG903_VIDCOn_MOD_TRSDEC_POS 0 318: #define AG903_VIDCOn_MOD_TRSDEC_MSK (0x1UL << AG903_VIDCOn_MOD_TRSDEC_POS) 319: #define AG903_VIDCOn_MOD_DELAY_POS 16 320: #define AG903_VIDCOn_MOD_DELAY_MSK (0x1UL << AG903_VIDCOn_MOD_DELAY_POS) 321: #define AG903_VIDCOn_MOD_TDMTRS_POS 24 322: #define AG903_VIDCOn_MOD_TDMTRS_MSK (0x1UL << AG903_VIDCOn_MOD_TDMTRS_POS) 323: #define AG903_VIDCOn_MOD_TDMBLK_POS 25 324: #define AG903_VIDCOn_MOD_TDMBLK_MSK (0x1UL << AG903_VIDCOn_MOD_TDMBLK_POS) 325: 326: #define AG903_VIDCOn_TRSPRM_HFP_POS 0 327: #define AG903_VIDCOn_TRSPRM_HFP_MSK (0xfffUL << AG903_VIDCOn_TRSPRM_HFP_POS) 328: #define AG903_VIDCOn_TRSPRM_HREF_POS 12 329: #define AG903_VIDCOn_TRSPRM_HREF_MSK (0x1UL << AG903_VIDCOn_TRSPRM_HREF_POS) 330: #define AG903_VIDCOn_TRSPRM_VFP_POS 16 331: #define AG903_VIDCOn_TRSPRM_VFP_MSK (0xfffUL << AG903_VIDCOn_TRSPRM_VFP_POS) 332: #define AG903_VIDCOn_TRSPRM_OFP_POS 28 333: #define AG903_VIDCOn_TRSPRM_OFP_MSK (0x1UL << AG903_VIDCOn_TRSPRM_OFP_POS) 334: #define AG903_VIDCOn_TRSPRM_EFP_POS 29 335: #define AG903_VIDCOn_TRSPRM_EFP_MSK (0x1UL << AG903_VIDCOn_TRSPRM_EFP_POS) 336: 337: #define AG903_VIDCOn_SDPRM_HMAX_POS 0 338: #define AG903_VIDCOn_SDPRM_HMAX_MSK (0x1fffUL << AG903_VIDCOn_SDPRM_HMAX_POS) 339: #define AG903_VIDCOn_SDPRM_VMAX_POS 16 340: #define AG903_VIDCOn_SDPRM_VMAX_MSK (0x1fffUL << AG903_VIDCOn_SDPRM_VMAX_POS) 341: 342: #define AG903_VIDCOn_STAT_TDMCH_POS 0 343: #define AG903_VIDCOn_STAT_TDMCH_MSK (0x7UL << AG903_VIDCOn_STAT_TDMCH_POS) 344: #define AG903_VIDCOn_STAT_HBLANK_POS 8 345: #define AG903_VIDCOn_STAT_HBLANK_MSK (0x1UL << AG903_VIDCOn_STAT_HBLANK_POS) 346: #define AG903_VIDCOn_STAT_VBLANK_POS 9 347: #define AG903_VIDCOn_STAT_VBLANK_MSK (0x1UL << AG903_VIDCOn_STAT_VBLANK_POS) 348: #define AG903_VIDCOn_STAT_TRSVAL_POS 16 349: #define AG903_VIDCOn_STAT_TRSVAL_MSK (0xffUL << AG903_VIDCOn_STAT_TRSVAL_POS) 350: #define AG903_VIDCOn_STAT_BLKVAL_POS 24 351: #define AG903_VIDCOn_STAT_BLKVAL_MSK (0xffUL << AG903_VIDCOn_STAT_BLKVAL_POS) 352: 353: #define AG903_VIDCOn_HST0_HPW_POS 0 354: #define AG903_VIDCOn_HST0_HPW_MSK (0x1fffUL << AG903_VIDCOn_HST0_HPW_POS) 355: 356: #define AG903_VIDCOn_HST1_HBP_POS 0 357: #define AG903_VIDCOn_HST1_HBP_MSK (0x1fffUL << AG903_VIDCOn_HST1_HBP_POS) 358: #define AG903_VIDCOn_HST1_HFP_POS 16 359: #define AG903_VIDCOn_HST1_HFP_MSK (0x1fffUL << AG903_VIDCOn_HST1_HFP_POS) 360: 361: #define AG903_VIDCOn_VST0_VPW_POS 0 362: #define AG903_VIDCOn_VST0_VPW_MSK (0x1fffUL << AG903_VIDCOn_VST0_VPW_POS) 363: #define AG903_VIDCOn_VST0_OFP_POS 16 364: #define AG903_VIDCOn_VST0_OFP_MSK (0x1UL << AG903_VIDCOn_VST0_OFP_POS) 365: #define AG903_VIDCOn_VST0_OBP_POS 17 366: #define AG903_VIDCOn_VST0_OBP_MSK (0x1UL << AG903_VIDCOn_VST0_OBP_POS) 367: #define AG903_VIDCOn_VST0_EFP_POS 18 368: #define AG903_VIDCOn_VST0_EFP_MSK (0x1UL << AG903_VIDCOn_VST0_EFP_POS) 369: #define AG903_VIDCOn_VST0_EBP_POS 19 370: #define AG903_VIDCOn_VST0_EBP_MSK (0x1UL << AG903_VIDCOn_VST0_EBP_POS) 371: #define AG903_VIDCOn_VST0_SCAN_POS 20 372: #define AG903_VIDCOn_VST0_SCAN_MSK (0x1UL << AG903_VIDCOn_VST0_SCAN_POS) 373: 374: #define AG903_VIDCOn_VST1_VBP_POS 0 375: #define AG903_VIDCOn_VST1_VBP_MSK (0x1fffUL << AG903_VIDCOn_VST1_VBP_POS) 376: #define AG903_VIDCOn_VST1_VFP_POS 16 377: #define AG903_VIDCOn_VST1_VFP_MSK (0x1fffUL << AG903_VIDCOn_VST1_VFP_POS) 378: 379: #define AG903_VIDCOn_FST_HFS_POS 0 380: #define AG903_VIDCOn_FST_HFS_MSK (0x1fffUL << AG903_VIDCOn_FST_HFS_POS) 381: #define AG903_VIDCOn_FST_VFS_POS 16 382: #define AG903_VIDCOn_FST_VFS_MSK (0x1fffUL << AG903_VIDCOn_FST_VFS_POS) 383: 384: #endif 385:
名前 
説明 
VID Base Address 
VIDCTRL ON-bit mask 
VIDCTRL ON-bit position 
VIDFMT FMT-bit mask 
VIDFMT FMT-bit position 
VIDCOn Base Address 
VIDCOn Base Address 
VIDCOn Base Address 
VIDCOn Base Address 
VIDCOn Base Address (n=0..3) 
VIDCOnFST Address (n=0..3) 
VIDCOnFST HFS-bit mask 
VIDCOnFST HFS-bit position 
VIDCOnFST VFS-bit mask 
VIDCOnFST VFS-bit position 
VIDCOnHST0 Address (n=0..3) 
VIDCOnHST0 HPW-bit mask 
VIDCOnHST0 HPW-bit position 
VIDCOnHST1 Address (n=0..3) 
VIDCOnHST1 HBP-bit mask 
VIDCOnHST1 HBP-bit position 
VIDCOnHST1 HFP-bit mask 
VIDCOnHST1 HFP-bit position 
VIDCOnMOD Address (n=0..3) 
VIDCOnMOD DELAY-bit mask 
VIDCOnMOD DELAY-bit position 
VIDCOnMOD TDMBLK-bit mask 
VIDCOnMOD TDMBLK-bit position 
VIDCOnMOD TDMTRS-bit mask 
VIDCOnMOD TDMTRS-bit position 
VIDCOnMOD TRSDEC-bit mask 
VIDCOnMOD TRSDEC-bit position 
VIDCOnSDPRM Address (n=0..3) 
VIDCOnSDPRM HMAX-bit mask 
VIDCOnSDPRM HMAX-bit position 
VIDCOnSDPRM VMAX-bit mask 
VIDCOnSDPRM VMAX-bit position 
VIDCOnSTAT Address (n=0..3) 
VIDCOnSTAT BLKVAL-bit mask 
VIDCOnSTAT BLKVAL-bit position 
VIDCOnSTAT HBLANK-bit mask 
VIDCOnSTAT HBLANK-bit position 
VIDCOnSTAT TDMCH-bit mask 
VIDCOnSTAT TDMCH-bit position 
VIDCOnSTAT TRSVAL-bit mask 
VIDCOnSTAT TRSVAL-bit position 
VIDCOnSTAT VBLANK-bit mask 
VIDCOnSTAT VBLANK-bit position 
VIDCOnTRSPRM Address (n=0..3) 
VIDCOnTRSPRM EFP-bit mask 
VIDCOnTRSPRM EFP-bit position 
VIDCOnTRSPRM HFP-bit mask 
VIDCOnTRSPRM HFP-bit position 
VIDCOnTRSPRM HREF-bit mask 
VIDCOnTRSPRM HREF-bit position 
VIDCOnTRSPRM OFP-bit mask 
VIDCOnTRSPRM OFP-bit position 
VIDCOnTRSPRM VFP-bit mask 
VIDCOnTRSPRM VFP-bit position 
VIDCOnVST0 Address (n=0..3) 
VIDCOnVST0 EBP-bit mask 
VIDCOnVST0 EBP-bit position 
VIDCOnVST0 EFP-bit mask 
VIDCOnVST0 EFP-bit position 
VIDCOnVST0 OBP-bit mask 
VIDCOnVST0 OBP-bit position 
VIDCOnVST0 OFP-bit mask 
VIDCOnVST0 OFP-bit position 
VIDCOnVST0 SCAN-bit mask 
VIDCOnVST0 SCAN-bit position 
VIDCOnVST0 VPW-bit mask 
VIDCOnVST0 VPW-bit position 
VIDCOnVST1 Address (n=0..3) 
VIDCOnVST1 VBP-bit mask 
VIDCOnVST1 VBP-bit position 
VIDCOnVST1 VFP-bit mask 
VIDCOnVST1 VFP-bit position 
VIDIOn Base Address 
VIDIOn Base Address 
VIDIOn Base Address (n=0..1) 
VIDIOnCTRL Address (n=0..1) 
VIDIOnCTRL SOE-bit mask 
VIDIOnCTRL SOE-bit position 
VIDIOnMOD Address (n=0..1) 
VIDIOnMOD CPOL-bit mask 
VIDIOnMOD CPOL-bit position 
VIDIOnMOD DPOL-bit mask 
VIDIOnMOD DPOL-bit position 
VIDIOnMOD FPOL-bit mask 
VIDIOnMOD FPOL-bit position 
VIDIOnMOD HPOL-bit mask 
VIDIOnMOD HPOL-bit position 
VIDIOnMOD VPOL-bit mask 
VIDIOnMOD VPOL-bit position 
VIDIOnOHPRM0 Address (n=0..1) 
VIDIOnOHPRM0 HPW-bit mask 
VIDIOnOHPRM0 HPW-bit position 
VIDIOnOHPRM1 Address (n=0..1) 
VIDIOnOHPRM1 HBP-bit mask 
VIDIOnOHPRM1 HBP-bit position 
VIDIOnOHPRM1 HFP-bit mask 
VIDIOnOHPRM1 HFP-bit position 
VIDIOnOSIZE Address (n=0..1) 
VIDIOnOSIZE HFS-bit mask 
VIDIOnOSIZE HFS-bit position 
VIDIOnOSIZE VFS-bit mask 
VIDIOnOSIZE VFS-bit position 
VIDIOnOVPRM0 Address (n=0..1) 
VIDIOnOVPRM0 VPW-bit mask 
VIDIOnOVPRM0 VPW-bit position 
VIDIOnOVPRM1 Address (n=0..1) 
VIDIOnOVPRM1 VBP-bit mask 
VIDIOnOVPRM1 VBP-bit position 
VIDIOnOVPRM1 VFP-bit mask 
VIDIOnOVPRM1 VFP-bit position 
VIDIOnSTAT Address (n=0..1) 
VIDIOnSTAT CWT-bit mask 
VIDIOnSTAT CWT-bit position 
名前 
説明 
VID Type 
VIDCOn Type 
VIDIOn Type 
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