AG903ライブラリリファレンス
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sspprm.c

SSP Primitive

SSP Primitive Layer

none

AXELL CORPORATION

2017_02_22 初版 

2017_10_26 Ver2.0 

2023_03_31 [SDK3.5] SSPライブラリにI2Sのマスターモードを追加 (#4205) 

2025_03_06 [SDK3.7] SSPで1ワードの送信ができない不具合を修正 (#5633) 

2025_03_06 [SDK3.7] SSPライブラリにSPIモードでの送受信アクセス機能を追加 (#5662)

1: 12: 13: 17: 18: 19: #include "AG903_errno.h" 20: #include "AG903_common.h" 21: #include "ssp/sspprm.h" 22: #include "register/AG903_sspreg.h" 23: 24: #define AG903_SSP_READ_REG(CH,REG) (AG903_SSPn(CH)->REG) 25: #define AG903_SSP_READ_FLD(CH,REG,POS,MSK) (((AG903_SSPn(CH)->REG)&MSK) >> POS) 26: #define AG903_SSP_WRITE_REG(CH,REG,VAL) (AG903_SSPn(CH)->REG = (uint32_t)(VAL)) 27: #define AG903_SSP_CLR_REG(CH,REG,VAL) (AG903_SSPn(CH)->REG &= (uint32_t)(~VAL)) 28: #define AG903_SSP_SET_REG(CH,REG,VAL) (AG903_SSPn(CH)->REG |= (uint32_t)(VAL)) 29: #define AG903_SSP_UNPACK_FLD(V,REG,FLD) (((V) & AG903_SSPn_##REG##_##FLD##_MSK) >> AG903_SSPn_##REG##_##FLD##_POS) 30: #define AG903_SSP_PACK_FLD(V,REG,FLD) (((V) << AG903_SSPn_##REG##_##FLD##_POS) & AG903_SSPn_##REG##_##FLD##_MSK) 31: 32: 39: void AG903_SSPPrmSetControl(uint8_t ch, AG903_SSPPrmCtrl* param) 40: { 41: uint32_t ctrl_0=0; 42: uint32_t ctrl_1=0; 43: 44: ASSERT(AG903_SSP_CH_NUM > ch); 45: 46: if (AG903_SSP_OPM_MASTER == param->opm || 47: AG903_SSP_OPM_MASTER_STEREO == param->opm) { 48: ctrl_0 |= (uint32_t)(1 << AG903_SSPn_SSPCR0_FSFDBK_POS); 49: ctrl_0 |= (uint32_t)(1 << AG903_SSPn_SSPCR0_SCLKFDBK_POS); 50: } 51: 52: if(0 != param->spi_fspo) { 53: ctrl_0 |= (uint32_t)(1 << AG903_SSPn_SSPCR0_SPIFSPO_POS); 54: } 55: 56: ctrl_0 |= (uint32_t)((param->format << AG903_SSPn_SSPCR0_FFMT_POS) & AG903_SSPn_SSPCR0_FFMT_MSK); 57: 58: if(0 != param->spi_flash) { 59: ctrl_0 |= (uint32_t)(1 << AG903_SSPn_SSPCR0_FLASH_POS); 60: } 61: if(0 != param->validity) { 62: ctrl_0 |= (uint32_t)(1 << AG903_SSPn_SSPCR0_Validity_POS); 63: } 64: 65: ctrl_0 |= (uint32_t)((param->fsdist << AG903_SSPn_SSPCR0_FSDIST_POS) & AG903_SSPn_SSPCR0_FSDIST_MSK); 66: 67: if(0 != param->lsb) { 68: ctrl_0 |= (uint32_t)(1 << AG903_SSPn_SSPCR0_LSB_POS); 69: } 70: if(0 != param->fspo) { 71: ctrl_0 |= (uint32_t)(1 << AG903_SSPn_SSPCR0_FSPO_POS); 72: } 73: if(0 != param->fsjstfy) { 74: ctrl_0 |= (uint32_t)(1 << AG903_SSPn_SSPCR0_FSJSTFY_POS); 75: } 76: 77: ctrl_0 |= (uint32_t)((param->opm << AG903_SSPn_SSPCR0_OPM_POS) & AG903_SSPn_SSPCR0_OPM_MSK); 78: 79: if(0 != param->sclkpo) { 80: ctrl_0 |= (uint32_t)(1 << AG903_SSPn_SSPCR0_SCLKPO_POS); 81: } 82: if(0 != param->sclkph) { 83: ctrl_0 |= (uint32_t)(1 << AG903_SSPn_SSPCR0_SCLKPH_POS); 84: } 85: 86: ctrl_1 |= (uint32_t)((param->pdl << AG903_SSPn_SSPCR1_PDL_POS) & AG903_SSPn_SSPCR1_PDL_MSK); 87: ctrl_1 |= (uint32_t)((param->sdl << AG903_SSPn_SSPCR1_SDL_POS) & AG903_SSPn_SSPCR1_SDL_MSK); 88: ctrl_1 |= (uint32_t)((param->sclk_div << AG903_SSPn_SSPCR1_SCLKDIV_POS) & AG903_SSPn_SSPCR1_SCLKDIV_MSK); 89: 90: AG903_SSP_WRITE_REG(ch,SSPCR0,ctrl_0); 91: AG903_SSP_WRITE_REG(ch,SSPCR1,ctrl_1); 92: return; 93: } 94: 95: 102: void AG903_SSPPrmGetControl2(uint8_t ch, AG903_SSPPrmCtrl2* param) 103: { 104: uint32_t ctrl_2; 105: 106: ASSERT(AG903_SSP_CH_NUM > ch); 107: 108: ctrl_2 = AG903_SSP_READ_REG(ch,SSPCR2); 109: param->fsos = AG903_SSP_UNPACK_FLD(ctrl_2, SSPCR2, FSOS); 110: param->fs = AG903_SSP_UNPACK_FLD(ctrl_2, SSPCR2, FS); 111: param->txen = AG903_SSP_UNPACK_FLD(ctrl_2, SSPCR2, TXEN); 112: param->rxen = AG903_SSP_UNPACK_FLD(ctrl_2, SSPCR2, RXEN); 113: param->ssprst = 0; 114: param->txfclr = 0; 115: param->rxfclr = 0; 116: param->txdoe = AG903_SSP_UNPACK_FLD(ctrl_2, SSPCR2, TXDOE); 117: param->sspen = AG903_SSP_UNPACK_FLD(ctrl_2, SSPCR2, SSPEN); 118: return; 119: } 120: 121: 128: void AG903_SSPPrmSetControl2(uint8_t ch, AG903_SSPPrmCtrl2* param) 129: { 130: uint32_t ctrl_2; 131: 132: ASSERT(AG903_SSP_CH_NUM > ch); 133: param->fsos = 0; 134: 135: ctrl_2 = 0; 136: ctrl_2 |= AG903_SSP_PACK_FLD(param->fsos, SSPCR2, FSOS); 137: ctrl_2 |= AG903_SSP_PACK_FLD(param->fs, SSPCR2, FS); 138: ctrl_2 |= AG903_SSP_PACK_FLD(param->txen, SSPCR2, TXEN); 139: ctrl_2 |= AG903_SSP_PACK_FLD(param->rxen, SSPCR2, RXEN); 140: ctrl_2 |= AG903_SSP_PACK_FLD(param->ssprst, SSPCR2, SSPRST); 141: ctrl_2 |= AG903_SSP_PACK_FLD(param->txfclr, SSPCR2, TXFCLR); 142: ctrl_2 |= AG903_SSP_PACK_FLD(param->rxfclr, SSPCR2, RXFCLR); 143: ctrl_2 |= AG903_SSP_PACK_FLD(param->txdoe, SSPCR2, TXDOE); 144: ctrl_2 |= AG903_SSP_PACK_FLD(param->sspen, SSPCR2, SSPEN); 145: AG903_SSP_WRITE_REG(ch,SSPCR2,ctrl_2); 146: return; 147: } 148: 149: 156: void AG903_SSPPrmEnableOutput(uint8_t ch) 157: { 158: ASSERT(AG903_SSP_CH_NUM > ch); 159: AG903_SSP_SET_REG(ch,SSPCR2,(1<<AG903_SSPn_SSPCR2_TXDOE_POS)); 160: return; 161: } 162: 163: 170: void AG903_SSPPrmDisableOutput(uint8_t ch) 171: { 172: ASSERT(AG903_SSP_CH_NUM > ch); 173: AG903_SSP_CLR_REG(ch,SSPCR2,(1<<AG903_SSPn_SSPCR2_TXDOE_POS)); 174: return; 175: } 176: 177: 184: void AG903_SSPPrmEnableTransfer(uint8_t ch) 185: { 186: ASSERT(AG903_SSP_CH_NUM > ch); 187: AG903_SSP_SET_REG(ch,SSPCR2,(1<<AG903_SSPn_SSPCR2_SSPEN_POS)); 188: return; 189: } 190: 191: 198: void AG903_SSPPrmDisableTransfer(uint8_t ch) 199: { 200: ASSERT(AG903_SSP_CH_NUM > ch); 201: AG903_SSP_CLR_REG(ch,SSPCR2,(1<<AG903_SSPn_SSPCR2_SSPEN_POS)); 202: return; 203: } 204: 205: 212: void AG903_SSPPrmCheckEnable(uint8_t ch, uint8_t* enable) 213: { 214: ASSERT(AG903_SSP_CH_NUM > ch); 215: (*enable) = AG903_SSP_READ_FLD(ch,SSPCR2,AG903_SSPn_SSPCR2_SSPEN_POS,AG903_SSPn_SSPCR2_SSPEN_MSK); 216: return; 217: } 218: 219: 226: void AG903_SSPPrmEnableTxFunc(uint8_t ch) 227: { 228: ASSERT(AG903_SSP_CH_NUM > ch); 229: AG903_SSP_SET_REG(ch,SSPCR2,(1<<AG903_SSPn_SSPCR2_TXEN_POS)); 230: return; 231: } 232: 233: 240: void AG903_SSPPrmDisbleTxFunc(uint8_t ch) 241: { 242: ASSERT(AG903_SSP_CH_NUM > ch); 243: AG903_SSP_CLR_REG(ch,SSPCR2,(1<<AG903_SSPn_SSPCR2_TXEN_POS)); 244: return; 245: } 246: 247: 254: void AG903_SSPPrmEnableRxFunc(uint8_t ch) 255: { 256: ASSERT(AG903_SSP_CH_NUM > ch); 257: AG903_SSP_SET_REG(ch,SSPCR2,(1<<AG903_SSPn_SSPCR2_RXEN_POS)); 258: return; 259: } 260: 261: 268: void AG903_SSPPrmDisbleRxFunc(uint8_t ch) 269: { 270: ASSERT(AG903_SSP_CH_NUM > ch); 271: AG903_SSP_CLR_REG(ch,SSPCR2,(1<<AG903_SSPn_SSPCR2_RXEN_POS)); 272: return; 273: } 274: 275: 282: void AG903_SSPPrmGetTxFifoEntry(uint8_t ch, uint8_t* entry) 283: { 284: (*entry) = AG903_SSP_READ_FLD(ch,SSPStatus,AG903_SSPn_SSPStatus_TFVE_POS,AG903_SSPn_SSPStatus_TFVE_MSK); 285: return; 286: } 287: 288: 295: void AG903_SSPPrmGetRxFifoEntry(uint8_t ch, uint8_t* entry) 296: { 297: (*entry) = AG903_SSP_READ_FLD(ch,SSPStatus,AG903_SSPn_SSPStatus_RFVE_POS,AG903_SSPn_SSPStatus_RFVE_MSK); 298: return; 299: } 300: 301: 309: void AG903_SSPPrmSetTxFifoThreshold(uint8_t ch, uint8_t val) 310: { 311: AG903_SSP_CLR_REG(ch,IntrCR,AG903_SSPn_IntrCR_TFTHOD_MSK); 312: AG903_SSP_SET_REG(ch,IntrCR,(val<<AG903_SSPn_IntrCR_TFTHOD_POS)); 313: return; 314: } 315: 316: 324: void AG903_SSPPrmSetRxFifoThreshold(uint8_t ch, uint8_t val) 325: { 326: AG903_SSP_CLR_REG(ch,IntrCR,AG903_SSPn_IntrCR_RFTHOD_MSK); 327: AG903_SSP_SET_REG(ch,IntrCR,(val<<AG903_SSPn_IntrCR_RFTHOD_POS)); 328: return; 329: } 330: 331: 338: void AG903_SSPPrmClearTxFifo(uint8_t ch) 339: { 340: ASSERT(AG903_SSP_CH_NUM > ch); 341: AG903_SSP_SET_REG(ch,SSPCR2,(1<<AG903_SSPn_SSPCR2_TXFCLR_POS)); 342: return; 343: } 344: 345: 352: void AG903_SSPPrmClearRxFifo(uint8_t ch) 353: { 354: ASSERT(AG903_SSP_CH_NUM > ch); 355: AG903_SSP_SET_REG(ch,SSPCR2,(1<<AG903_SSPn_SSPCR2_RXFCLR_POS)); 356: return; 357: } 358: 359: 366: void AG903_SSPPrmReset(uint8_t ch) 367: { 368: ASSERT(AG903_SSP_CH_NUM > ch); 369: AG903_SSP_SET_REG(ch,SSPCR2,(1<<AG903_SSPn_SSPCR2_SSPRST_POS)); 370: return; 371: } 372: 373: 381: void AG903_SSPPrmSetStatusBit(uint8_t ch, uint32_t status_0, uint32_t status_1) 382: { 383: ASSERT(AG903_SSP_CH_NUM > ch); 384: AG903_SSP_WRITE_REG(ch,SPDIFStatus0,status_0); 385: AG903_SSP_WRITE_REG(ch,SPDIFStatus1,status_1); 386: return; 387: } 388: 389: 397: void AG903_SSPPrmSetUserBit(uint8_t ch, uint8_t offset, uint32_t val) 398: { 399: uint32_t* reg; 400: 401: ASSERT(AG903_SSP_CH_NUM > ch); 402: 403: reg = (uint32_t*)(&AG903_SSPn(ch)->SPDIFUser0); 404: (*(reg+offset)) = val; 405: return; 406: } 407: 408: 415: void AG903_SSPPrmEnableTxInt(uint8_t ch) 416: { 417: uint32_t val; 418: 419: ASSERT(AG903_SSP_CH_NUM > ch); 420: val = 421: 1<<AG903_SSPn_IntrCR_TFTHIEN_POS | 422: 1<<AG903_SSPn_IntrCR_TFURIEN_POS; 423: AG903_SSP_SET_REG(ch,IntrCR,val); 424: return; 425: } 426: 427: 434: void AG903_SSPPrmDisbleTxInt(uint8_t ch) 435: { 436: uint32_t val; 437: 438: ASSERT(AG903_SSP_CH_NUM > ch); 439: val = 440: 1<<AG903_SSPn_IntrCR_TFTHIEN_POS | 441: 1<<AG903_SSPn_IntrCR_TFURIEN_POS; 442: AG903_SSP_CLR_REG(ch,IntrCR,val); 443: return; 444: } 445: 446: 453: void AG903_SSPPrmEnableRxInt(uint8_t ch) 454: { 455: uint32_t val; 456: 457: ASSERT(AG903_SSP_CH_NUM > ch); 458: val = 459: 1<<AG903_SSPn_IntrCR_RFTHIEN_POS | 460: 1<<AG903_SSPn_IntrCR_RFORIEN_POS; 461: AG903_SSP_SET_REG(ch,IntrCR,val); 462: return; 463: } 464: 465: 472: void AG903_SSPPrmDisbleRxInt(uint8_t ch) 473: { 474: uint32_t val; 475: 476: ASSERT(AG903_SSP_CH_NUM > ch); 477: val = 478: 1<<AG903_SSPn_IntrCR_RFTHIEN_POS | 479: 1<<AG903_SSPn_IntrCR_RFORIEN_POS; 480: AG903_SSP_CLR_REG(ch,IntrCR,val); 481: return; 482: } 483: 484: 491: void AG903_SSPPrmEnableTxDmareq(uint8_t ch) 492: { 493: ASSERT(AG903_SSP_CH_NUM > ch); 494: AG903_SSP_SET_REG(ch,IntrCR,(1<<AG903_SSPn_IntrCR_TFDMAEN_POS)); 495: return; 496: } 497: 498: 505: void AG903_SSPPrmDisableTxDmareq(uint8_t ch) 506: { 507: ASSERT(AG903_SSP_CH_NUM > ch); 508: AG903_SSP_CLR_REG(ch,IntrCR,(1<<AG903_SSPn_IntrCR_TFDMAEN_POS)); 509: return; 510: } 511: 512: 519: void AG903_SSPPrmEnableRxDmareq(uint8_t ch) 520: { 521: ASSERT(AG903_SSP_CH_NUM > ch); 522: AG903_SSP_SET_REG(ch,IntrCR,(1<<AG903_SSPn_IntrCR_RFDMAEN_POS)); 523: return; 524: } 525: 526: 533: void AG903_SSPPrmDisableRxDmareq(uint8_t ch) 534: { 535: ASSERT(AG903_SSP_CH_NUM > ch); 536: AG903_SSP_CLR_REG(ch,IntrCR,(1<<AG903_SSPn_IntrCR_RFDMAEN_POS)); 537: return; 538: } 539: 540: 547: void AG903_SSPPrmSetData(uint8_t ch, uint32_t val) 548: { 549: ASSERT(AG903_SSP_CH_NUM > ch); 550: AG903_SSP_WRITE_REG(ch,TxRxDR,val); 551: return; 552: } 553: 554: 561: void AG903_SSPPrmGetData(uint8_t ch, uint32_t* val) 562: { 563: ASSERT(AG903_SSP_CH_NUM > ch); 564: (*val) = AG903_SSP_READ_REG(ch,TxRxDR); 565: return; 566: } 567: 568: 575: void AG903_SSPPrmGetStatus(uint8_t ch, AG903_SSPPrmStatus* status) 576: { 577: uint32_t val; 578: 579: ASSERT(AG903_SSP_CH_NUM > ch); 580: val = AG903_SSP_READ_REG(ch,SSPStatus); 581: 582: status->txfifo_num = (uint8_t)((val & AG903_SSPn_SSPStatus_TFVE_MSK) >> AG903_SSPn_SSPStatus_TFVE_POS); 583: status->rxfifo_num = (uint8_t)((val & AG903_SSPn_SSPStatus_RFVE_MSK) >> AG903_SSPn_SSPStatus_RFVE_POS); 584: if(AG903_SSPn_SSPStatus_BUSY_MSK & val) { 585: status->busy = true; 586: } 587: else { 588: status->busy = false; 589: } 590: if(AG903_SSPn_SSPStatus_TFNF_MSK & val) { 591: status->txfifo_notfull = true; 592: } 593: else { 594: status->txfifo_notfull = false; 595: } 596: if(AG903_SSPn_SSPStatus_RFF_MSK & val) { 597: status->rxfifo_full = true; 598: } 599: else { 600: status->rxfifo_full = false; 601: } 602: 603: return; 604: } 605: 606: 613: void AG903_SSPPrmSetIntControl(uint8_t ch, AG903_SSPPrmIntCtrl* param) 614: { 615: uint32_t intr_cr; 616: 617: ASSERT(AG903_SSP_CH_NUM > ch); 618: 619: intr_cr = 0; 620: intr_cr |= AG903_SSP_PACK_FLD(param->tfthod, IntrCR, TFTHOD); 621: intr_cr |= AG903_SSP_PACK_FLD(param->rfthod, IntrCR, RFTHOD); 622: intr_cr |= AG903_SSP_PACK_FLD(param->tfdmaen, IntrCR, TFDMAEN); 623: intr_cr |= AG903_SSP_PACK_FLD(param->rfdmaen, IntrCR, RFDMAEN); 624: intr_cr |= AG903_SSP_PACK_FLD(param->tfthien, IntrCR, TFTHIEN); 625: intr_cr |= AG903_SSP_PACK_FLD(param->rfthien, IntrCR, RFTHIEN); 626: intr_cr |= AG903_SSP_PACK_FLD(param->tfurien, IntrCR, TFURIEN); 627: intr_cr |= AG903_SSP_PACK_FLD(param->rforien, IntrCR, RFORIEN); 628: AG903_SSP_WRITE_REG(ch,IntrCR,intr_cr); 629: return; 630: } 631: 632: 639: void AG903_SSPPrmGetIntControl(uint8_t ch, AG903_SSPPrmIntCtrl* param) 640: { 641: uint32_t intr_cr; 642: 643: ASSERT(AG903_SSP_CH_NUM > ch); 644: 645: intr_cr = AG903_SSP_READ_REG(ch,IntrCR); 646: param->tfthod = AG903_SSP_UNPACK_FLD(intr_cr, IntrCR, TFTHOD); 647: param->rfthod = AG903_SSP_UNPACK_FLD(intr_cr, IntrCR, RFTHOD); 648: param->tfdmaen = AG903_SSP_UNPACK_FLD(intr_cr, IntrCR, TFDMAEN); 649: param->rfdmaen = AG903_SSP_UNPACK_FLD(intr_cr, IntrCR, RFDMAEN); 650: param->tfthien = AG903_SSP_UNPACK_FLD(intr_cr, IntrCR, TFTHIEN); 651: param->rfthien = AG903_SSP_UNPACK_FLD(intr_cr, IntrCR, RFTHIEN); 652: param->tfurien = AG903_SSP_UNPACK_FLD(intr_cr, IntrCR, TFURIEN); 653: param->rforien = AG903_SSP_UNPACK_FLD(intr_cr, IntrCR, RFORIEN); 654: return; 655: } 656: 657: 664: void AG903_SSPPrmGetIntStatus(uint8_t ch, uint32_t* status) 665: { 666: ASSERT(AG903_SSP_CH_NUM > ch); 667: (*status) = AG903_SSP_READ_REG(ch,IntrStatus); 668: return; 669: } 670:
 
名前 
説明 
 
SSPnSSPCR2レジスタのSSPENビットRead 
 
SSPnSSPCR2レジスタのRXFCLRビットSet 
 
SSPnSSPCR2レジスタのTXFCLRビットSet 
 
SSPnSSPCR2レジスタのTXDOEビットClear 
 
SSPnIntrCRレジスタのRFDMAENビットClear 
 
SSPnSSPCR2レジスタのSSPENビットClear 
 
SSPnIntrCRレジスタのTFDMAENビットClear 
 
SSPnSSPCR2レジスタのRXENビットClear 
 
SSPnIntrCRレジスタのRFTHIEN,RFORIENビットClear 
 
SSPnSSPCR2レジスタのTXENビットClear 
 
SSPnIntrCRレジスタのTFTHIEN,TFURIENビットClear 
 
SSPnSSPCR2レジスタのTXDOEビットSet 
 
SSPnIntrCRレジスタのRFDMAENビットSet 
 
SSPnSSPCR2レジスタのRXENビットSet 
 
SSPnIntrCRレジスタのRFTHIEN,RFORIENビットSet 
 
SSPnSSPCR2レジスタのSSPENビットSet 
 
SSPnIntrCRレジスタのTFDMAENビットSet 
 
SSPnSSPCR2レジスタのTXENビットSet 
 
SSPnIntrCRレジスタのTFTHIEN,TFURIENビットSet 
 
SSPnSSPCR2のレジスタRead 
 
SSPnTxRxDRレジスタRead 
 
SSPnIntrCRレジスタRead 
 
SSPnIntrStatusレジスタRead 
 
SSPnSSPStatusレジスタのRFVEフィールドRead 
 
SSPnSSPStatusレジスタRead 
 
SSPnSSPStatusレジスタのTFVEフィールドRead 
 
SSPnSSPCR2レジスタのSSPRSTビットSet 
 
SSPnSSPCR0,SSPnSSPCR1のレジスタWrite 
 
SSPnSSPCR2のレジスタWrite 
 
SSPnTxRxDRレジスタWrite 
 
SSPnIntrCRレジスタWrite 
 
SSPnIntrCRレジスタのRFTHODフィールドWrite 
 
SSPnSPDIFStatus0,SSPnSPDIFStatus1レジスタWrite 
 
SSPnIntrCRレジスタのTFTHODフィールドWrite 
 
SSPnSPDIFUsernレジスタWrite 
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