AG903ライブラリリファレンス
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AG903_uartreg.h
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1: 9: 10: 14: 15:
#ifndef
_AG903_UART_REGMAP_H_ 16:
#define
_AG903_UART_REGMAP_H_ 17: 18: 19:
#include
"AG903_regmap.h" 20: 21:
#ifndef
__I
22: 23:
#define
__I
volatile
const
24:
#endif
25:
#ifndef
__O
26: 27:
#define
__O
volatile
28:
#endif
29:
#ifndef
__IO
30: 31:
#define
__IO
volatile
32:
#endif
33: 34: 35:
typedef
struct
{ 36: 37:
union
{ 38:
__I
uint8_t RBR; 39:
__O
uint8_t THR; 40:
__IO
uint8_t DLL; 41: }; 42: 43:
__I
uint8_t RESERVED1[3]; 44: 45:
union
{ 46:
__IO
uint8_t IER; 47: 48:
struct
{ 49:
__IO
uint8_t Receiver_Data_Available : 1; 50:
__IO
uint8_t THR_Empty : 1; 51:
__IO
uint8_t Receiver_Line_Status : 1; 52:
__IO
uint8_t MODEM_Status : 1; 53:
__IO
uint8_t RTSEn : 1; 54:
__IO
uint8_t CTSEn : 1; 55:
__IO
uint8_t DTREn : 1; 56:
__IO
uint8_t DSREn : 1; 57: } IER_bits; 58: 59:
__IO
uint8_t DLM; 60: }; 61: 62:
__I
uint8_t RESERVED2[3]; 63: 64:
union
{ 65:
__I
uint8_t IIR; 66: 67:
struct
{ 68:
__I
uint8_t Interrupt_Pending : 1; 69:
__I
uint8_t Interrupt_Identification_Code : 2; 70:
__I
uint8_t FIFO_mode_only : 1; 71:
__I
uint8_t Tx_FIFO_full : 1; 72: uint8_t : 1; 73:
__I
uint8_t FIFO_mode_enable : 2; 74: } IIR_bits; 75: 76:
__O
uint8_t FCR; 77: 78:
struct
{ 79:
__O
uint8_t FIFO_Enable : 1; 80:
__O
uint8_t RX_FIFO_Reset : 1; 81:
__O
uint8_t TX_FIFO_Reset : 1; 82:
__O
uint8_t DMA_Mode : 1; 83: uint8_t : 2; 84:
__O
uint8_t RXFIFO_TRGL : 2; 85: } FCR_bits; 86: 87:
__IO
uint8_t PSR; 88: 89:
struct
{ 90:
__IO
uint8_t PSR : 5; 91: } PSR_bits; 92: }; 93: 94:
__I
uint8_t RESERVED3[3]; 95: 96:
union
{ 97:
__IO
uint8_t LCR; 98: 99:
struct
{ 100:
__IO
uint8_t WL0 : 1; 101:
__IO
uint8_t WL1 : 1; 102:
__IO
uint8_t Stop_Bits : 1; 103:
__IO
uint8_t Parity_Enable : 1; 104:
__IO
uint8_t Even_Parity : 1; 105:
__IO
uint8_t Stick_Parity : 1; 106:
__IO
uint8_t Set_Break : 1; 107:
__IO
uint8_t DLAB : 1; 108: } LCR_bits; 109: }; 110: 111:
__I
uint8_t RESERVED4[3]; 112: 113:
union
{ 114:
__IO
uint8_t MCR; 115: 116:
struct
{ 117:
__IO
uint8_t DTR : 1; 118:
__IO
uint8_t RTS : 1; 119:
__IO
uint8_t Out1 : 1; 120:
__IO
uint8_t Out2 : 1; 121:
__IO
uint8_t Loop : 1; 122:
__IO
uint8_t DMAmode2 : 1; 123:
__IO
uint8_t Out3 : 1; 124: } MCR_bits; 125: }; 126: 127:
__I
uint8_t RESERVED5[3]; 128: 129:
union
{ 130:
__I
uint8_t LSR; 131: 132:
struct
{ 133:
__I
uint8_t Data_Ready : 1; 134:
__I
uint8_t Overrun_Error : 1; 135:
__I
uint8_t Parity_Error : 1; 136:
__I
uint8_t Framing_Error : 1; 137:
__I
uint8_t Break_Interrupt : 1; 138:
__I
uint8_t THR_Empty : 1; 139:
__I
uint8_t Transmitter_Empty : 1; 140:
__I
uint8_t FIFO_Data_Error : 1; 141: } LSR_bits; 142: 143:
__O
uint8_t TST; 144: 145:
struct
{ 146:
__O
uint8_t TEST_PAR_ERR : 1; 147:
__O
uint8_t TEST_FRM_ERR : 1; 148:
__O
uint8_t TEST_BAUDGEN : 1; 149:
__O
uint8_t TEST_PHY_ERR : 1; 150:
__O
uint8_t TEST_CRC_ERR : 1; 151: } TST_bits; 152: }; 153: 154:
__I
uint8_t RESERVED6[3]; 155: 156:
union
{ 157:
__I
uint8_t MSR; 158: 159:
struct
{ 160:
__I
uint8_t Delta_CTS : 1; 161:
__I
uint8_t Delta_DSR : 1; 162:
__I
uint8_t Trailing_edge_R1 : 1; 163:
__I
uint8_t Delta_DCD : 1; 164:
__I
uint8_t CTS : 1; 165:
__I
uint8_t DSR : 1; 166:
__I
uint8_t RI : 1; 167:
__I
uint8_t DCD : 1; 168: } MSR_bits; 169: }; 170: 171:
__I
uint8_t RESERVED7[3]; 172: 173:
union
{ 174:
__IO
uint8_t SPR; 175: }; 176: 177:
__I
uint8_t RESERVED8[3]; 178:
__I
uint32_t RESERVED9[18]; 179: 180:
union
{ 181:
__I
uint8_t FEATURE; 182: 183:
struct
{ 184:
__I
uint8_t FIFO_DEPTH : 4; 185:
__I
uint8_t IrDA_INSIDE : 1; 186: } FEATURE_bits; 187: }; 188: 189:
__I
uint8_t RESERVED10[3]; 190: 191:
union
{ 192:
__I
uint8_t REVD1; 193: }; 194: 195:
__I
uint8_t RESERVED11[3]; 196: 197:
union
{ 198:
__I
uint8_t REVD2; 199: }; 200: 201:
__I
uint8_t RESERVED12[3]; 202: 203:
union
{ 204:
__I
uint8_t REVD3; 205: }; 206: 207:
__I
uint8_t RESERVED13[3]; 208:
__I
uint32_t RESERVED14[2]; 209: 210:
union
{ 211:
__IO
uint32_t MOD; 212: 213:
struct
{ 214:
__IO
uint32_t FC : 1; 215: uint32_t : 7; 216:
__IO
uint32_t SM : 1; 217:
__IO
uint32_t HM : 1; 218: uint32_t : 6; 219:
__IO
uint32_t TD : 1; 220: } MOD_bits; 221: }; 222: 223:
union
{ 224:
__IO
uint32_t CMD; 225: 226:
struct
{ 227:
__IO
uint32_t ST : 2; 228: } CMD_bits; 229: }; 230: 231:
union
{ 232:
__IO
uint32_t SETUPTIME; 233: }; 234: 235:
union
{ 236:
__IO
uint32_t HOLDTIME; 237: }; 238: 239:
union
{ 240:
__I
uint32_t STAT; 241: 242:
struct
{ 243:
__I
uint32_t RTO : 1; 244: uint32_t : 15; 245:
__I
uint32_t CTO : 1; 246: } STAT_bits; 247: }; 248: 249:
union
{ 250:
__O
uint32_t CLR; 251: 252:
struct
{ 253:
__O
uint32_t RTO : 1; 254: uint32_t : 15; 255:
__O
uint32_t CTO : 1; 256: } CLR_bits; 257: }; 258: 259:
union
{ 260:
__IO
uint32_t INTMASK; 261: 262:
struct
{ 263:
__IO
uint32_t RTO : 1; 264: uint32_t : 15; 265:
__IO
uint32_t CTO : 1; 266: } INTMASK_bits; 267: }; 268: 269:
__I
uint32_t RESERVED15[1]; 270: 271:
union
{ 272:
__IO
uint32_t RECEIVETIME; 273: }; 274: 275:
union
{ 276:
__IO
uint32_t CHARINTERVAL; 277: }; 278: 279:
union
{ 280:
__IO
uint32_t TIMEOUT; 281: }; 282: 283: 284: }
AG903_UARTn_Type
; 285: 286:
#define
AG903_UARTn
(ch) ((
volatile
AG903_UARTn_Type
*)(
AG903_UART0_BASE
+ 0x100000 * ch)) 287:
#define
AG903_UARTn_RBR
(ch)
AG903_UARTn
(ch)->RBR 288:
#define
AG903_UARTn_THR
(ch)
AG903_UARTn
(ch)->THR 289:
#define
AG903_UARTn_DLL
(ch)
AG903_UARTn
(ch)->DLL 290:
#define
AG903_UARTn_IER
(ch)
AG903_UARTn
(ch)->IER 291:
#define
AG903_UARTn_DLM
(ch)
AG903_UARTn
(ch)->DLM 292:
#define
AG903_UARTn_IIR
(ch)
AG903_UARTn
(ch)->IIR 293:
#define
AG903_UARTn_FCR
(ch)
AG903_UARTn
(ch)->FCR 294:
#define
AG903_UARTn_PSR
(ch)
AG903_UARTn
(ch)->PSR 295:
#define
AG903_UARTn_LCR
(ch)
AG903_UARTn
(ch)->LCR 296:
#define
AG903_UARTn_MCR
(ch)
AG903_UARTn
(ch)->MCR 297:
#define
AG903_UARTn_LSR
(ch)
AG903_UARTn
(ch)->LSR 298:
#define
AG903_UARTn_TST
(ch)
AG903_UARTn
(ch)->TST 299:
#define
AG903_UARTn_MSR
(ch)
AG903_UARTn
(ch)->MSR 300:
#define
AG903_UARTn_SPR
(ch)
AG903_UARTn
(ch)->SPR 301:
#define
AG903_UARTn_FEATURE
(ch)
AG903_UARTn
(ch)->FEATURE 302:
#define
AG903_UARTn_REVD1
(ch)
AG903_UARTn
(ch)->REVD1 303:
#define
AG903_UARTn_REVD2
(ch)
AG903_UARTn
(ch)->REVD2 304:
#define
AG903_UARTn_REVD3
(ch)
AG903_UARTn
(ch)->REVD3 305:
#define
AG903_UARTn_MOD
(ch)
AG903_UARTn
(ch)->MOD 306:
#define
AG903_UARTn_CMD
(ch)
AG903_UARTn
(ch)->CMD 307:
#define
AG903_UARTn_SETUPTIME
(ch)
AG903_UARTn
(ch)->SETUPTIME 308:
#define
AG903_UARTn_HOLDTIME
(ch)
AG903_UARTn
(ch)->HOLDTIME 309:
#define
AG903_UARTn_STAT
(ch)
AG903_UARTn
(ch)->STAT 310:
#define
AG903_UARTn_CLR
(ch)
AG903_UARTn
(ch)->CLR 311:
#define
AG903_UARTn_INTMASK
(ch)
AG903_UARTn
(ch)->INTMASK 312:
#define
AG903_UARTn_RECEIVETIME
(ch)
AG903_UARTn
(ch)->RECEIVETIME 313:
#define
AG903_UARTn_CHARINTERVAL
(ch)
AG903_UARTn
(ch)->CHARINTERVAL 314:
#define
AG903_UARTn_TIMEOUT
(ch)
AG903_UARTn
(ch)->TIMEOUT 315: 316:
#define
AG903_UART0
((
volatile
AG903_UARTn_Type
*)
AG903_UART0_BASE
) 317:
#define
AG903_UART1
((
volatile
AG903_UARTn_Type
*)
AG903_UART1_BASE
) 318:
#define
AG903_UART2
((
volatile
AG903_UARTn_Type
*)
AG903_UART2_BASE
) 319:
#define
AG903_UART3
((
volatile
AG903_UARTn_Type
*)
AG903_UART3_BASE
) 320: 321: 322:
#define
AG903_UARTn_RBR_RBR_POS
0 323:
#define
AG903_UARTn_RBR_RBR_MSK
(0xffU <<
AG903_UARTn_RBR_RBR_POS
) 324: 325:
#define
AG903_UARTn_THR_THR_POS
0 326:
#define
AG903_UARTn_THR_THR_MSK
(0xffU <<
AG903_UARTn_THR_THR_POS
) 327: 328:
#define
AG903_UARTn_DLL_DLL_POS
0 329:
#define
AG903_UARTn_DLL_DLL_MSK
(0xffU <<
AG903_UARTn_DLL_DLL_POS
) 330: 331:
#define
AG903_UARTn_IER_Receiver_Data_Available_POS
0 332:
#define
AG903_UARTn_IER_Receiver_Data_Available_MSK
(0x1U <<
AG903_UARTn_IER_Receiver_Data_Available_POS
) 333:
#define
AG903_UARTn_IER_THR_Empty_POS
1 334:
#define
AG903_UARTn_IER_THR_Empty_MSK
(0x1U <<
AG903_UARTn_IER_THR_Empty_POS
) 335:
#define
AG903_UARTn_IER_Receiver_Line_Status_POS
2 336:
#define
AG903_UARTn_IER_Receiver_Line_Status_MSK
(0x1U <<
AG903_UARTn_IER_Receiver_Line_Status_POS
) 337:
#define
AG903_UARTn_IER_MODEM_Status_POS
3 338:
#define
AG903_UARTn_IER_MODEM_Status_MSK
(0x1U <<
AG903_UARTn_IER_MODEM_Status_POS
) 339:
#define
AG903_UARTn_IER_RTSEn_POS
4 340:
#define
AG903_UARTn_IER_RTSEn_MSK
(0x1U <<
AG903_UARTn_IER_RTSEn_POS
) 341:
#define
AG903_UARTn_IER_CTSEn_POS
5 342:
#define
AG903_UARTn_IER_CTSEn_MSK
(0x1U <<
AG903_UARTn_IER_CTSEn_POS
) 343:
#define
AG903_UARTn_IER_DTREn_POS
6 344:
#define
AG903_UARTn_IER_DTREn_MSK
(0x1U <<
AG903_UARTn_IER_DTREn_POS
) 345:
#define
AG903_UARTn_IER_DSREn_POS
7 346:
#define
AG903_UARTn_IER_DSREn_MSK
(0x1U <<
AG903_UARTn_IER_DSREn_POS
) 347: 348:
#define
AG903_UARTn_DLM_DLM_POS
0 349:
#define
AG903_UARTn_DLM_DLM_MSK
(0xffU <<
AG903_UARTn_DLM_DLM_POS
) 350: 351:
#define
AG903_UARTn_IIR_Interrupt_Pending_POS
0 352:
#define
AG903_UARTn_IIR_Interrupt_Pending_MSK
(0x1U <<
AG903_UARTn_IIR_Interrupt_Pending_POS
) 353:
#define
AG903_UARTn_IIR_Interrupt_Identification_Code_POS
1 354:
#define
AG903_UARTn_IIR_Interrupt_Identification_Code_MSK
(0x3U <<
AG903_UARTn_IIR_Interrupt_Identification_Code_POS
) 355:
#define
AG903_UARTn_IIR_FIFO_mode_only_POS
3 356:
#define
AG903_UARTn_IIR_FIFO_mode_only_MSK
(0x1U <<
AG903_UARTn_IIR_FIFO_mode_only_POS
) 357:
#define
AG903_UARTn_IIR_Tx_FIFO_full_POS
4 358:
#define
AG903_UARTn_IIR_Tx_FIFO_full_MSK
(0x1U <<
AG903_UARTn_IIR_Tx_FIFO_full_POS
) 359:
#define
AG903_UARTn_IIR_FIFO_mode_enable_POS
6 360:
#define
AG903_UARTn_IIR_FIFO_mode_enable_MSK
(0x3U <<
AG903_UARTn_IIR_FIFO_mode_enable_POS
) 361: 362:
#define
AG903_UARTn_FCR_FIFO_Enable_POS
0 363:
#define
AG903_UARTn_FCR_FIFO_Enable_MSK
(0x1U <<
AG903_UARTn_FCR_FIFO_Enable_POS
) 364:
#define
AG903_UARTn_FCR_RX_FIFO_Reset_POS
1 365:
#define
AG903_UARTn_FCR_RX_FIFO_Reset_MSK
(0x1U <<
AG903_UARTn_FCR_RX_FIFO_Reset_POS
) 366:
#define
AG903_UARTn_FCR_TX_FIFO_Reset_POS
2 367:
#define
AG903_UARTn_FCR_TX_FIFO_Reset_MSK
(0x1U <<
AG903_UARTn_FCR_TX_FIFO_Reset_POS
) 368:
#define
AG903_UARTn_FCR_DMA_Mode_POS
3 369:
#define
AG903_UARTn_FCR_DMA_Mode_MSK
(0x1U <<
AG903_UARTn_FCR_DMA_Mode_POS
) 370:
#define
AG903_UARTn_FCR_RXFIFO_TRGL_POS
6 371:
#define
AG903_UARTn_FCR_RXFIFO_TRGL_MSK
(0x3U <<
AG903_UARTn_FCR_RXFIFO_TRGL_POS
) 372: 373:
#define
AG903_UARTn_PSR_PSR_POS
0 374:
#define
AG903_UARTn_PSR_PSR_MSK
(0x1fU <<
AG903_UARTn_PSR_PSR_POS
) 375: 376:
#define
AG903_UARTn_LCR_WL0_POS
0 377:
#define
AG903_UARTn_LCR_WL0_MSK
(0x1U <<
AG903_UARTn_LCR_WL0_POS
) 378:
#define
AG903_UARTn_LCR_WL1_POS
1 379:
#define
AG903_UARTn_LCR_WL1_MSK
(0x1U <<
AG903_UARTn_LCR_WL1_POS
) 380:
#define
AG903_UARTn_LCR_Stop_Bits_POS
2 381:
#define
AG903_UARTn_LCR_Stop_Bits_MSK
(0x1U <<
AG903_UARTn_LCR_Stop_Bits_POS
) 382:
#define
AG903_UARTn_LCR_Parity_Enable_POS
3 383:
#define
AG903_UARTn_LCR_Parity_Enable_MSK
(0x1U <<
AG903_UARTn_LCR_Parity_Enable_POS
) 384:
#define
AG903_UARTn_LCR_Even_Parity_POS
4 385:
#define
AG903_UARTn_LCR_Even_Parity_MSK
(0x1U <<
AG903_UARTn_LCR_Even_Parity_POS
) 386:
#define
AG903_UARTn_LCR_Stick_Parity_POS
5 387:
#define
AG903_UARTn_LCR_Stick_Parity_MSK
(0x1U <<
AG903_UARTn_LCR_Stick_Parity_POS
) 388:
#define
AG903_UARTn_LCR_Set_Break_POS
6 389:
#define
AG903_UARTn_LCR_Set_Break_MSK
(0x1U <<
AG903_UARTn_LCR_Set_Break_POS
) 390:
#define
AG903_UARTn_LCR_DLAB_POS
7 391:
#define
AG903_UARTn_LCR_DLAB_MSK
(0x1U <<
AG903_UARTn_LCR_DLAB_POS
) 392: 393:
#define
AG903_UARTn_MCR_DTR_POS
0 394:
#define
AG903_UARTn_MCR_DTR_MSK
(0x1U <<
AG903_UARTn_MCR_DTR_POS
) 395:
#define
AG903_UARTn_MCR_RTS_POS
1 396:
#define
AG903_UARTn_MCR_RTS_MSK
(0x1U <<
AG903_UARTn_MCR_RTS_POS
) 397:
#define
AG903_UARTn_MCR_Out1_POS
2 398:
#define
AG903_UARTn_MCR_Out1_MSK
(0x1U <<
AG903_UARTn_MCR_Out1_POS
) 399:
#define
AG903_UARTn_MCR_Out2_POS
3 400:
#define
AG903_UARTn_MCR_Out2_MSK
(0x1U <<
AG903_UARTn_MCR_Out2_POS
) 401:
#define
AG903_UARTn_MCR_Loop_POS
4 402:
#define
AG903_UARTn_MCR_Loop_MSK
(0x1U <<
AG903_UARTn_MCR_Loop_POS
) 403:
#define
AG903_UARTn_MCR_DMAmode2_POS
5 404:
#define
AG903_UARTn_MCR_DMAmode2_MSK
(0x1U <<
AG903_UARTn_MCR_DMAmode2_POS
) 405:
#define
AG903_UARTn_MCR_Out3_POS
6 406:
#define
AG903_UARTn_MCR_Out3_MSK
(0x1U <<
AG903_UARTn_MCR_Out3_POS
) 407: 408:
#define
AG903_UARTn_LSR_Data_Ready_POS
0 409:
#define
AG903_UARTn_LSR_Data_Ready_MSK
(0x1U <<
AG903_UARTn_LSR_Data_Ready_POS
) 410:
#define
AG903_UARTn_LSR_Overrun_Error_POS
1 411:
#define
AG903_UARTn_LSR_Overrun_Error_MSK
(0x1U <<
AG903_UARTn_LSR_Overrun_Error_POS
) 412:
#define
AG903_UARTn_LSR_Parity_Error_POS
2 413:
#define
AG903_UARTn_LSR_Parity_Error_MSK
(0x1U <<
AG903_UARTn_LSR_Parity_Error_POS
) 414:
#define
AG903_UARTn_LSR_Framing_Error_POS
3 415:
#define
AG903_UARTn_LSR_Framing_Error_MSK
(0x1U <<
AG903_UARTn_LSR_Framing_Error_POS
) 416:
#define
AG903_UARTn_LSR_Break_Interrupt_POS
4 417:
#define
AG903_UARTn_LSR_Break_Interrupt_MSK
(0x1U <<
AG903_UARTn_LSR_Break_Interrupt_POS
) 418:
#define
AG903_UARTn_LSR_THR_Empty_POS
5 419:
#define
AG903_UARTn_LSR_THR_Empty_MSK
(0x1U <<
AG903_UARTn_LSR_THR_Empty_POS
) 420:
#define
AG903_UARTn_LSR_Transmitter_Empty_POS
6 421:
#define
AG903_UARTn_LSR_Transmitter_Empty_MSK
(0x1U <<
AG903_UARTn_LSR_Transmitter_Empty_POS
) 422:
#define
AG903_UARTn_LSR_FIFO_Data_Error_POS
7 423:
#define
AG903_UARTn_LSR_FIFO_Data_Error_MSK
(0x1U <<
AG903_UARTn_LSR_FIFO_Data_Error_POS
) 424: 425:
#define
AG903_UARTn_TST_TEST_PAR_ERR_POS
0 426:
#define
AG903_UARTn_TST_TEST_PAR_ERR_MSK
(0x1U <<
AG903_UARTn_TST_TEST_PAR_ERR_POS
) 427:
#define
AG903_UARTn_TST_TEST_FRM_ERR_POS
1 428:
#define
AG903_UARTn_TST_TEST_FRM_ERR_MSK
(0x1U <<
AG903_UARTn_TST_TEST_FRM_ERR_POS
) 429:
#define
AG903_UARTn_TST_TEST_BAUDGEN_POS
2 430:
#define
AG903_UARTn_TST_TEST_BAUDGEN_MSK
(0x1U <<
AG903_UARTn_TST_TEST_BAUDGEN_POS
) 431:
#define
AG903_UARTn_TST_TEST_PHY_ERR_POS
3 432:
#define
AG903_UARTn_TST_TEST_PHY_ERR_MSK
(0x1U <<
AG903_UARTn_TST_TEST_PHY_ERR_POS
) 433:
#define
AG903_UARTn_TST_TEST_CRC_ERR_POS
4 434:
#define
AG903_UARTn_TST_TEST_CRC_ERR_MSK
(0x1U <<
AG903_UARTn_TST_TEST_CRC_ERR_POS
) 435: 436:
#define
AG903_UARTn_MSR_Delta_CTS_POS
0 437:
#define
AG903_UARTn_MSR_Delta_CTS_MSK
(0x1U <<
AG903_UARTn_MSR_Delta_CTS_POS
) 438:
#define
AG903_UARTn_MSR_Delta_DSR_POS
1 439:
#define
AG903_UARTn_MSR_Delta_DSR_MSK
(0x1U <<
AG903_UARTn_MSR_Delta_DSR_POS
) 440:
#define
AG903_UARTn_MSR_Trailing_edge_R1_POS
2 441:
#define
AG903_UARTn_MSR_Trailing_edge_R1_MSK
(0x1U <<
AG903_UARTn_MSR_Trailing_edge_R1_POS
) 442:
#define
AG903_UARTn_MSR_Delta_DCD_POS
3 443:
#define
AG903_UARTn_MSR_Delta_DCD_MSK
(0x1U <<
AG903_UARTn_MSR_Delta_DCD_POS
) 444:
#define
AG903_UARTn_MSR_CTS_POS
4 445:
#define
AG903_UARTn_MSR_CTS_MSK
(0x1U <<
AG903_UARTn_MSR_CTS_POS
) 446:
#define
AG903_UARTn_MSR_DSR_POS
5 447:
#define
AG903_UARTn_MSR_DSR_MSK
(0x1U <<
AG903_UARTn_MSR_DSR_POS
) 448:
#define
AG903_UARTn_MSR_RI_POS
6 449:
#define
AG903_UARTn_MSR_RI_MSK
(0x1U <<
AG903_UARTn_MSR_RI_POS
) 450:
#define
AG903_UARTn_MSR_DCD_POS
7 451:
#define
AG903_UARTn_MSR_DCD_MSK
(0x1U <<
AG903_UARTn_MSR_DCD_POS
) 452: 453:
#define
AG903_UARTn_SPR_User_Data_POS
0 454:
#define
AG903_UARTn_SPR_User_Data_MSK
(0xffU <<
AG903_UARTn_SPR_User_Data_POS
) 455: 456:
#define
AG903_UARTn_FEATURE_FIFO_DEPTH_POS
0 457:
#define
AG903_UARTn_FEATURE_FIFO_DEPTH_MSK
(0xfU <<
AG903_UARTn_FEATURE_FIFO_DEPTH_POS
) 458:
#define
AG903_UARTn_FEATURE_IrDA_INSIDE_POS
4 459:
#define
AG903_UARTn_FEATURE_IrDA_INSIDE_MSK
(0x1U <<
AG903_UARTn_FEATURE_IrDA_INSIDE_POS
) 460: 461:
#define
AG903_UARTn_REVD1_REVD1_POS
0 462:
#define
AG903_UARTn_REVD1_REVD1_MSK
(0xffU <<
AG903_UARTn_REVD1_REVD1_POS
) 463: 464:
#define
AG903_UARTn_REVD2_REVD2_POS
0 465:
#define
AG903_UARTn_REVD2_REVD2_MSK
(0xffU <<
AG903_UARTn_REVD2_REVD2_POS
) 466: 467:
#define
AG903_UARTn_REVD3_REVD3_POS
0 468:
#define
AG903_UARTn_REVD3_REVD3_MSK
(0xffU <<
AG903_UARTn_REVD3_REVD3_POS
) 469: 470:
#define
AG903_UARTn_MOD_FC_POS
0 471:
#define
AG903_UARTn_MOD_FC_MSK
(0x1UL <<
AG903_UARTn_MOD_FC_POS
) 472:
#define
AG903_UARTn_MOD_SM_POS
8 473:
#define
AG903_UARTn_MOD_SM_MSK
(0x1UL <<
AG903_UARTn_MOD_SM_POS
) 474:
#define
AG903_UARTn_MOD_HM_POS
9 475:
#define
AG903_UARTn_MOD_HM_MSK
(0x1UL <<
AG903_UARTn_MOD_HM_POS
) 476:
#define
AG903_UARTn_MOD_TD_POS
16 477:
#define
AG903_UARTn_MOD_TD_MSK
(0x1UL <<
AG903_UARTn_MOD_TD_POS
) 478: 479:
#define
AG903_UARTn_CMD_ST_POS
0 480:
#define
AG903_UARTn_CMD_ST_MSK
(0x3UL <<
AG903_UARTn_CMD_ST_POS
) 481: 482:
#define
AG903_UARTn_SETUPTIME_TIME_POS
0 483:
#define
AG903_UARTn_SETUPTIME_TIME_MSK
(0xffffffffUL <<
AG903_UARTn_SETUPTIME_TIME_POS
) 484: 485:
#define
AG903_UARTn_HOLDTIME_TIME_POS
0 486:
#define
AG903_UARTn_HOLDTIME_TIME_MSK
(0xffffffffUL <<
AG903_UARTn_HOLDTIME_TIME_POS
) 487: 488:
#define
AG903_UARTn_STAT_RTO_POS
0 489:
#define
AG903_UARTn_STAT_RTO_MSK
(0x1UL <<
AG903_UARTn_STAT_RTO_POS
) 490:
#define
AG903_UARTn_STAT_CTO_POS
16 491:
#define
AG903_UARTn_STAT_CTO_MSK
(0x1UL <<
AG903_UARTn_STAT_CTO_POS
) 492: 493:
#define
AG903_UARTn_CLR_RTO_POS
0 494:
#define
AG903_UARTn_CLR_RTO_MSK
(0x1UL <<
AG903_UARTn_CLR_RTO_POS
) 495:
#define
AG903_UARTn_CLR_CTO_POS
16 496:
#define
AG903_UARTn_CLR_CTO_MSK
(0x1UL <<
AG903_UARTn_CLR_CTO_POS
) 497: 498:
#define
AG903_UARTn_INTMASK_RTO_POS
0 499:
#define
AG903_UARTn_INTMASK_RTO_MSK
(0x1UL <<
AG903_UARTn_INTMASK_RTO_POS
) 500:
#define
AG903_UARTn_INTMASK_CTO_POS
16 501:
#define
AG903_UARTn_INTMASK_CTO_MSK
(0x1UL <<
AG903_UARTn_INTMASK_CTO_POS
) 502: 503:
#define
AG903_UARTn_RECEIVETIME_TIME_POS
0 504:
#define
AG903_UARTn_RECEIVETIME_TIME_MSK
(0xffffffffUL <<
AG903_UARTn_RECEIVETIME_TIME_POS
) 505: 506:
#define
AG903_UARTn_CHARINTERVAL_TIME_POS
0 507:
#define
AG903_UARTn_CHARINTERVAL_TIME_MSK
(0xffffffffUL <<
AG903_UARTn_CHARINTERVAL_TIME_POS
) 508: 509:
#define
AG903_UARTn_TIMEOUT_TIME_POS
0 510:
#define
AG903_UARTn_TIMEOUT_TIME_MSK
(0xffffffffUL <<
AG903_UARTn_TIMEOUT_TIME_POS
) 511: 512:
#endif
513:
Copyright (c) 2017-2025 Axell Corporation. All rights reserved.
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