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AG903_hdareg.h

HDA Register Definition

HDA Register Definition

none

AXELL CORPORATION

2017_10_20 Auto-generated.

1: 8: 9: 13: 14: #ifndef _AG903_HDA_REGMAP_H_ 15: #define _AG903_HDA_REGMAP_H_ 16: 17: 18: #include "AG903_regmap.h" 19: 20: #ifndef __I 21: 22: #define __I volatile const 23: #endif 24: #ifndef __O 25: 26: #define __O volatile 27: #endif 28: #ifndef __IO 29: 30: #define __IO volatile 31: #endif 32: 33: 34: typedef struct { 35: 36: union { 37: __I uint16_t GCAP; 38: 39: struct { 40: __I uint16_t OK64 : 1; 41: __I uint16_t NSDO : 2; 42: __I uint16_t BSS : 5; 43: __I uint16_t ISS : 4; 44: __I uint16_t OSS : 4; 45: } GCAP_bits; 46: }; 47: 48: union { 49: __I uint8_t VMIN; 50: }; 51: 52: union { 53: __I uint8_t VMAJ; 54: }; 55: 56: union { 57: __I uint16_t OUTPAY; 58: }; 59: 60: union { 61: __I uint16_t INPAY; 62: }; 63: 64: union { 65: __IO uint32_t GCTL; 66: 67: struct { 68: __IO uint32_t CRST : 1; 69: __IO uint32_t FCNTRL : 1; 70: uint32_t : 6; 71: __IO uint32_t UNSOL : 1; 72: } GCTL_bits; 73: }; 74: 75: union { 76: __IO uint16_t WAKEEN; 77: 78: struct { 79: __IO uint16_t SDIWEN : 15; 80: } WAKEEN_bits; 81: }; 82: 83: union { 84: __IO uint16_t WAKESTS; 85: 86: struct { 87: __IO uint16_t SDIWAKE : 15; 88: } WAKESTS_bits; 89: }; 90: 91: union { 92: __IO uint16_t GSTS; 93: 94: struct { 95: uint16_t : 1; 96: __IO uint16_t FSTS : 1; 97: } GSTS_bits; 98: }; 99: 100: __I uint8_t RESERVED1[2]; 101: __I uint32_t RESERVED2[1]; 102: 103: union { 104: __I uint16_t OUTSTRMPAY; 105: }; 106: 107: union { 108: __I uint16_t INSTRMPAY; 109: }; 110: 111: __I uint32_t RESERVED3[1]; 112: 113: union { 114: __IO uint32_t INTCTL; 115: 116: struct { 117: __IO uint32_t SIE : 30; 118: __IO uint32_t CIE : 1; 119: __IO uint32_t GIE : 1; 120: } INTCTL_bits; 121: }; 122: 123: union { 124: __I uint32_t INTSTS; 125: 126: struct { 127: __I uint32_t SIS : 30; 128: __I uint32_t CIS : 1; 129: __I uint32_t GIS : 1; 130: } INTSTS_bits; 131: }; 132: 133: __I uint32_t RESERVED4[2]; 134: 135: union { 136: __I uint32_t WALCLK; 137: }; 138: 139: __I uint32_t RESERVED5[1]; 140: 141: union { 142: __IO uint32_t SSYNC; 143: 144: struct { 145: __IO uint32_t SSYNC : 30; 146: } SSYNC_bits; 147: }; 148: 149: __I uint32_t RESERVED6[1]; 150: 151: union { 152: __IO uint32_t CORBLBASE; 153: 154: struct { 155: uint32_t : 7; 156: __IO uint32_t CORBLBASE : 25; 157: } CORBLBASE_bits; 158: }; 159: 160: union { 161: __IO uint32_t CORBUBASE; 162: }; 163: 164: union { 165: __IO uint16_t CORBWP; 166: 167: struct { 168: __IO uint16_t CORBWP : 8; 169: } CORBWP_bits; 170: }; 171: 172: union { 173: __IO uint16_t CORBRP; 174: 175: struct { 176: __I uint16_t CORBRP : 8; 177: uint16_t : 7; 178: __IO uint16_t CORBRPRST : 1; 179: } CORBRP_bits; 180: }; 181: 182: union { 183: __IO uint8_t CORBCTL; 184: 185: struct { 186: __IO uint8_t CMEIE : 1; 187: __IO uint8_t CORBRUN : 1; 188: } CORBCTL_bits; 189: }; 190: 191: union { 192: __IO uint8_t CORBSTS; 193: 194: struct { 195: __IO uint8_t CMEI : 1; 196: } CORBSTS_bits; 197: }; 198: 199: union { 200: __I uint8_t CORBSIZE; 201: 202: struct { 203: __I uint8_t CORBSIZE : 2; 204: uint8_t : 2; 205: __I uint8_t CORBSZCAP : 4; 206: } CORBSIZE_bits; 207: }; 208: 209: __I uint8_t RESERVED7[1]; 210: 211: union { 212: __IO uint32_t RIRBLBASE; 213: 214: struct { 215: uint32_t : 7; 216: __IO uint32_t RIRBLBASE : 25; 217: } RIRBLBASE_bits; 218: }; 219: 220: union { 221: __IO uint32_t RIRBUBASE; 222: }; 223: 224: union { 225: __IO uint16_t RIRBWP; 226: 227: struct { 228: __I uint16_t RIRBWP : 8; 229: uint16_t : 7; 230: __O uint16_t RIRBWPRST : 1; 231: } RIRBWP_bits; 232: }; 233: 234: union { 235: __IO uint16_t RINTCNT; 236: 237: struct { 238: __IO uint16_t RINTCNT : 8; 239: } RINTCNT_bits; 240: }; 241: 242: union { 243: __IO uint8_t RIRBCTL; 244: 245: struct { 246: __IO uint8_t RINTCTL : 1; 247: __IO uint8_t RIRBDMAEN : 1; 248: __IO uint8_t RIRBOIC : 1; 249: } RIRBCTL_bits; 250: }; 251: 252: union { 253: __IO uint8_t RIRBSTS; 254: 255: struct { 256: __IO uint8_t RINTFL : 1; 257: uint8_t : 1; 258: __IO uint8_t RIRBOIS : 1; 259: } RIRBSTS_bits; 260: }; 261: 262: union { 263: __I uint8_t RIRBSIZE; 264: 265: struct { 266: __I uint8_t RIRBSIZE : 2; 267: uint8_t : 2; 268: __I uint8_t RIRBSZCAP : 4; 269: } RIRBSIZE_bits; 270: }; 271: 272: __I uint8_t RESERVED8[1]; 273: 274: union { 275: __I uint32_t ICOI; 276: }; 277: 278: union { 279: __I uint32_t IRII; 280: }; 281: 282: union { 283: __IO uint16_t ICS; 284: 285: struct { 286: __IO uint16_t ICB : 1; 287: __IO uint16_t IRV : 1; 288: __I uint16_t ICV : 1; 289: __I uint16_t IRRUNSOL : 1; 290: __I uint16_t IRRADD : 4; 291: } ICS_bits; 292: }; 293: 294: __I uint8_t RESERVED9[2]; 295: __I uint32_t RESERVED10[1]; 296: 297: union { 298: __IO uint32_t DPLBASE; 299: 300: struct { 301: __IO uint32_t DPBE : 1; 302: uint32_t : 6; 303: __IO uint32_t DPLBASE : 25; 304: } DPLBASE_bits; 305: }; 306: 307: union { 308: __IO uint32_t DPUBASE; 309: }; 310: 311: __I uint32_t RESERVED11[2]; 312: 313: union { 314: __IO uint8_t ISD0CTLL; 315: 316: struct { 317: __IO uint8_t SRST : 1; 318: __IO uint8_t RUN : 1; 319: __IO uint8_t IOCE : 1; 320: __IO uint8_t FEIE : 1; 321: __IO uint8_t DEIE : 1; 322: } ISD0CTLL_bits; 323: }; 324: 325: __I uint8_t RESERVED12[1]; 326: 327: union { 328: __IO uint8_t ISD0CTLU; 329: 330: struct { 331: __IO uint8_t STRIPE : 2; 332: __IO uint8_t TP : 1; 333: __IO uint8_t DIR : 1; 334: __IO uint8_t STRM : 4; 335: } ISD0CTLU_bits; 336: }; 337: 338: union { 339: __IO uint8_t ISD0STS; 340: 341: struct { 342: uint8_t : 2; 343: __IO uint8_t BCIS : 1; 344: __IO uint8_t FIFOE : 1; 345: __IO uint8_t DESE : 1; 346: __I uint8_t FIFORDY : 1; 347: } ISD0STS_bits; 348: }; 349: 350: union { 351: __I uint32_t ISD0LPIB; 352: }; 353: 354: union { 355: __IO uint32_t ISD0CBL; 356: }; 357: 358: union { 359: __IO uint16_t ISD0LVI; 360: 361: struct { 362: __IO uint16_t LVI : 8; 363: } ISD0LVI_bits; 364: }; 365: 366: __I uint8_t RESERVED13[2]; 367: 368: union { 369: __I uint16_t ISD0FIFOS; 370: }; 371: 372: union { 373: __IO uint16_t ISD0FMT; 374: 375: struct { 376: __IO uint16_t CHAN : 4; 377: __IO uint16_t BITS : 3; 378: uint16_t : 1; 379: __IO uint16_t DIV : 3; 380: __IO uint16_t MULT : 3; 381: __IO uint16_t BASE : 1; 382: } ISD0FMT_bits; 383: }; 384: 385: __I uint32_t RESERVED14[1]; 386: 387: union { 388: __IO uint32_t ISD0BDPL; 389: 390: struct { 391: uint32_t : 7; 392: __IO uint32_t BDLLBASE : 25; 393: } ISD0BDPL_bits; 394: }; 395: 396: union { 397: __IO uint32_t ISD0BDPU; 398: }; 399: 400: union { 401: __IO uint8_t OSD0CTLL; 402: 403: struct { 404: __IO uint8_t SRST : 1; 405: __IO uint8_t RUN : 1; 406: __IO uint8_t IOCE : 1; 407: __IO uint8_t FEIE : 1; 408: __IO uint8_t DEIE : 1; 409: } OSD0CTLL_bits; 410: }; 411: 412: __I uint8_t RESERVED15[1]; 413: 414: union { 415: __IO uint8_t OSD0CTLU; 416: 417: struct { 418: __IO uint8_t STRIPE : 2; 419: __IO uint8_t TP : 1; 420: __IO uint8_t DIR : 1; 421: __IO uint8_t STRM : 4; 422: } OSD0CTLU_bits; 423: }; 424: 425: union { 426: __IO uint8_t OSD0STS; 427: 428: struct { 429: uint8_t : 2; 430: __IO uint8_t BCIS : 1; 431: __IO uint8_t FIFOE : 1; 432: __IO uint8_t DESE : 1; 433: __I uint8_t FIFORDY : 1; 434: } OSD0STS_bits; 435: }; 436: 437: union { 438: __I uint32_t OSD0LPIB; 439: }; 440: 441: union { 442: __IO uint32_t OSD0CBL; 443: }; 444: 445: union { 446: __IO uint16_t OSD0LVI; 447: 448: struct { 449: __IO uint16_t LVI : 8; 450: } OSD0LVI_bits; 451: }; 452: 453: __I uint8_t RESERVED16[2]; 454: 455: union { 456: __I uint16_t OSD0FIFOS; 457: }; 458: 459: union { 460: __IO uint16_t OSD0FMT; 461: 462: struct { 463: __IO uint16_t CHAN : 4; 464: __IO uint16_t BITS : 3; 465: uint16_t : 1; 466: __IO uint16_t DIV : 3; 467: __IO uint16_t MULT : 3; 468: __IO uint16_t BASE : 1; 469: } OSD0FMT_bits; 470: }; 471: 472: __I uint32_t RESERVED17[1]; 473: 474: union { 475: __IO uint32_t OSD0BDPL; 476: 477: struct { 478: uint32_t : 7; 479: __IO uint32_t BDLLBASE : 25; 480: } OSD0BDPL_bits; 481: }; 482: 483: union { 484: __IO uint32_t OSD0BDPU; 485: }; 486: 487: union { 488: __IO uint8_t OSD1CTLL; 489: 490: struct { 491: __IO uint8_t SRST : 1; 492: __IO uint8_t RUN : 1; 493: __IO uint8_t IOCE : 1; 494: __IO uint8_t FEIE : 1; 495: __IO uint8_t DEIE : 1; 496: } OSD1CTLL_bits; 497: }; 498: 499: __I uint8_t RESERVED18[1]; 500: 501: union { 502: __IO uint8_t OSD1CTLU; 503: 504: struct { 505: __IO uint8_t STRIPE : 2; 506: __IO uint8_t TP : 1; 507: __IO uint8_t DIR : 1; 508: __IO uint8_t STRM : 4; 509: } OSD1CTLU_bits; 510: }; 511: 512: union { 513: __IO uint8_t OSD1STS; 514: 515: struct { 516: uint8_t : 2; 517: __IO uint8_t BCIS : 1; 518: __IO uint8_t FIFOE : 1; 519: __IO uint8_t DESE : 1; 520: __I uint8_t FIFORDY : 1; 521: } OSD1STS_bits; 522: }; 523: 524: union { 525: __I uint32_t OSD1LPIB; 526: }; 527: 528: union { 529: __IO uint32_t OSD1CBL; 530: }; 531: 532: union { 533: __IO uint16_t OSD1LVI; 534: 535: struct { 536: __IO uint16_t LVI : 8; 537: } OSD1LVI_bits; 538: }; 539: 540: __I uint8_t RESERVED19[2]; 541: 542: union { 543: __I uint16_t OSD1FIFOS; 544: }; 545: 546: union { 547: __IO uint16_t OSD1FMT; 548: 549: struct { 550: __IO uint16_t CHAN : 4; 551: __IO uint16_t BITS : 3; 552: uint16_t : 1; 553: __IO uint16_t DIV : 3; 554: __IO uint16_t MULT : 3; 555: __IO uint16_t BASE : 1; 556: } OSD1FMT_bits; 557: }; 558: 559: __I uint32_t RESERVED20[1]; 560: 561: union { 562: __IO uint32_t OSD1BDPL; 563: 564: struct { 565: uint32_t : 7; 566: __IO uint32_t BDLLBASE : 25; 567: } OSD1BDPL_bits; 568: }; 569: 570: union { 571: __IO uint32_t OSD1BDPU; 572: }; 573: 574: union { 575: __IO uint8_t OSD2CTLL; 576: 577: struct { 578: __IO uint8_t SRST : 1; 579: __IO uint8_t RUN : 1; 580: __IO uint8_t IOCE : 1; 581: __IO uint8_t FEIE : 1; 582: __IO uint8_t DEIE : 1; 583: } OSD2CTLL_bits; 584: }; 585: 586: __I uint8_t RESERVED21[1]; 587: 588: union { 589: __IO uint8_t OSD2CTLU; 590: 591: struct { 592: __IO uint8_t STRIPE : 2; 593: __IO uint8_t TP : 1; 594: __IO uint8_t DIR : 1; 595: __IO uint8_t STRM : 4; 596: } OSD2CTLU_bits; 597: }; 598: 599: union { 600: __IO uint8_t OSD2STS; 601: 602: struct { 603: uint8_t : 2; 604: __IO uint8_t BCIS : 1; 605: __IO uint8_t FIFOE : 1; 606: __IO uint8_t DESE : 1; 607: __I uint8_t FIFORDY : 1; 608: } OSD2STS_bits; 609: }; 610: 611: union { 612: __I uint32_t OSD2LPIB; 613: }; 614: 615: union { 616: __IO uint32_t OSD2CBL; 617: }; 618: 619: union { 620: __IO uint16_t OSD2LVI; 621: 622: struct { 623: __IO uint16_t LVI : 8; 624: } OSD2LVI_bits; 625: }; 626: 627: __I uint8_t RESERVED22[2]; 628: 629: union { 630: __I uint16_t OSD2FIFOS; 631: }; 632: 633: union { 634: __IO uint16_t OSD2FMT; 635: 636: struct { 637: __IO uint16_t CHAN : 4; 638: __IO uint16_t BITS : 3; 639: uint16_t : 1; 640: __IO uint16_t DIV : 3; 641: __IO uint16_t MULT : 3; 642: __IO uint16_t BASE : 1; 643: } OSD2FMT_bits; 644: }; 645: 646: __I uint32_t RESERVED23[1]; 647: 648: union { 649: __IO uint32_t OSD2BDPL; 650: 651: struct { 652: uint32_t : 7; 653: __IO uint32_t BDLLBASE : 25; 654: } OSD2BDPL_bits; 655: }; 656: 657: union { 658: __IO uint32_t OSD2BDPU; 659: }; 660: 661: union { 662: __IO uint8_t OSD3CTLL; 663: 664: struct { 665: __IO uint8_t SRST : 1; 666: __IO uint8_t RUN : 1; 667: __IO uint8_t IOCE : 1; 668: __IO uint8_t FEIE : 1; 669: __IO uint8_t DEIE : 1; 670: } OSD3CTLL_bits; 671: }; 672: 673: __I uint8_t RESERVED24[1]; 674: 675: union { 676: __IO uint8_t OSD3CTLU; 677: 678: struct { 679: __IO uint8_t STRIPE : 2; 680: __IO uint8_t TP : 1; 681: __IO uint8_t DIR : 1; 682: __IO uint8_t STRM : 4; 683: } OSD3CTLU_bits; 684: }; 685: 686: union { 687: __IO uint8_t OSD3STS; 688: 689: struct { 690: uint8_t : 2; 691: __IO uint8_t BCIS : 1; 692: __IO uint8_t FIFOE : 1; 693: __IO uint8_t DESE : 1; 694: __I uint8_t FIFORDY : 1; 695: } OSD3STS_bits; 696: }; 697: 698: union { 699: __I uint32_t OSD3LPIB; 700: }; 701: 702: union { 703: __IO uint32_t OSD3CBL; 704: }; 705: 706: union { 707: __IO uint16_t OSD3LVI; 708: 709: struct { 710: __IO uint16_t LVI : 8; 711: } OSD3LVI_bits; 712: }; 713: 714: __I uint8_t RESERVED25[2]; 715: 716: union { 717: __I uint16_t OSD3FIFOS; 718: }; 719: 720: union { 721: __IO uint16_t OSD3FMT; 722: 723: struct { 724: __IO uint16_t CHAN : 4; 725: __IO uint16_t BITS : 3; 726: uint16_t : 1; 727: __IO uint16_t DIV : 3; 728: __IO uint16_t MULT : 3; 729: __IO uint16_t BASE : 1; 730: } OSD3FMT_bits; 731: }; 732: 733: __I uint32_t RESERVED26[1]; 734: 735: union { 736: __IO uint32_t OSD3BDPL; 737: 738: struct { 739: uint32_t : 7; 740: __IO uint32_t BDLLBASE : 25; 741: } OSD3BDPL_bits; 742: }; 743: 744: union { 745: __IO uint32_t OSD3BDPU; 746: }; 747: 748: __I uint32_t RESERVED27[1988]; 749: 750: union { 751: __I uint32_t WALCLKA; 752: }; 753: 754: __I uint32_t RESERVED28[20]; 755: 756: union { 757: __I uint32_t ISD0LPIBA; 758: }; 759: 760: __I uint32_t RESERVED29[7]; 761: 762: union { 763: __I uint32_t OSD0LPIBA; 764: }; 765: 766: __I uint32_t RESERVED30[7]; 767: 768: union { 769: __I uint32_t OSD1LPIBA; 770: }; 771: 772: __I uint32_t RESERVED31[7]; 773: 774: union { 775: __I uint32_t OSD2LPIBA; 776: }; 777: 778: __I uint32_t RESERVED32[7]; 779: 780: union { 781: __I uint32_t OSD3LPIBA; 782: }; 783: 784: 785: }AG903_HDA_Type; 786: 787: #define AG903_HDA ((volatile AG903_HDA_Type *) AG903_HDA_BASE) 788: 789: 790: #define AG903_HDA_GCAP_OK64_POS 0 791: #define AG903_HDA_GCAP_OK64_MSK (0x1U << AG903_HDA_GCAP_OK64_POS) 792: #define AG903_HDA_GCAP_NSDO_POS 1 793: #define AG903_HDA_GCAP_NSDO_MSK (0x3U << AG903_HDA_GCAP_NSDO_POS) 794: #define AG903_HDA_GCAP_BSS_POS 3 795: #define AG903_HDA_GCAP_BSS_MSK (0x1fU << AG903_HDA_GCAP_BSS_POS) 796: #define AG903_HDA_GCAP_ISS_POS 8 797: #define AG903_HDA_GCAP_ISS_MSK (0xfU << AG903_HDA_GCAP_ISS_POS) 798: #define AG903_HDA_GCAP_OSS_POS 12 799: #define AG903_HDA_GCAP_OSS_MSK (0xfU << AG903_HDA_GCAP_OSS_POS) 800: 801: #define AG903_HDA_VMIN_VMIN_POS 0 802: #define AG903_HDA_VMIN_VMIN_MSK (0xffU << AG903_HDA_VMIN_VMIN_POS) 803: 804: #define AG903_HDA_VMAJ_VMAJ_POS 0 805: #define AG903_HDA_VMAJ_VMAJ_MSK (0xffU << AG903_HDA_VMAJ_VMAJ_POS) 806: 807: #define AG903_HDA_OUTPAY_OUTPAY_POS 0 808: #define AG903_HDA_OUTPAY_OUTPAY_MSK (0xffffU << AG903_HDA_OUTPAY_OUTPAY_POS) 809: 810: #define AG903_HDA_INPAY_INPAY_POS 0 811: #define AG903_HDA_INPAY_INPAY_MSK (0xffffU << AG903_HDA_INPAY_INPAY_POS) 812: 813: #define AG903_HDA_GCTL_CRST_POS 0 814: #define AG903_HDA_GCTL_CRST_MSK (0x1UL << AG903_HDA_GCTL_CRST_POS) 815: #define AG903_HDA_GCTL_FCNTRL_POS 1 816: #define AG903_HDA_GCTL_FCNTRL_MSK (0x1UL << AG903_HDA_GCTL_FCNTRL_POS) 817: #define AG903_HDA_GCTL_UNSOL_POS 8 818: #define AG903_HDA_GCTL_UNSOL_MSK (0x1UL << AG903_HDA_GCTL_UNSOL_POS) 819: 820: #define AG903_HDA_WAKEEN_SDIWEN_POS 0 821: #define AG903_HDA_WAKEEN_SDIWEN_MSK (0x7fffU << AG903_HDA_WAKEEN_SDIWEN_POS) 822: 823: #define AG903_HDA_WAKESTS_SDIWAKE_POS 0 824: #define AG903_HDA_WAKESTS_SDIWAKE_MSK (0x7fffU << AG903_HDA_WAKESTS_SDIWAKE_POS) 825: 826: #define AG903_HDA_GSTS_FSTS_POS 1 827: #define AG903_HDA_GSTS_FSTS_MSK (0x1U << AG903_HDA_GSTS_FSTS_POS) 828: 829: #define AG903_HDA_OUTSTRMPAY_OUTSTRMPAY_POS 0 830: #define AG903_HDA_OUTSTRMPAY_OUTSTRMPAY_MSK (0xffffU << AG903_HDA_OUTSTRMPAY_OUTSTRMPAY_POS) 831: 832: #define AG903_HDA_INSTRMPAY_INSTRMPAY_POS 0 833: #define AG903_HDA_INSTRMPAY_INSTRMPAY_MSK (0xffffU << AG903_HDA_INSTRMPAY_INSTRMPAY_POS) 834: 835: #define AG903_HDA_INTCTL_SIE_POS 0 836: #define AG903_HDA_INTCTL_SIE_MSK (0x3fffffffUL << AG903_HDA_INTCTL_SIE_POS) 837: #define AG903_HDA_INTCTL_CIE_POS 30 838: #define AG903_HDA_INTCTL_CIE_MSK (0x1UL << AG903_HDA_INTCTL_CIE_POS) 839: #define AG903_HDA_INTCTL_GIE_POS 31 840: #define AG903_HDA_INTCTL_GIE_MSK (0x1UL << AG903_HDA_INTCTL_GIE_POS) 841: 842: #define AG903_HDA_INTSTS_SIS_POS 0 843: #define AG903_HDA_INTSTS_SIS_MSK (0x3fffffffUL << AG903_HDA_INTSTS_SIS_POS) 844: #define AG903_HDA_INTSTS_CIS_POS 30 845: #define AG903_HDA_INTSTS_CIS_MSK (0x1UL << AG903_HDA_INTSTS_CIS_POS) 846: #define AG903_HDA_INTSTS_GIS_POS 31 847: #define AG903_HDA_INTSTS_GIS_MSK (0x1UL << AG903_HDA_INTSTS_GIS_POS) 848: 849: #define AG903_HDA_WALCLK_COUNTER_POS 0 850: #define AG903_HDA_WALCLK_COUNTER_MSK (0xffffffffUL << AG903_HDA_WALCLK_COUNTER_POS) 851: 852: #define AG903_HDA_SSYNC_SSYNC_POS 0 853: #define AG903_HDA_SSYNC_SSYNC_MSK (0x3fffffffUL << AG903_HDA_SSYNC_SSYNC_POS) 854: 855: #define AG903_HDA_CORBLBASE_CORBLBASE_POS 7 856: #define AG903_HDA_CORBLBASE_CORBLBASE_MSK (0x1ffffffUL << AG903_HDA_CORBLBASE_CORBLBASE_POS) 857: 858: #define AG903_HDA_CORBUBASE_CORBUBASE_POS 0 859: #define AG903_HDA_CORBUBASE_CORBUBASE_MSK (0xffffffffUL << AG903_HDA_CORBUBASE_CORBUBASE_POS) 860: 861: #define AG903_HDA_CORBWP_CORBWP_POS 0 862: #define AG903_HDA_CORBWP_CORBWP_MSK (0xffU << AG903_HDA_CORBWP_CORBWP_POS) 863: 864: #define AG903_HDA_CORBRP_CORBRP_POS 0 865: #define AG903_HDA_CORBRP_CORBRP_MSK (0xffU << AG903_HDA_CORBRP_CORBRP_POS) 866: #define AG903_HDA_CORBRP_CORBRPRST_POS 15 867: #define AG903_HDA_CORBRP_CORBRPRST_MSK (0x1U << AG903_HDA_CORBRP_CORBRPRST_POS) 868: 869: #define AG903_HDA_CORBCTL_CMEIE_POS 0 870: #define AG903_HDA_CORBCTL_CMEIE_MSK (0x1U << AG903_HDA_CORBCTL_CMEIE_POS) 871: #define AG903_HDA_CORBCTL_CORBRUN_POS 1 872: #define AG903_HDA_CORBCTL_CORBRUN_MSK (0x1U << AG903_HDA_CORBCTL_CORBRUN_POS) 873: 874: #define AG903_HDA_CORBSTS_CMEI_POS 0 875: #define AG903_HDA_CORBSTS_CMEI_MSK (0x1U << AG903_HDA_CORBSTS_CMEI_POS) 876: 877: #define AG903_HDA_CORBSIZE_CORBSIZE_POS 0 878: #define AG903_HDA_CORBSIZE_CORBSIZE_MSK (0x3U << AG903_HDA_CORBSIZE_CORBSIZE_POS) 879: #define AG903_HDA_CORBSIZE_CORBSZCAP_POS 4 880: #define AG903_HDA_CORBSIZE_CORBSZCAP_MSK (0xfU << AG903_HDA_CORBSIZE_CORBSZCAP_POS) 881: 882: #define AG903_HDA_RIRBLBASE_RIRBLBASE_POS 7 883: #define AG903_HDA_RIRBLBASE_RIRBLBASE_MSK (0x1ffffffUL << AG903_HDA_RIRBLBASE_RIRBLBASE_POS) 884: 885: #define AG903_HDA_RIRBUBASE_RIRBUBASE_POS 0 886: #define AG903_HDA_RIRBUBASE_RIRBUBASE_MSK (0xffffffffUL << AG903_HDA_RIRBUBASE_RIRBUBASE_POS) 887: 888: #define AG903_HDA_RIRBWP_RIRBWP_POS 0 889: #define AG903_HDA_RIRBWP_RIRBWP_MSK (0xffU << AG903_HDA_RIRBWP_RIRBWP_POS) 890: #define AG903_HDA_RIRBWP_RIRBWPRST_POS 15 891: #define AG903_HDA_RIRBWP_RIRBWPRST_MSK (0x1U << AG903_HDA_RIRBWP_RIRBWPRST_POS) 892: 893: #define AG903_HDA_RINTCNT_RINTCNT_POS 0 894: #define AG903_HDA_RINTCNT_RINTCNT_MSK (0xffU << AG903_HDA_RINTCNT_RINTCNT_POS) 895: 896: #define AG903_HDA_RIRBCTL_RINTCTL_POS 0 897: #define AG903_HDA_RIRBCTL_RINTCTL_MSK (0x1U << AG903_HDA_RIRBCTL_RINTCTL_POS) 898: #define AG903_HDA_RIRBCTL_RIRBDMAEN_POS 1 899: #define AG903_HDA_RIRBCTL_RIRBDMAEN_MSK (0x1U << AG903_HDA_RIRBCTL_RIRBDMAEN_POS) 900: #define AG903_HDA_RIRBCTL_RIRBOIC_POS 2 901: #define AG903_HDA_RIRBCTL_RIRBOIC_MSK (0x1U << AG903_HDA_RIRBCTL_RIRBOIC_POS) 902: 903: #define AG903_HDA_RIRBSTS_RINTFL_POS 0 904: #define AG903_HDA_RIRBSTS_RINTFL_MSK (0x1U << AG903_HDA_RIRBSTS_RINTFL_POS) 905: #define AG903_HDA_RIRBSTS_RIRBOIS_POS 2 906: #define AG903_HDA_RIRBSTS_RIRBOIS_MSK (0x1U << AG903_HDA_RIRBSTS_RIRBOIS_POS) 907: 908: #define AG903_HDA_RIRBSIZE_RIRBSIZE_POS 0 909: #define AG903_HDA_RIRBSIZE_RIRBSIZE_MSK (0x3U << AG903_HDA_RIRBSIZE_RIRBSIZE_POS) 910: #define AG903_HDA_RIRBSIZE_RIRBSZCAP_POS 4 911: #define AG903_HDA_RIRBSIZE_RIRBSZCAP_MSK (0xfU << AG903_HDA_RIRBSIZE_RIRBSZCAP_POS) 912: 913: #define AG903_HDA_ICOI_ICW_POS 0 914: #define AG903_HDA_ICOI_ICW_MSK (0xffffffffUL << AG903_HDA_ICOI_ICW_POS) 915: 916: #define AG903_HDA_IRII_IRR_POS 0 917: #define AG903_HDA_IRII_IRR_MSK (0xffffffffUL << AG903_HDA_IRII_IRR_POS) 918: 919: #define AG903_HDA_ICS_ICB_POS 0 920: #define AG903_HDA_ICS_ICB_MSK (0x1U << AG903_HDA_ICS_ICB_POS) 921: #define AG903_HDA_ICS_IRV_POS 1 922: #define AG903_HDA_ICS_IRV_MSK (0x1U << AG903_HDA_ICS_IRV_POS) 923: #define AG903_HDA_ICS_ICV_POS 2 924: #define AG903_HDA_ICS_ICV_MSK (0x1U << AG903_HDA_ICS_ICV_POS) 925: #define AG903_HDA_ICS_IRRUNSOL_POS 3 926: #define AG903_HDA_ICS_IRRUNSOL_MSK (0x1U << AG903_HDA_ICS_IRRUNSOL_POS) 927: #define AG903_HDA_ICS_IRRADD_POS 4 928: #define AG903_HDA_ICS_IRRADD_MSK (0xfU << AG903_HDA_ICS_IRRADD_POS) 929: 930: #define AG903_HDA_DPLBASE_DPBE_POS 0 931: #define AG903_HDA_DPLBASE_DPBE_MSK (0x1UL << AG903_HDA_DPLBASE_DPBE_POS) 932: #define AG903_HDA_DPLBASE_DPLBASE_POS 7 933: #define AG903_HDA_DPLBASE_DPLBASE_MSK (0x1ffffffUL << AG903_HDA_DPLBASE_DPLBASE_POS) 934: 935: #define AG903_HDA_DPUBASE_DPUBASE_POS 0 936: #define AG903_HDA_DPUBASE_DPUBASE_MSK (0xffffffffUL << AG903_HDA_DPUBASE_DPUBASE_POS) 937: 938: #define AG903_HDA_ISD0CTLL_SRST_POS 0 939: #define AG903_HDA_ISD0CTLL_SRST_MSK (0x1U << AG903_HDA_ISD0CTLL_SRST_POS) 940: #define AG903_HDA_ISD0CTLL_RUN_POS 1 941: #define AG903_HDA_ISD0CTLL_RUN_MSK (0x1U << AG903_HDA_ISD0CTLL_RUN_POS) 942: #define AG903_HDA_ISD0CTLL_IOCE_POS 2 943: #define AG903_HDA_ISD0CTLL_IOCE_MSK (0x1U << AG903_HDA_ISD0CTLL_IOCE_POS) 944: #define AG903_HDA_ISD0CTLL_FEIE_POS 3 945: #define AG903_HDA_ISD0CTLL_FEIE_MSK (0x1U << AG903_HDA_ISD0CTLL_FEIE_POS) 946: #define AG903_HDA_ISD0CTLL_DEIE_POS 4 947: #define AG903_HDA_ISD0CTLL_DEIE_MSK (0x1U << AG903_HDA_ISD0CTLL_DEIE_POS) 948: 949: #define AG903_HDA_ISD0CTLU_STRIPE_POS 0 950: #define AG903_HDA_ISD0CTLU_STRIPE_MSK (0x3U << AG903_HDA_ISD0CTLU_STRIPE_POS) 951: #define AG903_HDA_ISD0CTLU_TP_POS 2 952: #define AG903_HDA_ISD0CTLU_TP_MSK (0x1U << AG903_HDA_ISD0CTLU_TP_POS) 953: #define AG903_HDA_ISD0CTLU_DIR_POS 3 954: #define AG903_HDA_ISD0CTLU_DIR_MSK (0x1U << AG903_HDA_ISD0CTLU_DIR_POS) 955: #define AG903_HDA_ISD0CTLU_STRM_POS 4 956: #define AG903_HDA_ISD0CTLU_STRM_MSK (0xfU << AG903_HDA_ISD0CTLU_STRM_POS) 957: 958: #define AG903_HDA_ISD0STS_BCIS_POS 2 959: #define AG903_HDA_ISD0STS_BCIS_MSK (0x1U << AG903_HDA_ISD0STS_BCIS_POS) 960: #define AG903_HDA_ISD0STS_FIFOE_POS 3 961: #define AG903_HDA_ISD0STS_FIFOE_MSK (0x1U << AG903_HDA_ISD0STS_FIFOE_POS) 962: #define AG903_HDA_ISD0STS_DESE_POS 4 963: #define AG903_HDA_ISD0STS_DESE_MSK (0x1U << AG903_HDA_ISD0STS_DESE_POS) 964: #define AG903_HDA_ISD0STS_FIFORDY_POS 5 965: #define AG903_HDA_ISD0STS_FIFORDY_MSK (0x1U << AG903_HDA_ISD0STS_FIFORDY_POS) 966: 967: #define AG903_HDA_ISD0LPIB_LPIB_POS 0 968: #define AG903_HDA_ISD0LPIB_LPIB_MSK (0xffffffffUL << AG903_HDA_ISD0LPIB_LPIB_POS) 969: 970: #define AG903_HDA_ISD0CBL_CBL_POS 0 971: #define AG903_HDA_ISD0CBL_CBL_MSK (0xffffffffUL << AG903_HDA_ISD0CBL_CBL_POS) 972: 973: #define AG903_HDA_ISD0LVI_LVI_POS 0 974: #define AG903_HDA_ISD0LVI_LVI_MSK (0xffU << AG903_HDA_ISD0LVI_LVI_POS) 975: 976: #define AG903_HDA_ISD0FIFOS_FIFOS_POS 0 977: #define AG903_HDA_ISD0FIFOS_FIFOS_MSK (0xffffU << AG903_HDA_ISD0FIFOS_FIFOS_POS) 978: 979: #define AG903_HDA_ISD0FMT_CHAN_POS 0 980: #define AG903_HDA_ISD0FMT_CHAN_MSK (0xfU << AG903_HDA_ISD0FMT_CHAN_POS) 981: #define AG903_HDA_ISD0FMT_BITS_POS 4 982: #define AG903_HDA_ISD0FMT_BITS_MSK (0x7U << AG903_HDA_ISD0FMT_BITS_POS) 983: #define AG903_HDA_ISD0FMT_DIV_POS 8 984: #define AG903_HDA_ISD0FMT_DIV_MSK (0x7U << AG903_HDA_ISD0FMT_DIV_POS) 985: #define AG903_HDA_ISD0FMT_MULT_POS 11 986: #define AG903_HDA_ISD0FMT_MULT_MSK (0x7U << AG903_HDA_ISD0FMT_MULT_POS) 987: #define AG903_HDA_ISD0FMT_BASE_POS 14 988: #define AG903_HDA_ISD0FMT_BASE_MSK (0x1U << AG903_HDA_ISD0FMT_BASE_POS) 989: 990: #define AG903_HDA_ISD0BDPL_BDLLBASE_POS 7 991: #define AG903_HDA_ISD0BDPL_BDLLBASE_MSK (0x1ffffffUL << AG903_HDA_ISD0BDPL_BDLLBASE_POS) 992: 993: #define AG903_HDA_ISD0BDPU_BDLUBASE_POS 0 994: #define AG903_HDA_ISD0BDPU_BDLUBASE_MSK (0xffffffffUL << AG903_HDA_ISD0BDPU_BDLUBASE_POS) 995: 996: #define AG903_HDA_OSD0CTLL_SRST_POS 0 997: #define AG903_HDA_OSD0CTLL_SRST_MSK (0x1U << AG903_HDA_OSD0CTLL_SRST_POS) 998: #define AG903_HDA_OSD0CTLL_RUN_POS 1 999: #define AG903_HDA_OSD0CTLL_RUN_MSK (0x1U << AG903_HDA_OSD0CTLL_RUN_POS) 1000: #define AG903_HDA_OSD0CTLL_IOCE_POS 2 1001: #define AG903_HDA_OSD0CTLL_IOCE_MSK (0x1U << AG903_HDA_OSD0CTLL_IOCE_POS) 1002: #define AG903_HDA_OSD0CTLL_FEIE_POS 3 1003: #define AG903_HDA_OSD0CTLL_FEIE_MSK (0x1U << AG903_HDA_OSD0CTLL_FEIE_POS) 1004: #define AG903_HDA_OSD0CTLL_DEIE_POS 4 1005: #define AG903_HDA_OSD0CTLL_DEIE_MSK (0x1U << AG903_HDA_OSD0CTLL_DEIE_POS) 1006: 1007: #define AG903_HDA_OSD0CTLU_STRIPE_POS 0 1008: #define AG903_HDA_OSD0CTLU_STRIPE_MSK (0x3U << AG903_HDA_OSD0CTLU_STRIPE_POS) 1009: #define AG903_HDA_OSD0CTLU_TP_POS 2 1010: #define AG903_HDA_OSD0CTLU_TP_MSK (0x1U << AG903_HDA_OSD0CTLU_TP_POS) 1011: #define AG903_HDA_OSD0CTLU_DIR_POS 3 1012: #define AG903_HDA_OSD0CTLU_DIR_MSK (0x1U << AG903_HDA_OSD0CTLU_DIR_POS) 1013: #define AG903_HDA_OSD0CTLU_STRM_POS 4 1014: #define AG903_HDA_OSD0CTLU_STRM_MSK (0xfU << AG903_HDA_OSD0CTLU_STRM_POS) 1015: 1016: #define AG903_HDA_OSD0STS_BCIS_POS 2 1017: #define AG903_HDA_OSD0STS_BCIS_MSK (0x1U << AG903_HDA_OSD0STS_BCIS_POS) 1018: #define AG903_HDA_OSD0STS_FIFOE_POS 3 1019: #define AG903_HDA_OSD0STS_FIFOE_MSK (0x1U << AG903_HDA_OSD0STS_FIFOE_POS) 1020: #define AG903_HDA_OSD0STS_DESE_POS 4 1021: #define AG903_HDA_OSD0STS_DESE_MSK (0x1U << AG903_HDA_OSD0STS_DESE_POS) 1022: #define AG903_HDA_OSD0STS_FIFORDY_POS 5 1023: #define AG903_HDA_OSD0STS_FIFORDY_MSK (0x1U << AG903_HDA_OSD0STS_FIFORDY_POS) 1024: 1025: #define AG903_HDA_OSD0LPIB_LPIB_POS 0 1026: #define AG903_HDA_OSD0LPIB_LPIB_MSK (0xffffffffUL << AG903_HDA_OSD0LPIB_LPIB_POS) 1027: 1028: #define AG903_HDA_OSD0CBL_CBL_POS 0 1029: #define AG903_HDA_OSD0CBL_CBL_MSK (0xffffffffUL << AG903_HDA_OSD0CBL_CBL_POS) 1030: 1031: #define AG903_HDA_OSD0LVI_LVI_POS 0 1032: #define AG903_HDA_OSD0LVI_LVI_MSK (0xffU << AG903_HDA_OSD0LVI_LVI_POS) 1033: 1034: #define AG903_HDA_OSD0FIFOS_FIFOS_POS 0 1035: #define AG903_HDA_OSD0FIFOS_FIFOS_MSK (0xffffU << AG903_HDA_OSD0FIFOS_FIFOS_POS) 1036: 1037: #define AG903_HDA_OSD0FMT_CHAN_POS 0 1038: #define AG903_HDA_OSD0FMT_CHAN_MSK (0xfU << AG903_HDA_OSD0FMT_CHAN_POS) 1039: #define AG903_HDA_OSD0FMT_BITS_POS 4 1040: #define AG903_HDA_OSD0FMT_BITS_MSK (0x7U << AG903_HDA_OSD0FMT_BITS_POS) 1041: #define AG903_HDA_OSD0FMT_DIV_POS 8 1042: #define AG903_HDA_OSD0FMT_DIV_MSK (0x7U << AG903_HDA_OSD0FMT_DIV_POS) 1043: #define AG903_HDA_OSD0FMT_MULT_POS 11 1044: #define AG903_HDA_OSD0FMT_MULT_MSK (0x7U << AG903_HDA_OSD0FMT_MULT_POS) 1045: #define AG903_HDA_OSD0FMT_BASE_POS 14 1046: #define AG903_HDA_OSD0FMT_BASE_MSK (0x1U << AG903_HDA_OSD0FMT_BASE_POS) 1047: 1048: #define AG903_HDA_OSD0BDPL_BDLLBASE_POS 7 1049: #define AG903_HDA_OSD0BDPL_BDLLBASE_MSK (0x1ffffffUL << AG903_HDA_OSD0BDPL_BDLLBASE_POS) 1050: 1051: #define AG903_HDA_OSD0BDPU_BDLUBASE_POS 0 1052: #define AG903_HDA_OSD0BDPU_BDLUBASE_MSK (0xffffffffUL << AG903_HDA_OSD0BDPU_BDLUBASE_POS) 1053: 1054: #define AG903_HDA_OSD1CTLL_SRST_POS 0 1055: #define AG903_HDA_OSD1CTLL_SRST_MSK (0x1U << AG903_HDA_OSD1CTLL_SRST_POS) 1056: #define AG903_HDA_OSD1CTLL_RUN_POS 1 1057: #define AG903_HDA_OSD1CTLL_RUN_MSK (0x1U << AG903_HDA_OSD1CTLL_RUN_POS) 1058: #define AG903_HDA_OSD1CTLL_IOCE_POS 2 1059: #define AG903_HDA_OSD1CTLL_IOCE_MSK (0x1U << AG903_HDA_OSD1CTLL_IOCE_POS) 1060: #define AG903_HDA_OSD1CTLL_FEIE_POS 3 1061: #define AG903_HDA_OSD1CTLL_FEIE_MSK (0x1U << AG903_HDA_OSD1CTLL_FEIE_POS) 1062: #define AG903_HDA_OSD1CTLL_DEIE_POS 4 1063: #define AG903_HDA_OSD1CTLL_DEIE_MSK (0x1U << AG903_HDA_OSD1CTLL_DEIE_POS) 1064: 1065: #define AG903_HDA_OSD1CTLU_STRIPE_POS 0 1066: #define AG903_HDA_OSD1CTLU_STRIPE_MSK (0x3U << AG903_HDA_OSD1CTLU_STRIPE_POS) 1067: #define AG903_HDA_OSD1CTLU_TP_POS 2 1068: #define AG903_HDA_OSD1CTLU_TP_MSK (0x1U << AG903_HDA_OSD1CTLU_TP_POS) 1069: #define AG903_HDA_OSD1CTLU_DIR_POS 3 1070: #define AG903_HDA_OSD1CTLU_DIR_MSK (0x1U << AG903_HDA_OSD1CTLU_DIR_POS) 1071: #define AG903_HDA_OSD1CTLU_STRM_POS 4 1072: #define AG903_HDA_OSD1CTLU_STRM_MSK (0xfU << AG903_HDA_OSD1CTLU_STRM_POS) 1073: 1074: #define AG903_HDA_OSD1STS_BCIS_POS 2 1075: #define AG903_HDA_OSD1STS_BCIS_MSK (0x1U << AG903_HDA_OSD1STS_BCIS_POS) 1076: #define AG903_HDA_OSD1STS_FIFOE_POS 3 1077: #define AG903_HDA_OSD1STS_FIFOE_MSK (0x1U << AG903_HDA_OSD1STS_FIFOE_POS) 1078: #define AG903_HDA_OSD1STS_DESE_POS 4 1079: #define AG903_HDA_OSD1STS_DESE_MSK (0x1U << AG903_HDA_OSD1STS_DESE_POS) 1080: #define AG903_HDA_OSD1STS_FIFORDY_POS 5 1081: #define AG903_HDA_OSD1STS_FIFORDY_MSK (0x1U << AG903_HDA_OSD1STS_FIFORDY_POS) 1082: 1083: #define AG903_HDA_OSD1LPIB_LPIB_POS 0 1084: #define AG903_HDA_OSD1LPIB_LPIB_MSK (0xffffffffUL << AG903_HDA_OSD1LPIB_LPIB_POS) 1085: 1086: #define AG903_HDA_OSD1CBL_CBL_POS 0 1087: #define AG903_HDA_OSD1CBL_CBL_MSK (0xffffffffUL << AG903_HDA_OSD1CBL_CBL_POS) 1088: 1089: #define AG903_HDA_OSD1LVI_LVI_POS 0 1090: #define AG903_HDA_OSD1LVI_LVI_MSK (0xffU << AG903_HDA_OSD1LVI_LVI_POS) 1091: 1092: #define AG903_HDA_OSD1FIFOS_FIFOS_POS 0 1093: #define AG903_HDA_OSD1FIFOS_FIFOS_MSK (0xffffU << AG903_HDA_OSD1FIFOS_FIFOS_POS) 1094: 1095: #define AG903_HDA_OSD1FMT_CHAN_POS 0 1096: #define AG903_HDA_OSD1FMT_CHAN_MSK (0xfU << AG903_HDA_OSD1FMT_CHAN_POS) 1097: #define AG903_HDA_OSD1FMT_BITS_POS 4 1098: #define AG903_HDA_OSD1FMT_BITS_MSK (0x7U << AG903_HDA_OSD1FMT_BITS_POS) 1099: #define AG903_HDA_OSD1FMT_DIV_POS 8 1100: #define AG903_HDA_OSD1FMT_DIV_MSK (0x7U << AG903_HDA_OSD1FMT_DIV_POS) 1101: #define AG903_HDA_OSD1FMT_MULT_POS 11 1102: #define AG903_HDA_OSD1FMT_MULT_MSK (0x7U << AG903_HDA_OSD1FMT_MULT_POS) 1103: #define AG903_HDA_OSD1FMT_BASE_POS 14 1104: #define AG903_HDA_OSD1FMT_BASE_MSK (0x1U << AG903_HDA_OSD1FMT_BASE_POS) 1105: 1106: #define AG903_HDA_OSD1BDPL_BDLLBASE_POS 7 1107: #define AG903_HDA_OSD1BDPL_BDLLBASE_MSK (0x1ffffffUL << AG903_HDA_OSD1BDPL_BDLLBASE_POS) 1108: 1109: #define AG903_HDA_OSD1BDPU_BDLUBASE_POS 0 1110: #define AG903_HDA_OSD1BDPU_BDLUBASE_MSK (0xffffffffUL << AG903_HDA_OSD1BDPU_BDLUBASE_POS) 1111: 1112: #define AG903_HDA_OSD2CTLL_SRST_POS 0 1113: #define AG903_HDA_OSD2CTLL_SRST_MSK (0x1U << AG903_HDA_OSD2CTLL_SRST_POS) 1114: #define AG903_HDA_OSD2CTLL_RUN_POS 1 1115: #define AG903_HDA_OSD2CTLL_RUN_MSK (0x1U << AG903_HDA_OSD2CTLL_RUN_POS) 1116: #define AG903_HDA_OSD2CTLL_IOCE_POS 2 1117: #define AG903_HDA_OSD2CTLL_IOCE_MSK (0x1U << AG903_HDA_OSD2CTLL_IOCE_POS) 1118: #define AG903_HDA_OSD2CTLL_FEIE_POS 3 1119: #define AG903_HDA_OSD2CTLL_FEIE_MSK (0x1U << AG903_HDA_OSD2CTLL_FEIE_POS) 1120: #define AG903_HDA_OSD2CTLL_DEIE_POS 4 1121: #define AG903_HDA_OSD2CTLL_DEIE_MSK (0x1U << AG903_HDA_OSD2CTLL_DEIE_POS) 1122: 1123: #define AG903_HDA_OSD2CTLU_STRIPE_POS 0 1124: #define AG903_HDA_OSD2CTLU_STRIPE_MSK (0x3U << AG903_HDA_OSD2CTLU_STRIPE_POS) 1125: #define AG903_HDA_OSD2CTLU_TP_POS 2 1126: #define AG903_HDA_OSD2CTLU_TP_MSK (0x1U << AG903_HDA_OSD2CTLU_TP_POS) 1127: #define AG903_HDA_OSD2CTLU_DIR_POS 3 1128: #define AG903_HDA_OSD2CTLU_DIR_MSK (0x1U << AG903_HDA_OSD2CTLU_DIR_POS) 1129: #define AG903_HDA_OSD2CTLU_STRM_POS 4 1130: #define AG903_HDA_OSD2CTLU_STRM_MSK (0xfU << AG903_HDA_OSD2CTLU_STRM_POS) 1131: 1132: #define AG903_HDA_OSD2STS_BCIS_POS 2 1133: #define AG903_HDA_OSD2STS_BCIS_MSK (0x1U << AG903_HDA_OSD2STS_BCIS_POS) 1134: #define AG903_HDA_OSD2STS_FIFOE_POS 3 1135: #define AG903_HDA_OSD2STS_FIFOE_MSK (0x1U << AG903_HDA_OSD2STS_FIFOE_POS) 1136: #define AG903_HDA_OSD2STS_DESE_POS 4 1137: #define AG903_HDA_OSD2STS_DESE_MSK (0x1U << AG903_HDA_OSD2STS_DESE_POS) 1138: #define AG903_HDA_OSD2STS_FIFORDY_POS 5 1139: #define AG903_HDA_OSD2STS_FIFORDY_MSK (0x1U << AG903_HDA_OSD2STS_FIFORDY_POS) 1140: 1141: #define AG903_HDA_OSD2LPIB_LPIB_POS 0 1142: #define AG903_HDA_OSD2LPIB_LPIB_MSK (0xffffffffUL << AG903_HDA_OSD2LPIB_LPIB_POS) 1143: 1144: #define AG903_HDA_OSD2CBL_CBL_POS 0 1145: #define AG903_HDA_OSD2CBL_CBL_MSK (0xffffffffUL << AG903_HDA_OSD2CBL_CBL_POS) 1146: 1147: #define AG903_HDA_OSD2LVI_LVI_POS 0 1148: #define AG903_HDA_OSD2LVI_LVI_MSK (0xffU << AG903_HDA_OSD2LVI_LVI_POS) 1149: 1150: #define AG903_HDA_OSD2FIFOS_FIFOS_POS 0 1151: #define AG903_HDA_OSD2FIFOS_FIFOS_MSK (0xffffU << AG903_HDA_OSD2FIFOS_FIFOS_POS) 1152: 1153: #define AG903_HDA_OSD2FMT_CHAN_POS 0 1154: #define AG903_HDA_OSD2FMT_CHAN_MSK (0xfU << AG903_HDA_OSD2FMT_CHAN_POS) 1155: #define AG903_HDA_OSD2FMT_BITS_POS 4 1156: #define AG903_HDA_OSD2FMT_BITS_MSK (0x7U << AG903_HDA_OSD2FMT_BITS_POS) 1157: #define AG903_HDA_OSD2FMT_DIV_POS 8 1158: #define AG903_HDA_OSD2FMT_DIV_MSK (0x7U << AG903_HDA_OSD2FMT_DIV_POS) 1159: #define AG903_HDA_OSD2FMT_MULT_POS 11 1160: #define AG903_HDA_OSD2FMT_MULT_MSK (0x7U << AG903_HDA_OSD2FMT_MULT_POS) 1161: #define AG903_HDA_OSD2FMT_BASE_POS 14 1162: #define AG903_HDA_OSD2FMT_BASE_MSK (0x1U << AG903_HDA_OSD2FMT_BASE_POS) 1163: 1164: #define AG903_HDA_OSD2BDPL_BDLLBASE_POS 7 1165: #define AG903_HDA_OSD2BDPL_BDLLBASE_MSK (0x1ffffffUL << AG903_HDA_OSD2BDPL_BDLLBASE_POS) 1166: 1167: #define AG903_HDA_OSD2BDPU_BDLUBASE_POS 0 1168: #define AG903_HDA_OSD2BDPU_BDLUBASE_MSK (0xffffffffUL << AG903_HDA_OSD2BDPU_BDLUBASE_POS) 1169: 1170: #define AG903_HDA_OSD3CTLL_SRST_POS 0 1171: #define AG903_HDA_OSD3CTLL_SRST_MSK (0x1U << AG903_HDA_OSD3CTLL_SRST_POS) 1172: #define AG903_HDA_OSD3CTLL_RUN_POS 1 1173: #define AG903_HDA_OSD3CTLL_RUN_MSK (0x1U << AG903_HDA_OSD3CTLL_RUN_POS) 1174: #define AG903_HDA_OSD3CTLL_IOCE_POS 2 1175: #define AG903_HDA_OSD3CTLL_IOCE_MSK (0x1U << AG903_HDA_OSD3CTLL_IOCE_POS) 1176: #define AG903_HDA_OSD3CTLL_FEIE_POS 3 1177: #define AG903_HDA_OSD3CTLL_FEIE_MSK (0x1U << AG903_HDA_OSD3CTLL_FEIE_POS) 1178: #define AG903_HDA_OSD3CTLL_DEIE_POS 4 1179: #define AG903_HDA_OSD3CTLL_DEIE_MSK (0x1U << AG903_HDA_OSD3CTLL_DEIE_POS) 1180: 1181: #define AG903_HDA_OSD3CTLU_STRIPE_POS 0 1182: #define AG903_HDA_OSD3CTLU_STRIPE_MSK (0x3U << AG903_HDA_OSD3CTLU_STRIPE_POS) 1183: #define AG903_HDA_OSD3CTLU_TP_POS 2 1184: #define AG903_HDA_OSD3CTLU_TP_MSK (0x1U << AG903_HDA_OSD3CTLU_TP_POS) 1185: #define AG903_HDA_OSD3CTLU_DIR_POS 3 1186: #define AG903_HDA_OSD3CTLU_DIR_MSK (0x1U << AG903_HDA_OSD3CTLU_DIR_POS) 1187: #define AG903_HDA_OSD3CTLU_STRM_POS 4 1188: #define AG903_HDA_OSD3CTLU_STRM_MSK (0xfU << AG903_HDA_OSD3CTLU_STRM_POS) 1189: 1190: #define AG903_HDA_OSD3STS_BCIS_POS 2 1191: #define AG903_HDA_OSD3STS_BCIS_MSK (0x1U << AG903_HDA_OSD3STS_BCIS_POS) 1192: #define AG903_HDA_OSD3STS_FIFOE_POS 3 1193: #define AG903_HDA_OSD3STS_FIFOE_MSK (0x1U << AG903_HDA_OSD3STS_FIFOE_POS) 1194: #define AG903_HDA_OSD3STS_DESE_POS 4 1195: #define AG903_HDA_OSD3STS_DESE_MSK (0x1U << AG903_HDA_OSD3STS_DESE_POS) 1196: #define AG903_HDA_OSD3STS_FIFORDY_POS 5 1197: #define AG903_HDA_OSD3STS_FIFORDY_MSK (0x1U << AG903_HDA_OSD3STS_FIFORDY_POS) 1198: 1199: #define AG903_HDA_OSD3LPIB_LPIB_POS 0 1200: #define AG903_HDA_OSD3LPIB_LPIB_MSK (0xffffffffUL << AG903_HDA_OSD3LPIB_LPIB_POS) 1201: 1202: #define AG903_HDA_OSD3CBL_CBL_POS 0 1203: #define AG903_HDA_OSD3CBL_CBL_MSK (0xffffffffUL << AG903_HDA_OSD3CBL_CBL_POS) 1204: 1205: #define AG903_HDA_OSD3LVI_LVI_POS 0 1206: #define AG903_HDA_OSD3LVI_LVI_MSK (0xffU << AG903_HDA_OSD3LVI_LVI_POS) 1207: 1208: #define AG903_HDA_OSD3FIFOS_FIFOS_POS 0 1209: #define AG903_HDA_OSD3FIFOS_FIFOS_MSK (0xffffU << AG903_HDA_OSD3FIFOS_FIFOS_POS) 1210: 1211: #define AG903_HDA_OSD3FMT_CHAN_POS 0 1212: #define AG903_HDA_OSD3FMT_CHAN_MSK (0xfU << AG903_HDA_OSD3FMT_CHAN_POS) 1213: #define AG903_HDA_OSD3FMT_BITS_POS 4 1214: #define AG903_HDA_OSD3FMT_BITS_MSK (0x7U << AG903_HDA_OSD3FMT_BITS_POS) 1215: #define AG903_HDA_OSD3FMT_DIV_POS 8 1216: #define AG903_HDA_OSD3FMT_DIV_MSK (0x7U << AG903_HDA_OSD3FMT_DIV_POS) 1217: #define AG903_HDA_OSD3FMT_MULT_POS 11 1218: #define AG903_HDA_OSD3FMT_MULT_MSK (0x7U << AG903_HDA_OSD3FMT_MULT_POS) 1219: #define AG903_HDA_OSD3FMT_BASE_POS 14 1220: #define AG903_HDA_OSD3FMT_BASE_MSK (0x1U << AG903_HDA_OSD3FMT_BASE_POS) 1221: 1222: #define AG903_HDA_OSD3BDPL_BDLLBASE_POS 7 1223: #define AG903_HDA_OSD3BDPL_BDLLBASE_MSK (0x1ffffffUL << AG903_HDA_OSD3BDPL_BDLLBASE_POS) 1224: 1225: #define AG903_HDA_OSD3BDPU_BDLUBASE_POS 0 1226: #define AG903_HDA_OSD3BDPU_BDLUBASE_MSK (0xffffffffUL << AG903_HDA_OSD3BDPU_BDLUBASE_POS) 1227: 1228: #define AG903_HDA_WALCLKA_COUNTERA_POS 0 1229: #define AG903_HDA_WALCLKA_COUNTERA_MSK (0xffffffffUL << AG903_HDA_WALCLKA_COUNTERA_POS) 1230: 1231: #define AG903_HDA_ISD0LPIBA_LPIBA_POS 0 1232: #define AG903_HDA_ISD0LPIBA_LPIBA_MSK (0xffffffffUL << AG903_HDA_ISD0LPIBA_LPIBA_POS) 1233: 1234: #define AG903_HDA_OSD0LPIBA_LPIBA_POS 0 1235: #define AG903_HDA_OSD0LPIBA_LPIBA_MSK (0xffffffffUL << AG903_HDA_OSD0LPIBA_LPIBA_POS) 1236: 1237: #define AG903_HDA_OSD1LPIBA_LPIBA_POS 0 1238: #define AG903_HDA_OSD1LPIBA_LPIBA_MSK (0xffffffffUL << AG903_HDA_OSD1LPIBA_LPIBA_POS) 1239: 1240: #define AG903_HDA_OSD2LPIBA_LPIBA_POS 0 1241: #define AG903_HDA_OSD2LPIBA_LPIBA_MSK (0xffffffffUL << AG903_HDA_OSD2LPIBA_LPIBA_POS) 1242: 1243: #define AG903_HDA_OSD3LPIBA_LPIBA_POS 0 1244: #define AG903_HDA_OSD3LPIBA_LPIBA_MSK (0xffffffffUL << AG903_HDA_OSD3LPIBA_LPIBA_POS) 1245: 1246: #endif 1247:
名前 
説明 
HDA Base Address 
HDACORBCTL CMEIE-bit mask 
HDACORBCTL CMEIE-bit position 
HDACORBCTL CORBRUN-bit mask 
HDACORBCTL CORBRUN-bit position 
HDACORBLBASE CORBLBASE-bit mask 
HDACORBLBASE CORBLBASE-bit position 
HDACORBRP CORBRP-bit mask 
HDACORBRP CORBRP-bit position 
HDACORBRP CORBRPRST-bit mask 
HDACORBRP CORBRPRST-bit position 
HDACORBSIZE CORBSIZE-bit mask 
HDACORBSIZE CORBSIZE-bit position 
HDACORBSIZE CORBSZCAP-bit mask 
HDACORBSIZE CORBSZCAP-bit position 
HDACORBSTS CMEI-bit mask 
HDACORBSTS CMEI-bit position 
HDACORBUBASE CORBUBASE-bit mask 
HDACORBUBASE CORBUBASE-bit position 
HDACORBWP CORBWP-bit mask 
HDACORBWP CORBWP-bit position 
HDADPLBASE DPBE-bit mask 
HDADPLBASE DPBE-bit position 
HDADPLBASE DPLBASE-bit mask 
HDADPLBASE DPLBASE-bit position 
HDADPUBASE DPUBASE-bit mask 
HDADPUBASE DPUBASE-bit position 
HDAGCAP BSS-bit mask 
HDAGCAP BSS-bit position 
HDAGCAP ISS-bit mask 
HDAGCAP ISS-bit position 
HDAGCAP NSDO-bit mask 
HDAGCAP NSDO-bit position 
HDAGCAP OK64-bit mask 
HDAGCAP OK64-bit position 
HDAGCAP OSS-bit mask 
HDAGCAP OSS-bit position 
HDAGCTL CRST-bit mask 
HDAGCTL CRST-bit position 
HDAGCTL FCNTRL-bit mask 
HDAGCTL FCNTRL-bit position 
HDAGCTL UNSOL-bit mask 
HDAGCTL UNSOL-bit position 
HDAGSTS FSTS-bit mask 
HDAGSTS FSTS-bit position 
HDAICOI ICW-bit mask 
HDAICOI ICW-bit position 
HDAICS ICB-bit mask 
HDAICS ICB-bit position 
HDAICS ICV-bit mask 
HDAICS ICV-bit position 
HDAICS IRRADD-bit mask 
HDAICS IRRADD-bit position 
HDAICS IRRUNSOL-bit mask 
HDAICS IRRUNSOL-bit position 
HDAICS IRV-bit mask 
HDAICS IRV-bit position 
HDAINPAY INPAY-bit mask 
HDAINPAY INPAY-bit position 
HDAINSTRMPAY INSTRMPAY-bit mask 
HDAINSTRMPAY INSTRMPAY-bit position 
HDAINTCTL CIE-bit mask 
HDAINTCTL CIE-bit position 
HDAINTCTL GIE-bit mask 
HDAINTCTL GIE-bit position 
HDAINTCTL SIE-bit mask 
HDAINTCTL SIE-bit position 
HDAINTSTS CIS-bit mask 
HDAINTSTS CIS-bit position 
HDAINTSTS GIS-bit mask 
HDAINTSTS GIS-bit position 
HDAINTSTS SIS-bit mask 
HDAINTSTS SIS-bit position 
HDAIRII IRR-bit mask 
HDAIRII IRR-bit position 
HDAISD0BDPL BDLLBASE-bit mask 
HDAISD0BDPL BDLLBASE-bit position 
HDAISD0BDPU BDLUBASE-bit mask 
HDAISD0BDPU BDLUBASE-bit position 
HDAISD0CBL CBL-bit mask 
HDAISD0CBL CBL-bit position 
HDAISD0CTLL DEIE-bit mask 
HDAISD0CTLL DEIE-bit position 
HDAISD0CTLL FEIE-bit mask 
HDAISD0CTLL FEIE-bit position 
HDAISD0CTLL IOCE-bit mask 
HDAISD0CTLL IOCE-bit position 
HDAISD0CTLL RUN-bit mask 
HDAISD0CTLL RUN-bit position 
HDAISD0CTLL SRST-bit mask 
HDAISD0CTLL SRST-bit position 
HDAISD0CTLU DIR-bit mask 
HDAISD0CTLU DIR-bit position 
HDAISD0CTLU STRIPE-bit mask 
HDAISD0CTLU STRIPE-bit position 
HDAISD0CTLU STRM-bit mask 
HDAISD0CTLU STRM-bit position 
HDAISD0CTLU TP-bit mask 
HDAISD0CTLU TP-bit position 
HDAISD0FIFOS FIFOS-bit mask 
HDAISD0FIFOS FIFOS-bit position 
HDAISD0FMT BASE-bit mask 
HDAISD0FMT BASE-bit position 
HDAISD0FMT BITS-bit mask 
HDAISD0FMT BITS-bit position 
HDAISD0FMT CHAN-bit mask 
HDAISD0FMT CHAN-bit position 
HDAISD0FMT DIV-bit mask 
HDAISD0FMT DIV-bit position 
HDAISD0FMT MULT-bit mask 
HDAISD0FMT MULT-bit position 
HDAISD0LPIB LPIB-bit mask 
HDAISD0LPIB LPIB-bit position 
HDAISD0LPIBA LPIBA-bit mask 
HDAISD0LPIBA LPIBA-bit position 
HDAISD0LVI LVI-bit mask 
HDAISD0LVI LVI-bit position 
HDAISD0STS BCIS-bit mask 
HDAISD0STS BCIS-bit position 
HDAISD0STS DESE-bit mask 
HDAISD0STS DESE-bit position 
HDAISD0STS FIFOE-bit mask 
HDAISD0STS FIFOE-bit position 
HDAISD0STS FIFORDY-bit mask 
HDAISD0STS FIFORDY-bit position 
HDAOSD0BDPL BDLLBASE-bit mask 
HDAOSD0BDPL BDLLBASE-bit position 
HDAOSD0BDPU BDLUBASE-bit mask 
HDAOSD0BDPU BDLUBASE-bit position 
HDAOSD0CBL CBL-bit mask 
HDAOSD0CBL CBL-bit position 
HDAOSD0CTLL DEIE-bit mask 
HDAOSD0CTLL DEIE-bit position 
HDAOSD0CTLL FEIE-bit mask 
HDAOSD0CTLL FEIE-bit position 
HDAOSD0CTLL IOCE-bit mask 
HDAOSD0CTLL IOCE-bit position 
HDAOSD0CTLL RUN-bit mask 
HDAOSD0CTLL RUN-bit position 
HDAOSD0CTLL SRST-bit mask 
HDAOSD0CTLL SRST-bit position 
HDAOSD0CTLU DIR-bit mask 
HDAOSD0CTLU DIR-bit position 
HDAOSD0CTLU STRIPE-bit mask 
HDAOSD0CTLU STRIPE-bit position 
HDAOSD0CTLU STRM-bit mask 
HDAOSD0CTLU STRM-bit position 
HDAOSD0CTLU TP-bit mask 
HDAOSD0CTLU TP-bit position 
HDAOSD0FIFOS FIFOS-bit mask 
HDAOSD0FIFOS FIFOS-bit position 
HDAOSD0FMT BASE-bit mask 
HDAOSD0FMT BASE-bit position 
HDAOSD0FMT BITS-bit mask 
HDAOSD0FMT BITS-bit position 
HDAOSD0FMT CHAN-bit mask 
HDAOSD0FMT CHAN-bit position 
HDAOSD0FMT DIV-bit mask 
HDAOSD0FMT DIV-bit position 
HDAOSD0FMT MULT-bit mask 
HDAOSD0FMT MULT-bit position 
HDAOSD0LPIB LPIB-bit mask 
HDAOSD0LPIB LPIB-bit position 
HDAOSD0LPIBA LPIBA-bit mask 
HDAOSD0LPIBA LPIBA-bit position 
HDAOSD0LVI LVI-bit mask 
HDAOSD0LVI LVI-bit position 
HDAOSD0STS BCIS-bit mask 
HDAOSD0STS BCIS-bit position 
HDAOSD0STS DESE-bit mask 
HDAOSD0STS DESE-bit position 
HDAOSD0STS FIFOE-bit mask 
HDAOSD0STS FIFOE-bit position 
HDAOSD0STS FIFORDY-bit mask 
HDAOSD0STS FIFORDY-bit position 
HDAOSD1BDPL BDLLBASE-bit mask 
HDAOSD1BDPL BDLLBASE-bit position 
HDAOSD1BDPU BDLUBASE-bit mask 
HDAOSD1BDPU BDLUBASE-bit position 
HDAOSD1CBL CBL-bit mask 
HDAOSD1CBL CBL-bit position 
HDAOSD1CTLL DEIE-bit mask 
HDAOSD1CTLL DEIE-bit position 
HDAOSD1CTLL FEIE-bit mask 
HDAOSD1CTLL FEIE-bit position 
HDAOSD1CTLL IOCE-bit mask 
HDAOSD1CTLL IOCE-bit position 
HDAOSD1CTLL RUN-bit mask 
HDAOSD1CTLL RUN-bit position 
HDAOSD1CTLL SRST-bit mask 
HDAOSD1CTLL SRST-bit position 
HDAOSD1CTLU DIR-bit mask 
HDAOSD1CTLU DIR-bit position 
HDAOSD1CTLU STRIPE-bit mask 
HDAOSD1CTLU STRIPE-bit position 
HDAOSD1CTLU STRM-bit mask 
HDAOSD1CTLU STRM-bit position 
HDAOSD1CTLU TP-bit mask 
HDAOSD1CTLU TP-bit position 
HDAOSD1FIFOS FIFOS-bit mask 
HDAOSD1FIFOS FIFOS-bit position 
HDAOSD1FMT BASE-bit mask 
HDAOSD1FMT BASE-bit position 
HDAOSD1FMT BITS-bit mask 
HDAOSD1FMT BITS-bit position 
HDAOSD1FMT CHAN-bit mask 
HDAOSD1FMT CHAN-bit position 
HDAOSD1FMT DIV-bit mask 
HDAOSD1FMT DIV-bit position 
HDAOSD1FMT MULT-bit mask 
HDAOSD1FMT MULT-bit position 
HDAOSD1LPIB LPIB-bit mask 
HDAOSD1LPIB LPIB-bit position 
HDAOSD1LPIBA LPIBA-bit mask 
HDAOSD1LPIBA LPIBA-bit position 
HDAOSD1LVI LVI-bit mask 
HDAOSD1LVI LVI-bit position 
HDAOSD1STS BCIS-bit mask 
HDAOSD1STS BCIS-bit position 
HDAOSD1STS DESE-bit mask 
HDAOSD1STS DESE-bit position 
HDAOSD1STS FIFOE-bit mask 
HDAOSD1STS FIFOE-bit position 
HDAOSD1STS FIFORDY-bit mask 
HDAOSD1STS FIFORDY-bit position 
HDAOSD2BDPL BDLLBASE-bit mask 
HDAOSD2BDPL BDLLBASE-bit position 
HDAOSD2BDPU BDLUBASE-bit mask 
HDAOSD2BDPU BDLUBASE-bit position 
HDAOSD2CBL CBL-bit mask 
HDAOSD2CBL CBL-bit position 
HDAOSD2CTLL DEIE-bit mask 
HDAOSD2CTLL DEIE-bit position 
HDAOSD2CTLL FEIE-bit mask 
HDAOSD2CTLL FEIE-bit position 
HDAOSD2CTLL IOCE-bit mask 
HDAOSD2CTLL IOCE-bit position 
HDAOSD2CTLL RUN-bit mask 
HDAOSD2CTLL RUN-bit position 
HDAOSD2CTLL SRST-bit mask 
HDAOSD2CTLL SRST-bit position 
HDAOSD2CTLU DIR-bit mask 
HDAOSD2CTLU DIR-bit position 
HDAOSD2CTLU STRIPE-bit mask 
HDAOSD2CTLU STRIPE-bit position 
HDAOSD2CTLU STRM-bit mask 
HDAOSD2CTLU STRM-bit position 
HDAOSD2CTLU TP-bit mask 
HDAOSD2CTLU TP-bit position 
HDAOSD2FIFOS FIFOS-bit mask 
HDAOSD2FIFOS FIFOS-bit position 
HDAOSD2FMT BASE-bit mask 
HDAOSD2FMT BASE-bit position 
HDAOSD2FMT BITS-bit mask 
HDAOSD2FMT BITS-bit position 
HDAOSD2FMT CHAN-bit mask 
HDAOSD2FMT CHAN-bit position 
HDAOSD2FMT DIV-bit mask 
HDAOSD2FMT DIV-bit position 
HDAOSD2FMT MULT-bit mask 
HDAOSD2FMT MULT-bit position 
HDAOSD2LPIB LPIB-bit mask 
HDAOSD2LPIB LPIB-bit position 
HDAOSD2LPIBA LPIBA-bit mask 
HDAOSD2LPIBA LPIBA-bit position 
HDAOSD2LVI LVI-bit mask 
HDAOSD2LVI LVI-bit position 
HDAOSD2STS BCIS-bit mask 
HDAOSD2STS BCIS-bit position 
HDAOSD2STS DESE-bit mask 
HDAOSD2STS DESE-bit position 
HDAOSD2STS FIFOE-bit mask 
HDAOSD2STS FIFOE-bit position 
HDAOSD2STS FIFORDY-bit mask 
HDAOSD2STS FIFORDY-bit position 
HDAOSD3BDPL BDLLBASE-bit mask 
HDAOSD3BDPL BDLLBASE-bit position 
HDAOSD3BDPU BDLUBASE-bit mask 
HDAOSD3BDPU BDLUBASE-bit position 
HDAOSD3CBL CBL-bit mask 
HDAOSD3CBL CBL-bit position 
HDAOSD3CTLL DEIE-bit mask 
HDAOSD3CTLL DEIE-bit position 
HDAOSD3CTLL FEIE-bit mask 
HDAOSD3CTLL FEIE-bit position 
HDAOSD3CTLL IOCE-bit mask 
HDAOSD3CTLL IOCE-bit position 
HDAOSD3CTLL RUN-bit mask 
HDAOSD3CTLL RUN-bit position 
HDAOSD3CTLL SRST-bit mask 
HDAOSD3CTLL SRST-bit position 
HDAOSD3CTLU DIR-bit mask 
HDAOSD3CTLU DIR-bit position 
HDAOSD3CTLU STRIPE-bit mask 
HDAOSD3CTLU STRIPE-bit position 
HDAOSD3CTLU STRM-bit mask 
HDAOSD3CTLU STRM-bit position 
HDAOSD3CTLU TP-bit mask 
HDAOSD3CTLU TP-bit position 
HDAOSD3FIFOS FIFOS-bit mask 
HDAOSD3FIFOS FIFOS-bit position 
HDAOSD3FMT BASE-bit mask 
HDAOSD3FMT BASE-bit position 
HDAOSD3FMT BITS-bit mask 
HDAOSD3FMT BITS-bit position 
HDAOSD3FMT CHAN-bit mask 
HDAOSD3FMT CHAN-bit position 
HDAOSD3FMT DIV-bit mask 
HDAOSD3FMT DIV-bit position 
HDAOSD3FMT MULT-bit mask 
HDAOSD3FMT MULT-bit position 
HDAOSD3LPIB LPIB-bit mask 
HDAOSD3LPIB LPIB-bit position 
HDAOSD3LPIBA LPIBA-bit mask 
HDAOSD3LPIBA LPIBA-bit position 
HDAOSD3LVI LVI-bit mask 
HDAOSD3LVI LVI-bit position 
HDAOSD3STS BCIS-bit mask 
HDAOSD3STS BCIS-bit position 
HDAOSD3STS DESE-bit mask 
HDAOSD3STS DESE-bit position 
HDAOSD3STS FIFOE-bit mask 
HDAOSD3STS FIFOE-bit position 
HDAOSD3STS FIFORDY-bit mask 
HDAOSD3STS FIFORDY-bit position 
HDAOUTPAY OUTPAY-bit mask 
HDAOUTPAY OUTPAY-bit position 
HDAOUTSTRMPAY OUTSTRMPAY-bit mask 
HDAOUTSTRMPAY OUTSTRMPAY-bit position 
HDARINTCNT RINTCNT-bit mask 
HDARINTCNT RINTCNT-bit position 
HDARIRBCTL RINTCTL-bit mask 
HDARIRBCTL RINTCTL-bit position 
HDARIRBCTL RIRBDMAEN-bit mask 
HDARIRBCTL RIRBDMAEN-bit position 
HDARIRBCTL RIRBOIC-bit mask 
HDARIRBCTL RIRBOIC-bit position 
HDARIRBLBASE RIRBLBASE-bit mask 
HDARIRBLBASE RIRBLBASE-bit position 
HDARIRBSIZE RIRBSIZE-bit mask 
HDARIRBSIZE RIRBSIZE-bit position 
HDARIRBSIZE RIRBSZCAP-bit mask 
HDARIRBSIZE RIRBSZCAP-bit position 
HDARIRBSTS RINTFL-bit mask 
HDARIRBSTS RINTFL-bit position 
HDARIRBSTS RIRBOIS-bit mask 
HDARIRBSTS RIRBOIS-bit position 
HDARIRBUBASE RIRBUBASE-bit mask 
HDARIRBUBASE RIRBUBASE-bit position 
HDARIRBWP RIRBWP-bit mask 
HDARIRBWP RIRBWP-bit position 
HDARIRBWP RIRBWPRST-bit mask 
HDARIRBWP RIRBWPRST-bit position 
HDASSYNC SSYNC-bit mask 
HDASSYNC SSYNC-bit position 
HDAVMAJ VMAJ-bit mask 
HDAVMAJ VMAJ-bit position 
HDAVMIN VMIN-bit mask 
HDAVMIN VMIN-bit position 
HDAWAKEEN SDIWEN-bit mask 
HDAWAKEEN SDIWEN-bit position 
HDAWAKESTS SDIWAKE-bit mask 
HDAWAKESTS SDIWAKE-bit position 
HDAWALCLK COUNTER-bit mask 
HDAWALCLK COUNTER-bit position 
HDAWALCLKA COUNTERA-bit mask 
HDAWALCLKA COUNTERA-bit position 
名前 
説明 
HDA Type 
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