AG903ライブラリリファレンス
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1: 8: 9: 13: 14: #ifndef _AG903_ETH_REGMAP_H_ 15: #define _AG903_ETH_REGMAP_H_ 16: 17: 18: #include "AG903_regmap.h" 19: 20: #ifndef __I 21: 22: #define __I volatile const 23: #endif 24: #ifndef __O 25: 26: #define __O volatile 27: #endif 28: #ifndef __IO 29: 30: #define __IO volatile 31: #endif 32: 33: 34: typedef struct { 35: 36: union { 37: __I uint32_t ISR; 38: 39: struct { 40: __I uint32_t RPKT_FINISH : 1; 41: __I uint32_t NORXBUF : 1; 42: __I uint32_t XPKT_FINISH : 1; 43: __I uint32_t NOTXBUF : 1; 44: __I uint32_t XPKT_OK : 1; 45: __I uint32_t XPKT_LOST : 1; 46: __I uint32_t RPKT_SAV : 1; 47: __I uint32_t RPKT_LOST : 1; 48: __I uint32_t AHB_ERR : 1; 49: __I uint32_t PHYSTS_CHG : 1; 50: __I uint32_t TX_LPI_EXIT : 1; 51: __I uint32_t TX_LPI_IN : 1; 52: __I uint32_t RX_LPI_EXIT : 1; 53: __I uint32_t RX_LPI_IN : 1; 54: } ISR_bits; 55: }; 56: 57: union { 58: __IO uint32_t IME; 59: 60: struct { 61: __IO uint32_t RPKT_FINISH_EN : 1; 62: __IO uint32_t NORXBUF_EN : 1; 63: __IO uint32_t XPKT_FINISH_EN : 1; 64: __IO uint32_t NOTXBUF_EN : 1; 65: __IO uint32_t XPKT_OK_EN : 1; 66: __IO uint32_t XPKT_LOST_EN : 1; 67: __IO uint32_t RPKT_SAV_EN : 1; 68: __IO uint32_t RPKT_LOST_EN : 1; 69: __IO uint32_t AHB_ERR_EN : 1; 70: __IO uint32_t PHYSTS_CHG_EN : 1; 71: __IO uint32_t TX_LPI_EXIT_EN : 1; 72: __IO uint32_t TX_LPI_IN_EN : 1; 73: __IO uint32_t RX_LPI_EXIT_EN : 1; 74: __IO uint32_t RX_LPI_IN_EN : 1; 75: } IME_bits; 76: }; 77: 78: union { 79: __IO uint32_t MAC_MADR; 80: 81: struct { 82: __IO uint32_t MAC_MADR : 16; 83: } MAC_MADR_bits; 84: }; 85: 86: union { 87: __IO uint32_t MAC_LADR; 88: }; 89: 90: union { 91: __IO uint32_t MAHT0; 92: }; 93: 94: union { 95: __IO uint32_t MAHT1; 96: }; 97: 98: union { 99: __O uint32_t TXPD; 100: }; 101: 102: union { 103: __O uint32_t RXPD; 104: }; 105: 106: union { 107: __IO uint32_t TXR_BADR; 108: }; 109: 110: union { 111: __IO uint32_t RXR_BADR; 112: }; 113: 114: union { 115: __IO uint32_t ITC; 116: 117: struct { 118: __IO uint32_t RXINT_CNT : 4; 119: __IO uint32_t RXINT_THR : 3; 120: __IO uint32_t RXINT_TIME_SEL : 1; 121: __IO uint32_t TXINT_CNT : 4; 122: __IO uint32_t TXINT_THR : 3; 123: __IO uint32_t TXINT_TIME_SEL : 1; 124: } ITC_bits; 125: }; 126: 127: union { 128: __IO uint32_t APTC; 129: 130: struct { 131: __IO uint32_t RXPOLL_CNT : 4; 132: __IO uint32_t RXPOLL_TIME_SEL : 1; 133: uint32_t : 3; 134: __IO uint32_t TXPOLL_CNT : 4; 135: __IO uint32_t TXPOLL_TIME_SEL : 1; 136: } APTC_bits; 137: }; 138: 139: union { 140: __IO uint32_t DBLAC; 141: 142: struct { 143: uint32_t : 3; 144: __IO uint32_t RXFIFO_LTHR : 3; 145: __IO uint32_t RXFIFO_HTHR : 3; 146: __IO uint32_t RX_THR_EN : 1; 147: uint32_t : 4; 148: __IO uint32_t INCR_SEL : 2; 149: } DBLAC_bits; 150: }; 151: 152: union { 153: __I uint32_t REVR; 154: 155: struct { 156: __I uint32_t REV_B3 : 8; 157: __I uint32_t REV_B2 : 8; 158: __I uint32_t REV_B1 : 8; 159: } REVR_bits; 160: }; 161: 162: __I uint32_t RESERVED1[19]; 163: 164: union { 165: __IO uint32_t LPICR; 166: 167: struct { 168: __IO uint32_t WAKE_CNT : 16; 169: __IO uint32_t IDLE_CNT : 8; 170: __IO uint32_t TX_LPI_EN : 1; 171: __IO uint32_t RX_LPI_EN : 1; 172: } LPICR_bits; 173: }; 174: 175: union { 176: __IO uint32_t MACCR; 177: 178: struct { 179: __IO uint32_t XDMA_EN : 1; 180: __IO uint32_t RDMA_EN : 1; 181: __IO uint32_t SW_RST : 1; 182: __IO uint32_t LOOP_EN : 1; 183: __IO uint32_t CRC_DIS : 1; 184: __IO uint32_t XMT_EN : 1; 185: __IO uint32_t ENRX_IN_HALFTX : 1; 186: uint32_t : 1; 187: __IO uint32_t RCV_EN : 1; 188: __IO uint32_t HT_MULTI_EN : 1; 189: __IO uint32_t RX_RUNT : 1; 190: __IO uint32_t RX_FTL : 1; 191: __IO uint32_t RCV_ALL : 1; 192: uint32_t : 1; 193: __IO uint32_t CRC_APD : 1; 194: __IO uint32_t FULLDUP : 1; 195: __IO uint32_t RX_MULTIPKT : 1; 196: __IO uint32_t RX_BROADPKT : 1; 197: __IO uint32_t SPEED_100 : 1; 198: __IO uint32_t ZEROCOPY_DIS : 1; 199: } MACCR_bits; 200: }; 201: 202: union { 203: __I uint32_t MACSR; 204: 205: struct { 206: __I uint32_t MULTICAST : 1; 207: __I uint32_t BROADCAST : 1; 208: __I uint32_t COL : 1; 209: __I uint32_t RPKT_SAVE : 1; 210: __I uint32_t RPKT_LOST : 1; 211: __I uint32_t CRC_ERR : 1; 212: __I uint32_t FTL : 1; 213: __I uint32_t RUNT : 1; 214: __I uint32_t XPKT_OK : 1; 215: __I uint32_t XPKT_LOST : 1; 216: __I uint32_t LATE_COL : 1; 217: __I uint32_t COL_EXCEED : 1; 218: } MACSR_bits; 219: }; 220: 221: union { 222: __IO uint32_t PHYCR; 223: 224: struct { 225: __I uint32_t MIIRDATA : 16; 226: __IO uint32_t PHYAD : 5; 227: __IO uint32_t REGAD : 5; 228: __IO uint32_t MIIRD : 1; 229: __IO uint32_t MIIWR : 1; 230: } PHYCR_bits; 231: }; 232: 233: union { 234: __IO uint32_t PHYWDATA; 235: 236: struct { 237: __IO uint32_t MIIWDATA : 16; 238: __IO uint32_t MDC_CYCTHR : 8; 239: } PHYWDATA_bits; 240: }; 241: 242: union { 243: __IO uint32_t FCR; 244: 245: struct { 246: __IO uint32_t FC_EN : 1; 247: __IO uint32_t TX_PAUSE : 1; 248: __IO uint32_t FCTHR_EN : 1; 249: __I uint32_t TXPAUSED : 1; 250: __I uint32_t RX_PAUSE : 1; 251: uint32_t : 3; 252: __IO uint32_t FC_LOW : 4; 253: __IO uint32_t FC_HIGH : 4; 254: __IO uint32_t PAUSE_TIME : 16; 255: } FCR_bits; 256: }; 257: 258: union { 259: __IO uint32_t BPR; 260: 261: struct { 262: __IO uint32_t BK_EN : 1; 263: __IO uint32_t BK_MODE : 1; 264: uint32_t : 2; 265: __IO uint32_t BKJAM_LEN : 4; 266: __IO uint32_t BK_LOW : 4; 267: } BPR_bits; 268: }; 269: 270: union { 271: __IO uint32_t WOLCR; 272: 273: struct { 274: __IO uint32_t LINKCHG0_EN : 1; 275: __IO uint32_t LINKCHG1_EN : 1; 276: __IO uint32_t MAGICPKT_EN : 1; 277: __IO uint32_t WAKEUP1_EN : 1; 278: __IO uint32_t WAKEUP2_EN : 1; 279: __IO uint32_t WAKEUP3_EN : 1; 280: __IO uint32_t WAKEUP4_EN : 1; 281: uint32_t : 7; 282: __IO uint32_t POWER_STATE : 2; 283: __IO uint32_t WAKEUP_SEL : 2; 284: __IO uint32_t SW_PDNPHY : 1; 285: uint32_t : 5; 286: __IO uint32_t WOL_TYPE : 2; 287: } WOLCR_bits; 288: }; 289: 290: union { 291: __IO uint32_t WOLSR; 292: 293: struct { 294: __IO uint32_t LINKCHG0_STS : 1; 295: __IO uint32_t LINKCHG1_STS : 1; 296: __IO uint32_t MAGICPKT_STS : 1; 297: __IO uint32_t WAKEUP1_STS : 1; 298: __IO uint32_t WAKEUP2_STS : 1; 299: __IO uint32_t WAKEUP3_STS : 1; 300: __IO uint32_t WAKEUP4_STS : 1; 301: } WOLSR_bits; 302: }; 303: 304: union { 305: __IO uint32_t WFCRC; 306: }; 307: 308: __I uint32_t RESERVED2[1]; 309: 310: union { 311: __IO uint32_t WFBM1; 312: }; 313: 314: union { 315: __IO uint32_t WFBM2; 316: }; 317: 318: union { 319: __IO uint32_t WFBM3; 320: }; 321: 322: union { 323: __IO uint32_t WFBM4; 324: }; 325: 326: __I uint32_t RESERVED3[1]; 327: 328: union { 329: __IO uint32_t TS; 330: 331: struct { 332: __IO uint32_t Test_seed : 14; 333: } TS_bits; 334: }; 335: 336: union { 337: __I uint32_t DMAFIFOS; 338: 339: struct { 340: __I uint32_t RXDMA1_SM : 4; 341: __I uint32_t RXDMA2_SM : 3; 342: uint32_t : 1; 343: __I uint32_t TXDMA1_SM : 4; 344: __I uint32_t TXDMA2_SM : 3; 345: uint32_t : 11; 346: __I uint32_t RXFIFO_EMPTY : 1; 347: __I uint32_t TXFIFO_EMPTY : 1; 348: __I uint32_t DARB_RXGNT : 1; 349: __I uint32_t DARB_TXGNT : 1; 350: __I uint32_t RXD_REQ : 1; 351: __I uint32_t TXD_REQ : 1; 352: } DMAFIFOS_bits; 353: }; 354: 355: union { 356: __IO uint32_t TM; 357: 358: struct { 359: uint32_t : 5; 360: __IO uint32_t TEST_EXCEL : 5; 361: __IO uint32_t TEST_TIME : 10; 362: __IO uint32_t TEST_MODE : 1; 363: __IO uint32_t SEED_SEL : 1; 364: __IO uint32_t TEST_SEED_SEL : 1; 365: uint32_t : 1; 366: __IO uint32_t ITIMER_TEST : 1; 367: __IO uint32_t PTIMER_TEST : 1; 368: __IO uint32_t SINGLE_PKT : 1; 369: __IO uint32_t DMA_SWAP : 1; 370: __IO uint32_t PKT_SWAP_B : 1; 371: __IO uint32_t BIG_FORM : 1; 372: } TM_bits; 373: }; 374: 375: __I uint32_t RESERVED4[1]; 376: 377: union { 378: __I uint32_t COLCR; 379: 380: struct { 381: __I uint32_t TX_SCOL : 16; 382: __I uint32_t TX_MCOL : 16; 383: } COLCR_bits; 384: }; 385: 386: union { 387: __I uint32_t REFAEPCR; 388: 389: struct { 390: __I uint32_t AEP : 16; 391: __I uint32_t RPF : 16; 392: } REFAEPCR_bits; 393: }; 394: 395: union { 396: __I uint32_t XMPGCR; 397: 398: struct { 399: __I uint32_t PG : 16; 400: __I uint32_t XM : 16; 401: } XMPGCR_bits; 402: }; 403: 404: union { 405: __I uint32_t RUNTLCCCR; 406: 407: struct { 408: __I uint32_t TLCC : 16; 409: __I uint32_t RUNT_CNT : 16; 410: } RUNTLCCCR_bits; 411: }; 412: 413: union { 414: __I uint32_t CRCERFTLCR; 415: 416: struct { 417: __I uint32_t FTL_CNT : 16; 418: __I uint32_t CRCER_CNT : 16; 419: } CRCERFTLCR_bits; 420: }; 421: 422: union { 423: __I uint32_t RLCRCCCR; 424: 425: struct { 426: __I uint32_t RCC : 16; 427: __I uint32_t RLC : 16; 428: } RLCRCCCR_bits; 429: }; 430: 431: union { 432: __I uint32_t BROCCR; 433: }; 434: 435: union { 436: __I uint32_t MULCACR; 437: }; 438: 439: union { 440: __I uint32_t RPCR; 441: }; 442: 443: union { 444: __I uint32_t XPCR; 445: }; 446: 447: 448: }AG903_ETH_Type; 449: 450: #define AG903_ETH ((volatile AG903_ETH_Type *) AG903_ETH_BASE) 451: 452: 453: #define AG903_ETH_ISR_RPKT_FINISH_POS 0 454: #define AG903_ETH_ISR_RPKT_FINISH_MSK (0x1UL << AG903_ETH_ISR_RPKT_FINISH_POS) 455: #define AG903_ETH_ISR_NORXBUF_POS 1 456: #define AG903_ETH_ISR_NORXBUF_MSK (0x1UL << AG903_ETH_ISR_NORXBUF_POS) 457: #define AG903_ETH_ISR_XPKT_FINISH_POS 2 458: #define AG903_ETH_ISR_XPKT_FINISH_MSK (0x1UL << AG903_ETH_ISR_XPKT_FINISH_POS) 459: #define AG903_ETH_ISR_NOTXBUF_POS 3 460: #define AG903_ETH_ISR_NOTXBUF_MSK (0x1UL << AG903_ETH_ISR_NOTXBUF_POS) 461: #define AG903_ETH_ISR_XPKT_OK_POS 4 462: #define AG903_ETH_ISR_XPKT_OK_MSK (0x1UL << AG903_ETH_ISR_XPKT_OK_POS) 463: #define AG903_ETH_ISR_XPKT_LOST_POS 5 464: #define AG903_ETH_ISR_XPKT_LOST_MSK (0x1UL << AG903_ETH_ISR_XPKT_LOST_POS) 465: #define AG903_ETH_ISR_RPKT_SAV_POS 6 466: #define AG903_ETH_ISR_RPKT_SAV_MSK (0x1UL << AG903_ETH_ISR_RPKT_SAV_POS) 467: #define AG903_ETH_ISR_RPKT_LOST_POS 7 468: #define AG903_ETH_ISR_RPKT_LOST_MSK (0x1UL << AG903_ETH_ISR_RPKT_LOST_POS) 469: #define AG903_ETH_ISR_AHB_ERR_POS 8 470: #define AG903_ETH_ISR_AHB_ERR_MSK (0x1UL << AG903_ETH_ISR_AHB_ERR_POS) 471: #define AG903_ETH_ISR_PHYSTS_CHG_POS 9 472: #define AG903_ETH_ISR_PHYSTS_CHG_MSK (0x1UL << AG903_ETH_ISR_PHYSTS_CHG_POS) 473: #define AG903_ETH_ISR_TX_LPI_EXIT_POS 10 474: #define AG903_ETH_ISR_TX_LPI_EXIT_MSK (0x1UL << AG903_ETH_ISR_TX_LPI_EXIT_POS) 475: #define AG903_ETH_ISR_TX_LPI_IN_POS 11 476: #define AG903_ETH_ISR_TX_LPI_IN_MSK (0x1UL << AG903_ETH_ISR_TX_LPI_IN_POS) 477: #define AG903_ETH_ISR_RX_LPI_EXIT_POS 12 478: #define AG903_ETH_ISR_RX_LPI_EXIT_MSK (0x1UL << AG903_ETH_ISR_RX_LPI_EXIT_POS) 479: #define AG903_ETH_ISR_RX_LPI_IN_POS 13 480: #define AG903_ETH_ISR_RX_LPI_IN_MSK (0x1UL << AG903_ETH_ISR_RX_LPI_IN_POS) 481: 482: #define AG903_ETH_IME_RPKT_FINISH_EN_POS 0 483: #define AG903_ETH_IME_RPKT_FINISH_EN_MSK (0x1UL << AG903_ETH_IME_RPKT_FINISH_EN_POS) 484: #define AG903_ETH_IME_NORXBUF_EN_POS 1 485: #define AG903_ETH_IME_NORXBUF_EN_MSK (0x1UL << AG903_ETH_IME_NORXBUF_EN_POS) 486: #define AG903_ETH_IME_XPKT_FINISH_EN_POS 2 487: #define AG903_ETH_IME_XPKT_FINISH_EN_MSK (0x1UL << AG903_ETH_IME_XPKT_FINISH_EN_POS) 488: #define AG903_ETH_IME_NOTXBUF_EN_POS 3 489: #define AG903_ETH_IME_NOTXBUF_EN_MSK (0x1UL << AG903_ETH_IME_NOTXBUF_EN_POS) 490: #define AG903_ETH_IME_XPKT_OK_EN_POS 4 491: #define AG903_ETH_IME_XPKT_OK_EN_MSK (0x1UL << AG903_ETH_IME_XPKT_OK_EN_POS) 492: #define AG903_ETH_IME_XPKT_LOST_EN_POS 5 493: #define AG903_ETH_IME_XPKT_LOST_EN_MSK (0x1UL << AG903_ETH_IME_XPKT_LOST_EN_POS) 494: #define AG903_ETH_IME_RPKT_SAV_EN_POS 6 495: #define AG903_ETH_IME_RPKT_SAV_EN_MSK (0x1UL << AG903_ETH_IME_RPKT_SAV_EN_POS) 496: #define AG903_ETH_IME_RPKT_LOST_EN_POS 7 497: #define AG903_ETH_IME_RPKT_LOST_EN_MSK (0x1UL << AG903_ETH_IME_RPKT_LOST_EN_POS) 498: #define AG903_ETH_IME_AHB_ERR_EN_POS 8 499: #define AG903_ETH_IME_AHB_ERR_EN_MSK (0x1UL << AG903_ETH_IME_AHB_ERR_EN_POS) 500: #define AG903_ETH_IME_PHYSTS_CHG_EN_POS 9 501: #define AG903_ETH_IME_PHYSTS_CHG_EN_MSK (0x1UL << AG903_ETH_IME_PHYSTS_CHG_EN_POS) 502: #define AG903_ETH_IME_TX_LPI_EXIT_EN_POS 10 503: #define AG903_ETH_IME_TX_LPI_EXIT_EN_MSK (0x1UL << AG903_ETH_IME_TX_LPI_EXIT_EN_POS) 504: #define AG903_ETH_IME_TX_LPI_IN_EN_POS 11 505: #define AG903_ETH_IME_TX_LPI_IN_EN_MSK (0x1UL << AG903_ETH_IME_TX_LPI_IN_EN_POS) 506: #define AG903_ETH_IME_RX_LPI_EXIT_EN_POS 12 507: #define AG903_ETH_IME_RX_LPI_EXIT_EN_MSK (0x1UL << AG903_ETH_IME_RX_LPI_EXIT_EN_POS) 508: #define AG903_ETH_IME_RX_LPI_IN_EN_POS 13 509: #define AG903_ETH_IME_RX_LPI_IN_EN_MSK (0x1UL << AG903_ETH_IME_RX_LPI_IN_EN_POS) 510: 511: #define AG903_ETH_MAC_MADR_MAC_MADR_POS 0 512: #define AG903_ETH_MAC_MADR_MAC_MADR_MSK (0xffffUL << AG903_ETH_MAC_MADR_MAC_MADR_POS) 513: 514: #define AG903_ETH_MAC_LADR_MAC_LADR_POS 0 515: #define AG903_ETH_MAC_LADR_MAC_LADR_MSK (0xffffffffUL << AG903_ETH_MAC_LADR_MAC_LADR_POS) 516: 517: #define AG903_ETH_MAHT0_MAHT0_POS 0 518: #define AG903_ETH_MAHT0_MAHT0_MSK (0xffffffffUL << AG903_ETH_MAHT0_MAHT0_POS) 519: 520: #define AG903_ETH_MAHT1_MAHT1_POS 0 521: #define AG903_ETH_MAHT1_MAHT1_MSK (0xffffffffUL << AG903_ETH_MAHT1_MAHT1_POS) 522: 523: #define AG903_ETH_TXPD_TXPD_POS 0 524: #define AG903_ETH_TXPD_TXPD_MSK (0xffffffffUL << AG903_ETH_TXPD_TXPD_POS) 525: 526: #define AG903_ETH_RXPD_RXPD_POS 0 527: #define AG903_ETH_RXPD_RXPD_MSK (0xffffffffUL << AG903_ETH_RXPD_RXPD_POS) 528: 529: #define AG903_ETH_TXR_BADR_TXR_BADR_POS 0 530: #define AG903_ETH_TXR_BADR_TXR_BADR_MSK (0xffffffffUL << AG903_ETH_TXR_BADR_TXR_BADR_POS) 531: 532: #define AG903_ETH_RXR_BADR_RXR_BADR_POS 0 533: #define AG903_ETH_RXR_BADR_RXR_BADR_MSK (0xffffffffUL << AG903_ETH_RXR_BADR_RXR_BADR_POS) 534: 535: #define AG903_ETH_ITC_RXINT_CNT_POS 0 536: #define AG903_ETH_ITC_RXINT_CNT_MSK (0xfUL << AG903_ETH_ITC_RXINT_CNT_POS) 537: #define AG903_ETH_ITC_RXINT_THR_POS 4 538: #define AG903_ETH_ITC_RXINT_THR_MSK (0x7UL << AG903_ETH_ITC_RXINT_THR_POS) 539: #define AG903_ETH_ITC_RXINT_TIME_SEL_POS 7 540: #define AG903_ETH_ITC_RXINT_TIME_SEL_MSK (0x1UL << AG903_ETH_ITC_RXINT_TIME_SEL_POS) 541: #define AG903_ETH_ITC_TXINT_CNT_POS 8 542: #define AG903_ETH_ITC_TXINT_CNT_MSK (0xfUL << AG903_ETH_ITC_TXINT_CNT_POS) 543: #define AG903_ETH_ITC_TXINT_THR_POS 12 544: #define AG903_ETH_ITC_TXINT_THR_MSK (0x7UL << AG903_ETH_ITC_TXINT_THR_POS) 545: #define AG903_ETH_ITC_TXINT_TIME_SEL_POS 15 546: #define AG903_ETH_ITC_TXINT_TIME_SEL_MSK (0x1UL << AG903_ETH_ITC_TXINT_TIME_SEL_POS) 547: 548: #define AG903_ETH_APTC_RXPOLL_CNT_POS 0 549: #define AG903_ETH_APTC_RXPOLL_CNT_MSK (0xfUL << AG903_ETH_APTC_RXPOLL_CNT_POS) 550: #define AG903_ETH_APTC_RXPOLL_TIME_SEL_POS 4 551: #define AG903_ETH_APTC_RXPOLL_TIME_SEL_MSK (0x1UL << AG903_ETH_APTC_RXPOLL_TIME_SEL_POS) 552: #define AG903_ETH_APTC_TXPOLL_CNT_POS 8 553: #define AG903_ETH_APTC_TXPOLL_CNT_MSK (0xfUL << AG903_ETH_APTC_TXPOLL_CNT_POS) 554: #define AG903_ETH_APTC_TXPOLL_TIME_SEL_POS 12 555: #define AG903_ETH_APTC_TXPOLL_TIME_SEL_MSK (0x1UL << AG903_ETH_APTC_TXPOLL_TIME_SEL_POS) 556: 557: #define AG903_ETH_DBLAC_RXFIFO_LTHR_POS 3 558: #define AG903_ETH_DBLAC_RXFIFO_LTHR_MSK (0x7UL << AG903_ETH_DBLAC_RXFIFO_LTHR_POS) 559: #define AG903_ETH_DBLAC_RXFIFO_HTHR_POS 6 560: #define AG903_ETH_DBLAC_RXFIFO_HTHR_MSK (0x7UL << AG903_ETH_DBLAC_RXFIFO_HTHR_POS) 561: #define AG903_ETH_DBLAC_RX_THR_EN_POS 9 562: #define AG903_ETH_DBLAC_RX_THR_EN_MSK (0x1UL << AG903_ETH_DBLAC_RX_THR_EN_POS) 563: #define AG903_ETH_DBLAC_INCR_SEL_POS 14 564: #define AG903_ETH_DBLAC_INCR_SEL_MSK (0x3UL << AG903_ETH_DBLAC_INCR_SEL_POS) 565: 566: #define AG903_ETH_REVR_REV_B3_POS 0 567: #define AG903_ETH_REVR_REV_B3_MSK (0xffUL << AG903_ETH_REVR_REV_B3_POS) 568: #define AG903_ETH_REVR_REV_B2_POS 8 569: #define AG903_ETH_REVR_REV_B2_MSK (0xffUL << AG903_ETH_REVR_REV_B2_POS) 570: #define AG903_ETH_REVR_REV_B1_POS 16 571: #define AG903_ETH_REVR_REV_B1_MSK (0xffUL << AG903_ETH_REVR_REV_B1_POS) 572: 573: #define AG903_ETH_LPICR_WAKE_CNT_POS 0 574: #define AG903_ETH_LPICR_WAKE_CNT_MSK (0xffffUL << AG903_ETH_LPICR_WAKE_CNT_POS) 575: #define AG903_ETH_LPICR_IDLE_CNT_POS 16 576: #define AG903_ETH_LPICR_IDLE_CNT_MSK (0xffUL << AG903_ETH_LPICR_IDLE_CNT_POS) 577: #define AG903_ETH_LPICR_TX_LPI_EN_POS 24 578: #define AG903_ETH_LPICR_TX_LPI_EN_MSK (0x1UL << AG903_ETH_LPICR_TX_LPI_EN_POS) 579: #define AG903_ETH_LPICR_RX_LPI_EN_POS 25 580: #define AG903_ETH_LPICR_RX_LPI_EN_MSK (0x1UL << AG903_ETH_LPICR_RX_LPI_EN_POS) 581: 582: #define AG903_ETH_MACCR_XDMA_EN_POS 0 583: #define AG903_ETH_MACCR_XDMA_EN_MSK (0x1UL << AG903_ETH_MACCR_XDMA_EN_POS) 584: #define AG903_ETH_MACCR_RDMA_EN_POS 1 585: #define AG903_ETH_MACCR_RDMA_EN_MSK (0x1UL << AG903_ETH_MACCR_RDMA_EN_POS) 586: #define AG903_ETH_MACCR_SW_RST_POS 2 587: #define AG903_ETH_MACCR_SW_RST_MSK (0x1UL << AG903_ETH_MACCR_SW_RST_POS) 588: #define AG903_ETH_MACCR_LOOP_EN_POS 3 589: #define AG903_ETH_MACCR_LOOP_EN_MSK (0x1UL << AG903_ETH_MACCR_LOOP_EN_POS) 590: #define AG903_ETH_MACCR_CRC_DIS_POS 4 591: #define AG903_ETH_MACCR_CRC_DIS_MSK (0x1UL << AG903_ETH_MACCR_CRC_DIS_POS) 592: #define AG903_ETH_MACCR_XMT_EN_POS 5 593: #define AG903_ETH_MACCR_XMT_EN_MSK (0x1UL << AG903_ETH_MACCR_XMT_EN_POS) 594: #define AG903_ETH_MACCR_ENRX_IN_HALFTX_POS 6 595: #define AG903_ETH_MACCR_ENRX_IN_HALFTX_MSK (0x1UL << AG903_ETH_MACCR_ENRX_IN_HALFTX_POS) 596: #define AG903_ETH_MACCR_RCV_EN_POS 8 597: #define AG903_ETH_MACCR_RCV_EN_MSK (0x1UL << AG903_ETH_MACCR_RCV_EN_POS) 598: #define AG903_ETH_MACCR_HT_MULTI_EN_POS 9 599: #define AG903_ETH_MACCR_HT_MULTI_EN_MSK (0x1UL << AG903_ETH_MACCR_HT_MULTI_EN_POS) 600: #define AG903_ETH_MACCR_RX_RUNT_POS 10 601: #define AG903_ETH_MACCR_RX_RUNT_MSK (0x1UL << AG903_ETH_MACCR_RX_RUNT_POS) 602: #define AG903_ETH_MACCR_RX_FTL_POS 11 603: #define AG903_ETH_MACCR_RX_FTL_MSK (0x1UL << AG903_ETH_MACCR_RX_FTL_POS) 604: #define AG903_ETH_MACCR_RCV_ALL_POS 12 605: #define AG903_ETH_MACCR_RCV_ALL_MSK (0x1UL << AG903_ETH_MACCR_RCV_ALL_POS) 606: #define AG903_ETH_MACCR_CRC_APD_POS 14 607: #define AG903_ETH_MACCR_CRC_APD_MSK (0x1UL << AG903_ETH_MACCR_CRC_APD_POS) 608: #define AG903_ETH_MACCR_FULLDUP_POS 15 609: #define AG903_ETH_MACCR_FULLDUP_MSK (0x1UL << AG903_ETH_MACCR_FULLDUP_POS) 610: #define AG903_ETH_MACCR_RX_MULTIPKT_POS 16 611: #define AG903_ETH_MACCR_RX_MULTIPKT_MSK (0x1UL << AG903_ETH_MACCR_RX_MULTIPKT_POS) 612: #define AG903_ETH_MACCR_RX_BROADPKT_POS 17 613: #define AG903_ETH_MACCR_RX_BROADPKT_MSK (0x1UL << AG903_ETH_MACCR_RX_BROADPKT_POS) 614: #define AG903_ETH_MACCR_SPEED_100_POS 18 615: #define AG903_ETH_MACCR_SPEED_100_MSK (0x1UL << AG903_ETH_MACCR_SPEED_100_POS) 616: #define AG903_ETH_MACCR_ZEROCOPY_DIS_POS 19 617: #define AG903_ETH_MACCR_ZEROCOPY_DIS_MSK (0x1UL << AG903_ETH_MACCR_ZEROCOPY_DIS_POS) 618: 619: #define AG903_ETH_MACSR_MULTICAST_POS 0 620: #define AG903_ETH_MACSR_MULTICAST_MSK (0x1UL << AG903_ETH_MACSR_MULTICAST_POS) 621: #define AG903_ETH_MACSR_BROADCAST_POS 1 622: #define AG903_ETH_MACSR_BROADCAST_MSK (0x1UL << AG903_ETH_MACSR_BROADCAST_POS) 623: #define AG903_ETH_MACSR_COL_POS 2 624: #define AG903_ETH_MACSR_COL_MSK (0x1UL << AG903_ETH_MACSR_COL_POS) 625: #define AG903_ETH_MACSR_RPKT_SAVE_POS 3 626: #define AG903_ETH_MACSR_RPKT_SAVE_MSK (0x1UL << AG903_ETH_MACSR_RPKT_SAVE_POS) 627: #define AG903_ETH_MACSR_RPKT_LOST_POS 4 628: #define AG903_ETH_MACSR_RPKT_LOST_MSK (0x1UL << AG903_ETH_MACSR_RPKT_LOST_POS) 629: #define AG903_ETH_MACSR_CRC_ERR_POS 5 630: #define AG903_ETH_MACSR_CRC_ERR_MSK (0x1UL << AG903_ETH_MACSR_CRC_ERR_POS) 631: #define AG903_ETH_MACSR_FTL_POS 6 632: #define AG903_ETH_MACSR_FTL_MSK (0x1UL << AG903_ETH_MACSR_FTL_POS) 633: #define AG903_ETH_MACSR_RUNT_POS 7 634: #define AG903_ETH_MACSR_RUNT_MSK (0x1UL << AG903_ETH_MACSR_RUNT_POS) 635: #define AG903_ETH_MACSR_XPKT_OK_POS 8 636: #define AG903_ETH_MACSR_XPKT_OK_MSK (0x1UL << AG903_ETH_MACSR_XPKT_OK_POS) 637: #define AG903_ETH_MACSR_XPKT_LOST_POS 9 638: #define AG903_ETH_MACSR_XPKT_LOST_MSK (0x1UL << AG903_ETH_MACSR_XPKT_LOST_POS) 639: #define AG903_ETH_MACSR_LATE_COL_POS 10 640: #define AG903_ETH_MACSR_LATE_COL_MSK (0x1UL << AG903_ETH_MACSR_LATE_COL_POS) 641: #define AG903_ETH_MACSR_COL_EXCEED_POS 11 642: #define AG903_ETH_MACSR_COL_EXCEED_MSK (0x1UL << AG903_ETH_MACSR_COL_EXCEED_POS) 643: 644: #define AG903_ETH_PHYCR_MIIRDATA_POS 0 645: #define AG903_ETH_PHYCR_MIIRDATA_MSK (0xffffUL << AG903_ETH_PHYCR_MIIRDATA_POS) 646: #define AG903_ETH_PHYCR_PHYAD_POS 16 647: #define AG903_ETH_PHYCR_PHYAD_MSK (0x1fUL << AG903_ETH_PHYCR_PHYAD_POS) 648: #define AG903_ETH_PHYCR_REGAD_POS 21 649: #define AG903_ETH_PHYCR_REGAD_MSK (0x1fUL << AG903_ETH_PHYCR_REGAD_POS) 650: #define AG903_ETH_PHYCR_MIIRD_POS 26 651: #define AG903_ETH_PHYCR_MIIRD_MSK (0x1UL << AG903_ETH_PHYCR_MIIRD_POS) 652: #define AG903_ETH_PHYCR_MIIWR_POS 27 653: #define AG903_ETH_PHYCR_MIIWR_MSK (0x1UL << AG903_ETH_PHYCR_MIIWR_POS) 654: 655: #define AG903_ETH_PHYWDATA_MIIWDATA_POS 0 656: #define AG903_ETH_PHYWDATA_MIIWDATA_MSK (0xffffUL << AG903_ETH_PHYWDATA_MIIWDATA_POS) 657: #define AG903_ETH_PHYWDATA_MDC_CYCTHR_POS 16 658: #define AG903_ETH_PHYWDATA_MDC_CYCTHR_MSK (0xffUL << AG903_ETH_PHYWDATA_MDC_CYCTHR_POS) 659: 660: #define AG903_ETH_FCR_FC_EN_POS 0 661: #define AG903_ETH_FCR_FC_EN_MSK (0x1UL << AG903_ETH_FCR_FC_EN_POS) 662: #define AG903_ETH_FCR_TX_PAUSE_POS 1 663: #define AG903_ETH_FCR_TX_PAUSE_MSK (0x1UL << AG903_ETH_FCR_TX_PAUSE_POS) 664: #define AG903_ETH_FCR_FCTHR_EN_POS 2 665: #define AG903_ETH_FCR_FCTHR_EN_MSK (0x1UL << AG903_ETH_FCR_FCTHR_EN_POS) 666: #define AG903_ETH_FCR_TXPAUSED_POS 3 667: #define AG903_ETH_FCR_TXPAUSED_MSK (0x1UL << AG903_ETH_FCR_TXPAUSED_POS) 668: #define AG903_ETH_FCR_RX_PAUSE_POS 4 669: #define AG903_ETH_FCR_RX_PAUSE_MSK (0x1UL << AG903_ETH_FCR_RX_PAUSE_POS) 670: #define AG903_ETH_FCR_FC_LOW_POS 8 671: #define AG903_ETH_FCR_FC_LOW_MSK (0xfUL << AG903_ETH_FCR_FC_LOW_POS) 672: #define AG903_ETH_FCR_FC_HIGH_POS 12 673: #define AG903_ETH_FCR_FC_HIGH_MSK (0xfUL << AG903_ETH_FCR_FC_HIGH_POS) 674: #define AG903_ETH_FCR_PAUSE_TIME_POS 16 675: #define AG903_ETH_FCR_PAUSE_TIME_MSK (0xffffUL << AG903_ETH_FCR_PAUSE_TIME_POS) 676: 677: #define AG903_ETH_BPR_BK_EN_POS 0 678: #define AG903_ETH_BPR_BK_EN_MSK (0x1UL << AG903_ETH_BPR_BK_EN_POS) 679: #define AG903_ETH_BPR_BK_MODE_POS 1 680: #define AG903_ETH_BPR_BK_MODE_MSK (0x1UL << AG903_ETH_BPR_BK_MODE_POS) 681: #define AG903_ETH_BPR_BKJAM_LEN_POS 4 682: #define AG903_ETH_BPR_BKJAM_LEN_MSK (0xfUL << AG903_ETH_BPR_BKJAM_LEN_POS) 683: #define AG903_ETH_BPR_BK_LOW_POS 8 684: #define AG903_ETH_BPR_BK_LOW_MSK (0xfUL << AG903_ETH_BPR_BK_LOW_POS) 685: 686: #define AG903_ETH_WOLCR_LINKCHG0_EN_POS 0 687: #define AG903_ETH_WOLCR_LINKCHG0_EN_MSK (0x1UL << AG903_ETH_WOLCR_LINKCHG0_EN_POS) 688: #define AG903_ETH_WOLCR_LINKCHG1_EN_POS 1 689: #define AG903_ETH_WOLCR_LINKCHG1_EN_MSK (0x1UL << AG903_ETH_WOLCR_LINKCHG1_EN_POS) 690: #define AG903_ETH_WOLCR_MAGICPKT_EN_POS 2 691: #define AG903_ETH_WOLCR_MAGICPKT_EN_MSK (0x1UL << AG903_ETH_WOLCR_MAGICPKT_EN_POS) 692: #define AG903_ETH_WOLCR_WAKEUP1_EN_POS 3 693: #define AG903_ETH_WOLCR_WAKEUP1_EN_MSK (0x1UL << AG903_ETH_WOLCR_WAKEUP1_EN_POS) 694: #define AG903_ETH_WOLCR_WAKEUP2_EN_POS 4 695: #define AG903_ETH_WOLCR_WAKEUP2_EN_MSK (0x1UL << AG903_ETH_WOLCR_WAKEUP2_EN_POS) 696: #define AG903_ETH_WOLCR_WAKEUP3_EN_POS 5 697: #define AG903_ETH_WOLCR_WAKEUP3_EN_MSK (0x1UL << AG903_ETH_WOLCR_WAKEUP3_EN_POS) 698: #define AG903_ETH_WOLCR_WAKEUP4_EN_POS 6 699: #define AG903_ETH_WOLCR_WAKEUP4_EN_MSK (0x1UL << AG903_ETH_WOLCR_WAKEUP4_EN_POS) 700: #define AG903_ETH_WOLCR_POWER_STATE_POS 14 701: #define AG903_ETH_WOLCR_POWER_STATE_MSK (0x3UL << AG903_ETH_WOLCR_POWER_STATE_POS) 702: #define AG903_ETH_WOLCR_WAKEUP_SEL_POS 16 703: #define AG903_ETH_WOLCR_WAKEUP_SEL_MSK (0x3UL << AG903_ETH_WOLCR_WAKEUP_SEL_POS) 704: #define AG903_ETH_WOLCR_SW_PDNPHY_POS 18 705: #define AG903_ETH_WOLCR_SW_PDNPHY_MSK (0x1UL << AG903_ETH_WOLCR_SW_PDNPHY_POS) 706: #define AG903_ETH_WOLCR_WOL_TYPE_POS 24 707: #define AG903_ETH_WOLCR_WOL_TYPE_MSK (0x3UL << AG903_ETH_WOLCR_WOL_TYPE_POS) 708: 709: #define AG903_ETH_WOLSR_LINKCHG0_STS_POS 0 710: #define AG903_ETH_WOLSR_LINKCHG0_STS_MSK (0x1UL << AG903_ETH_WOLSR_LINKCHG0_STS_POS) 711: #define AG903_ETH_WOLSR_LINKCHG1_STS_POS 1 712: #define AG903_ETH_WOLSR_LINKCHG1_STS_MSK (0x1UL << AG903_ETH_WOLSR_LINKCHG1_STS_POS) 713: #define AG903_ETH_WOLSR_MAGICPKT_STS_POS 2 714: #define AG903_ETH_WOLSR_MAGICPKT_STS_MSK (0x1UL << AG903_ETH_WOLSR_MAGICPKT_STS_POS) 715: #define AG903_ETH_WOLSR_WAKEUP1_STS_POS 3 716: #define AG903_ETH_WOLSR_WAKEUP1_STS_MSK (0x1UL << AG903_ETH_WOLSR_WAKEUP1_STS_POS) 717: #define AG903_ETH_WOLSR_WAKEUP2_STS_POS 4 718: #define AG903_ETH_WOLSR_WAKEUP2_STS_MSK (0x1UL << AG903_ETH_WOLSR_WAKEUP2_STS_POS) 719: #define AG903_ETH_WOLSR_WAKEUP3_STS_POS 5 720: #define AG903_ETH_WOLSR_WAKEUP3_STS_MSK (0x1UL << AG903_ETH_WOLSR_WAKEUP3_STS_POS) 721: #define AG903_ETH_WOLSR_WAKEUP4_STS_POS 6 722: #define AG903_ETH_WOLSR_WAKEUP4_STS_MSK (0x1UL << AG903_ETH_WOLSR_WAKEUP4_STS_POS) 723: 724: #define AG903_ETH_WFCRC_WFCRC_POS 0 725: #define AG903_ETH_WFCRC_WFCRC_MSK (0xffffffffUL << AG903_ETH_WFCRC_WFCRC_POS) 726: 727: #define AG903_ETH_WFBM1_WFBM1_POS 0 728: #define AG903_ETH_WFBM1_WFBM1_MSK (0xffffffffUL << AG903_ETH_WFBM1_WFBM1_POS) 729: 730: #define AG903_ETH_WFBM2_WFBM2_POS 0 731: #define AG903_ETH_WFBM2_WFBM2_MSK (0xffffffffUL << AG903_ETH_WFBM2_WFBM2_POS) 732: 733: #define AG903_ETH_WFBM3_WFBM3_POS 0 734: #define AG903_ETH_WFBM3_WFBM3_MSK (0xffffffffUL << AG903_ETH_WFBM3_WFBM3_POS) 735: 736: #define AG903_ETH_WFBM4_WFBM4_POS 0 737: #define AG903_ETH_WFBM4_WFBM4_MSK (0xffffffffUL << AG903_ETH_WFBM4_WFBM4_POS) 738: 739: #define AG903_ETH_TS_Test_seed_POS 0 740: #define AG903_ETH_TS_Test_seed_MSK (0x3fffUL << AG903_ETH_TS_Test_seed_POS) 741: 742: #define AG903_ETH_DMAFIFOS_RXDMA1_SM_POS 0 743: #define AG903_ETH_DMAFIFOS_RXDMA1_SM_MSK (0xfUL << AG903_ETH_DMAFIFOS_RXDMA1_SM_POS) 744: #define AG903_ETH_DMAFIFOS_RXDMA2_SM_POS 4 745: #define AG903_ETH_DMAFIFOS_RXDMA2_SM_MSK (0x7UL << AG903_ETH_DMAFIFOS_RXDMA2_SM_POS) 746: #define AG903_ETH_DMAFIFOS_TXDMA1_SM_POS 8 747: #define AG903_ETH_DMAFIFOS_TXDMA1_SM_MSK (0xfUL << AG903_ETH_DMAFIFOS_TXDMA1_SM_POS) 748: #define AG903_ETH_DMAFIFOS_TXDMA2_SM_POS 12 749: #define AG903_ETH_DMAFIFOS_TXDMA2_SM_MSK (0x7UL << AG903_ETH_DMAFIFOS_TXDMA2_SM_POS) 750: #define AG903_ETH_DMAFIFOS_RXFIFO_EMPTY_POS 26 751: #define AG903_ETH_DMAFIFOS_RXFIFO_EMPTY_MSK (0x1UL << AG903_ETH_DMAFIFOS_RXFIFO_EMPTY_POS) 752: #define AG903_ETH_DMAFIFOS_TXFIFO_EMPTY_POS 27 753: #define AG903_ETH_DMAFIFOS_TXFIFO_EMPTY_MSK (0x1UL << AG903_ETH_DMAFIFOS_TXFIFO_EMPTY_POS) 754: #define AG903_ETH_DMAFIFOS_DARB_RXGNT_POS 28 755: #define AG903_ETH_DMAFIFOS_DARB_RXGNT_MSK (0x1UL << AG903_ETH_DMAFIFOS_DARB_RXGNT_POS) 756: #define AG903_ETH_DMAFIFOS_DARB_TXGNT_POS 29 757: #define AG903_ETH_DMAFIFOS_DARB_TXGNT_MSK (0x1UL << AG903_ETH_DMAFIFOS_DARB_TXGNT_POS) 758: #define AG903_ETH_DMAFIFOS_RXD_REQ_POS 30 759: #define AG903_ETH_DMAFIFOS_RXD_REQ_MSK (0x1UL << AG903_ETH_DMAFIFOS_RXD_REQ_POS) 760: #define AG903_ETH_DMAFIFOS_TXD_REQ_POS 31 761: #define AG903_ETH_DMAFIFOS_TXD_REQ_MSK (0x1UL << AG903_ETH_DMAFIFOS_TXD_REQ_POS) 762: 763: #define AG903_ETH_TM_TEST_EXCEL_POS 5 764: #define AG903_ETH_TM_TEST_EXCEL_MSK (0x1fUL << AG903_ETH_TM_TEST_EXCEL_POS) 765: #define AG903_ETH_TM_TEST_TIME_POS 10 766: #define AG903_ETH_TM_TEST_TIME_MSK (0x3ffUL << AG903_ETH_TM_TEST_TIME_POS) 767: #define AG903_ETH_TM_TEST_MODE_POS 20 768: #define AG903_ETH_TM_TEST_MODE_MSK (0x1UL << AG903_ETH_TM_TEST_MODE_POS) 769: #define AG903_ETH_TM_SEED_SEL_POS 21 770: #define AG903_ETH_TM_SEED_SEL_MSK (0x1UL << AG903_ETH_TM_SEED_SEL_POS) 771: #define AG903_ETH_TM_TEST_SEED_SEL_POS 22 772: #define AG903_ETH_TM_TEST_SEED_SEL_MSK (0x1UL << AG903_ETH_TM_TEST_SEED_SEL_POS) 773: #define AG903_ETH_TM_ITIMER_TEST_POS 24 774: #define AG903_ETH_TM_ITIMER_TEST_MSK (0x1UL << AG903_ETH_TM_ITIMER_TEST_POS) 775: #define AG903_ETH_TM_PTIMER_TEST_POS 25 776: #define AG903_ETH_TM_PTIMER_TEST_MSK (0x1UL << AG903_ETH_TM_PTIMER_TEST_POS) 777: #define AG903_ETH_TM_SINGLE_PKT_POS 26 778: #define AG903_ETH_TM_SINGLE_PKT_MSK (0x1UL << AG903_ETH_TM_SINGLE_PKT_POS) 779: #define AG903_ETH_TM_DMA_SWAP_POS 27 780: #define AG903_ETH_TM_DMA_SWAP_MSK (0x1UL << AG903_ETH_TM_DMA_SWAP_POS) 781: #define AG903_ETH_TM_PKT_SWAP_B_POS 28 782: #define AG903_ETH_TM_PKT_SWAP_B_MSK (0x1UL << AG903_ETH_TM_PKT_SWAP_B_POS) 783: #define AG903_ETH_TM_BIG_FORM_POS 29 784: #define AG903_ETH_TM_BIG_FORM_MSK (0x1UL << AG903_ETH_TM_BIG_FORM_POS) 785: 786: #define AG903_ETH_COLCR_TX_SCOL_POS 0 787: #define AG903_ETH_COLCR_TX_SCOL_MSK (0xffffUL << AG903_ETH_COLCR_TX_SCOL_POS) 788: #define AG903_ETH_COLCR_TX_MCOL_POS 16 789: #define AG903_ETH_COLCR_TX_MCOL_MSK (0xffffUL << AG903_ETH_COLCR_TX_MCOL_POS) 790: 791: #define AG903_ETH_REFAEPCR_AEP_POS 0 792: #define AG903_ETH_REFAEPCR_AEP_MSK (0xffffUL << AG903_ETH_REFAEPCR_AEP_POS) 793: #define AG903_ETH_REFAEPCR_RPF_POS 16 794: #define AG903_ETH_REFAEPCR_RPF_MSK (0xffffUL << AG903_ETH_REFAEPCR_RPF_POS) 795: 796: #define AG903_ETH_XMPGCR_PG_POS 0 797: #define AG903_ETH_XMPGCR_PG_MSK (0xffffUL << AG903_ETH_XMPGCR_PG_POS) 798: #define AG903_ETH_XMPGCR_XM_POS 16 799: #define AG903_ETH_XMPGCR_XM_MSK (0xffffUL << AG903_ETH_XMPGCR_XM_POS) 800: 801: #define AG903_ETH_RUNTLCCCR_TLCC_POS 0 802: #define AG903_ETH_RUNTLCCCR_TLCC_MSK (0xffffUL << AG903_ETH_RUNTLCCCR_TLCC_POS) 803: #define AG903_ETH_RUNTLCCCR_RUNT_CNT_POS 16 804: #define AG903_ETH_RUNTLCCCR_RUNT_CNT_MSK (0xffffUL << AG903_ETH_RUNTLCCCR_RUNT_CNT_POS) 805: 806: #define AG903_ETH_CRCERFTLCR_FTL_CNT_POS 0 807: #define AG903_ETH_CRCERFTLCR_FTL_CNT_MSK (0xffffUL << AG903_ETH_CRCERFTLCR_FTL_CNT_POS) 808: #define AG903_ETH_CRCERFTLCR_CRCER_CNT_POS 16 809: #define AG903_ETH_CRCERFTLCR_CRCER_CNT_MSK (0xffffUL << AG903_ETH_CRCERFTLCR_CRCER_CNT_POS) 810: 811: #define AG903_ETH_RLCRCCCR_RCC_POS 0 812: #define AG903_ETH_RLCRCCCR_RCC_MSK (0xffffUL << AG903_ETH_RLCRCCCR_RCC_POS) 813: #define AG903_ETH_RLCRCCCR_RLC_POS 16 814: #define AG903_ETH_RLCRCCCR_RLC_MSK (0xffffUL << AG903_ETH_RLCRCCCR_RLC_POS) 815: 816: #define AG903_ETH_BROCCR_BROC_POS 0 817: #define AG903_ETH_BROCCR_BROC_MSK (0xffffffffUL << AG903_ETH_BROCCR_BROC_POS) 818: 819: #define AG903_ETH_MULCACR_MULCA_POS 0 820: #define AG903_ETH_MULCACR_MULCA_MSK (0xffffffffUL << AG903_ETH_MULCACR_MULCA_POS) 821: 822: #define AG903_ETH_RPCR_RP_POS 0 823: #define AG903_ETH_RPCR_RP_MSK (0xffffffffUL << AG903_ETH_RPCR_RP_POS) 824: 825: #define AG903_ETH_XPCR_XP_POS 0 826: #define AG903_ETH_XPCR_XP_MSK (0xffffffffUL << AG903_ETH_XPCR_XP_POS) 827: 828: #endif 829:
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