1:
14:
15:
19:
20:
21:
#include "AG903_errno.h"
22:
#include "AG903_common.h"
23:
#include "sys/spcprm.h"
24:
#include "register/AG903_spcreg.h"
25:
26:
34:
void AG903_SPCPrmGetBootupStatus(uint8_t* pwr, uint8_t* wdt_rst, uint8_t* hw_rst)
35: {
36: uint32_t val;
37:
38:
ASSERT(NULL != pwr);
39:
ASSERT(NULL != wdt_rst);
40:
ASSERT(NULL != hw_rst);
41:
42: val =
AG903_SPC->BOOTUP_STATUS;
43: (*pwr) = (uint8_t)((val &
AG903_SPC_BOOTUP_STATUS_PWR_MSK) >>
AG903_SPC_BOOTUP_STATUS_PWR_POS);
44: (*wdt_rst) = (uint8_t)((val &
AG903_SPC_BOOTUP_STATUS_WDR_MSK) >>
AG903_SPC_BOOTUP_STATUS_WDR_POS);
45: (*hw_rst) = (uint8_t)((val &
AG903_SPC_BOOTUP_STATUS_HWR_MSK) >>
AG903_SPC_BOOTUP_STATUS_HWR_POS);
46:
47:
return;
48: }
49:
50:
59:
void AG903_SPCPrmClrBootupStatus(uint8_t pwr, uint8_t wdt_rst, uint8_t hw_rst)
60: {
61: uint32_t val = 0;
62:
63:
ASSERT(0 == pwr || 1 == pwr);
64:
ASSERT(0 == wdt_rst || 1 == wdt_rst);
65:
ASSERT(0 == hw_rst || 1 == hw_rst);
66:
67: val |= (pwr <<
AG903_SPC_BOOTUP_STATUS_PWR_POS) &
AG903_SPC_BOOTUP_STATUS_PWR_MSK;
68: val |= (wdt_rst <<
AG903_SPC_BOOTUP_STATUS_WDR_POS) &
AG903_SPC_BOOTUP_STATUS_WDR_MSK;
69: val |= (hw_rst <<
AG903_SPC_BOOTUP_STATUS_HWR_POS) &
AG903_SPC_BOOTUP_STATUS_HWR_MSK;
70:
AG903_SPC->BOOTUP_STATUS = val;
71:
72:
return;
73: }
74:
75:
89:
void AG903_SPCPrmSetFcsCtrl(uint8_t slf_refresh, uint8_t pll0_rst, uint8_t cpu_msk, uint8_t enable)
90: {
91: uint32_t val = 0;
92:
93:
ASSERT(2 == cpu_msk || 3 == cpu_msk);
94:
95:
if(
false == slf_refresh) {
96: val |= (uint32_t)(1 <<
AG903_SPC_FCS_CTRL_SELFR_CMD_OFF_POS);
97: }
98:
if(
false == pll0_rst) {
99: val |= (uint32_t)(1 <<
AG903_SPC_FCS_CTRL_FCS_PLL0_RSTn_POS);
100: }
101: val |= ((cpu_msk>>0 & 0x1) <<
AG903_SPC_FCS_CTRL_CPU_MASK_POS);
102: val |= ((cpu_msk>>1 & 0x1) <<
AG903_SPC_FCS_CTRL_CPU_MASK2_POS);
103:
if(
true == enable) {
104: val |= (uint32_t)(1 <<
AG903_SPC_FCS_CTRL_FCS_POS);
105: }
106:
AG903_SPC->FCS_CTRL = val;
107:
108:
return;
109: }
110:
111:
121:
void AG903_SPCPrmGetFcsCtrl(uint8_t* slf_refresh, uint8_t* pll0_rst, uint8_t* cpu_msk, uint8_t* enable)
122: {
123: uint32_t val;
124:
125:
ASSERT(NULL != slf_refresh);
126:
ASSERT(NULL != pll0_rst);
127:
ASSERT(NULL != cpu_msk);
128:
ASSERT(NULL != enable);
129:
130: val =
AG903_SPC->FCS_CTRL;
131:
if(
AG903_SPC_FCS_CTRL_SELFR_CMD_OFF_MSK & val) {
132: (*slf_refresh) =
false;
133: }
134:
else {
135: (*slf_refresh) =
true;
136: }
137:
if(
AG903_SPC_FCS_CTRL_FCS_PLL0_RSTn_MSK & val) {
138: (*pll0_rst) =
false;
139: }
140:
else {
141: (*pll0_rst) =
true;
142: }
143:
if(
AG903_SPC_FCS_CTRL_CPU_MASK_MSK & val) {
144: (*cpu_msk) = 1<<0;
145: }
146:
else {
147: (*cpu_msk) = 0<<0;
148: }
149:
if(
AG903_SPC_FCS_CTRL_CPU_MASK2_MSK & val) {
150: (*cpu_msk) |= 1<<1;
151: }
152:
else {
153: (*cpu_msk) |= 0<<1;
154: }
155:
if(
AG903_SPC_FCS_CTRL_FCS_MSK & val) {
156: (*enable) =
true;
157: }
158:
else {
159: (*enable) =
false;
160: }
161:
return;
162: }
163:
164:
171:
void AG903_SPCPrmSwReset(
void)
172: {
173: uint32_t val;
174: val =
AG903_SPC->FCS_CTRL;
175: val |= (1 <<
AG903_SPC_FCS_CTRL_SW_RST_POS);
176:
AG903_SPC->FCS_CTRL = val;
177:
return;
178: }
179:
180:
186:
void AG903_SPCPrmGetFcsIntStatus(uint8_t* status)
187: {
188: uint32_t val;
189:
190:
ASSERT(NULL != status);
191:
192: val =
AG903_SPC->INT_STATUS;
193: (*status) = (uint8_t)((val &
AG903_SPC_INT_STATUS_INT_FCS_MSK) >>
AG903_SPC_INT_STATUS_INT_FCS_POS);
194:
195:
return;
196: }
197:
198:
204:
void AG903_SPCPrmClrFcsIntStatus(
void)
205: {
206:
AG903_SPC->INT_STATUS = (1 <<
AG903_SPC_INT_STATUS_INT_FCS_POS);
207:
return;
208: }
209:
210:
216:
void AG903_SPCPrmSetFcsIntEnable(uint8_t enable)
217: {
218: uint32_t val = 0;
219:
220:
if(
true == enable) {
221: val |= (1 <<
AG903_SPC_INT_ENABLE_EINT_FCS_POS);
222: }
223:
AG903_SPC->INT_ENABLE = val;
224:
225:
return;
226: }
227:
228:
234:
void AG903_SPCPrmGetFcsIntEnable(uint8_t* enable)
235: {
236: uint32_t val;
237:
238:
ASSERT(NULL != enable);
239:
240: val =
AG903_SPC->INT_ENABLE;
241:
if(
AG903_SPC_INT_ENABLE_EINT_FCS_MSK & val) {
242: (*enable) =
true;
243: }
244:
else {
245: (*enable) =
false;
246: }
247:
248:
return;
249: }
250:
251:
258:
void AG903_SPCPrmSetSoftResetSetup(uint8_t wait, uint8_t active)
259: {
260: uint32_t val = 0;
261:
262: val |= (wait <<
AG903_SPC_SOFTRESET_SETUP_SWRST_WAIT_POS) &
AG903_SPC_SOFTRESET_SETUP_SWRST_WAIT_MSK;
263: val |= (active <<
AG903_SPC_SOFTRESET_SETUP_SWRST_ACTIVE_POS) &
AG903_SPC_SOFTRESET_SETUP_SWRST_ACTIVE_MSK;
264:
AG903_SPC->SOFTRESET_SETUP = val;
265:
266:
return;
267: }
268:
269:
276:
void AG903_SPCPrmGetSoftResetSetup(uint8_t* wait, uint8_t* active)
277: {
278: uint32_t val;
279:
280:
ASSERT(NULL != wait);
281:
ASSERT(NULL != active);
282:
283: val =
AG903_SPC->SOFTRESET_SETUP;
284: (*wait) = (uint8_t)((val &
AG903_SPC_SOFTRESET_SETUP_SWRST_WAIT_MSK) >>
AG903_SPC_SOFTRESET_SETUP_SWRST_WAIT_POS);
285: (*active) = (uint8_t)((val &
AG903_SPC_SOFTRESET_SETUP_SWRST_ACTIVE_MSK) >>
AG903_SPC_SOFTRESET_SETUP_SWRST_ACTIVE_POS);
286:
287:
return;
288: }
289:
290:
297:
void AG903_SPCPrmSetPll0Ctrl(
AG903_SPCPrmPllnParam* param)
298: {
299: uint32_t val = 0;
300:
301:
ASSERT(NULL != param);
302:
303: val |= (param->ns <<
AG903_SPC_PLL0_CTRL_NS_POS) &
AG903_SPC_PLL0_CTRL_NS_MSK;
304: val |= (param->ms <<
AG903_SPC_PLL0_CTRL_MS_POS) &
AG903_SPC_PLL0_CTRL_MS_MSK;
305: val |= (param->div <<
AG903_SPC_PLL0_CTRL_DIV_POS) &
AG903_SPC_PLL0_CTRL_DIV_MSK;
306:
if(
true == param->en) {
307: val |= (1 <<
AG903_SPC_PLL0_CTRL_EN_POS);
308: }
309:
AG903_SPC->PLL0_CTRL = val;
310:
311:
return;
312: }
313:
314:
321:
void AG903_SPCPrmGetPll0Ctrl(
AG903_SPCPrmPllnParam* param, uint8_t* status)
322: {
323: uint32_t val;
324:
325:
ASSERT(NULL != param);
326:
ASSERT(NULL != status);
327:
328: val =
AG903_SPC->PLL0_CTRL;
329: param->ns = (uint8_t)((val &
AG903_SPC_PLL0_CTRL_NS_MSK) >>
AG903_SPC_PLL0_CTRL_NS_POS);
330: param->ms = (uint8_t)((val &
AG903_SPC_PLL0_CTRL_MS_MSK) >>
AG903_SPC_PLL0_CTRL_MS_POS);
331: param->div = (uint8_t)((val &
AG903_SPC_PLL0_CTRL_DIV_MSK) >>
AG903_SPC_PLL0_CTRL_DIV_POS);
332:
if(
AG903_SPC_PLL0_CTRL_EN_MSK & val) {
333: param->en =
true;
334: }
335:
else {
336: param->en =
false;
337: }
338: (*status) = (uint8_t)((val &
AG903_SPC_PLL0_CTRL_STB_MSK) >>
AG903_SPC_PLL0_CTRL_STB_POS);
339:
340:
return;
341: }
342:
343:
350:
void AG903_SPCPrmSetDdrPhyPll(uint8_t enable)
351: {
352: uint32_t val;
353:
354: val =
AG903_SPC->DDRPHY_PLLSETUP;
355:
if(
true == enable) {
356: val |= (1 <<
AG903_SPC_DDRPHY_PLLSETUP_PLLEN_POS);
357: }
358:
else {
359: val &= ~
AG903_SPC_DDRPHY_PLLSETUP_PLLEN_MSK;
360: }
361:
AG903_SPC->DDRPHY_PLLSETUP = val;
362:
363:
return;
364: }
365:
366:
372:
void AG903_SPCPrmGetDdrPhyPll(uint8_t* enable)
373: {
374: uint32_t val;
375:
376:
ASSERT(NULL != enable);
377:
378: val =
AG903_SPC->DDRPHY_PLLSETUP;
379:
if(
AG903_SPC_DDRPHY_PLLSETUP_PLLEN_MSK & val) {
380: (*enable) =
true;
381: }
382:
else {
383: (*enable) =
false;
384: }
385:
return;
386: }
387:
388:
396:
void AG903_SPCPrmSetDdrPhyDll(uint8_t frange, uint8_t enable)
397: {
398: uint32_t val = 0;
399:
400: val |= (frange <<
AG903_SPC_DDRPHY_DLLSETUP_FRANGE_POS) &
AG903_SPC_DDRPHY_DLLSETUP_FRANGE_MSK;
401:
if(
true == enable) {
402: val |= (1 <<
AG903_SPC_DDRPHY_DLLSETUP_DLLEN_POS);
403: }
404:
AG903_SPC->DDRPHY_DLLSETUP = val;
405:
406:
return;
407: }
408:
409:
416:
void AG903_SPCPrmGetDdrPhyDll(uint8_t* frange, uint8_t* enable)
417: {
418: uint32_t val;
419:
420:
ASSERT(NULL != frange);
421:
ASSERT(NULL != enable);
422:
423: val =
AG903_SPC->DDRPHY_DLLSETUP;
424: (*frange) = (uint8_t)((val &
AG903_SPC_DDRPHY_DLLSETUP_FRANGE_MSK) >>
AG903_SPC_DDRPHY_DLLSETUP_FRANGE_POS);
425:
if(
AG903_SPC_DDRPHY_DLLSETUP_DLLEN_MSK & val) {
426: (*enable) =
true;
427: }
428:
else {
429: (*enable) =
false;
430: }
431:
return;
432: }
433:
434:
441:
void AG903_SPCPrmSetAhbClkCtrl(uint32_t clk_en)
442: {
443:
AG903_SPC->AHB_CLK_CTRL = clk_en;
444:
return;
445: }
446:
447:
454:
void AG903_SPCPrmGetAhbClkCtrl(uint32_t* clk_en)
455: {
456:
ASSERT(NULL != clk_en);
457: (*clk_en) =
AG903_SPC->AHB_CLK_CTRL;
458:
return;
459: }
460:
461:
468:
void AG903_SPCPrmSetApbClkCtrl(uint32_t clk_en)
469: {
470:
AG903_SPC->APB_CLK_CTRL = clk_en;
471:
return;
472: }
473:
474:
481:
void AG903_SPCPrmGetApbClkCtrl(uint32_t* clk_en)
482: {
483:
ASSERT(NULL != clk_en);
484: (*clk_en) =
AG903_SPC->APB_CLK_CTRL;
485:
return;
486: }
487:
488:
495:
void AG903_SPCPrmSetAxiClkCtrl1(uint32_t clk_en)
496: {
497:
AG903_SPC->AXI_CLK_CTRL1 = clk_en;
498:
return;
499: }
500:
501:
508:
void AG903_SPCPrmGetAxiClkCtrl1(uint32_t* clk_en)
509: {
510:
ASSERT(NULL != clk_en);
511: (*clk_en) =
AG903_SPC->AXI_CLK_CTRL1;
512:
return;
513: }
514:
515:
522:
void AG903_SPCPrmSetAxiClkCtrl2(uint32_t clk_en)
523: {
524:
AG903_SPC->AXI_CLK_CTRL2 = clk_en;
525:
return;
526: }
527:
528:
535:
void AG903_SPCPrmGetAxiClkCtrl2(uint32_t* clk_en)
536: {
537:
ASSERT(NULL != clk_en);
538: (*clk_en) =
AG903_SPC->AXI_CLK_CTRL2;
539:
return;
540: }
541:
542:
548:
void AG903_SPCPrmSetPll1Ctrl(
AG903_SPCPrmPllnParam* param)
549: {
550: uint32_t val = 0;
551:
552: val |= (param->src <<
AG903_SPC_PLL1_CTRL_SRC_POS) &
AG903_SPC_PLL1_CTRL_SRC_MSK;
553: val |= (param->ns <<
AG903_SPC_PLL1_CTRL_NS_POS) &
AG903_SPC_PLL1_CTRL_NS_MSK;
554: val |= (param->ms <<
AG903_SPC_PLL1_CTRL_MS_POS) &
AG903_SPC_PLL1_CTRL_MS_MSK;
555: val |= (param->div <<
AG903_SPC_PLL1_CTRL_DIV_POS) &
AG903_SPC_PLL1_CTRL_DIV_MSK;
556: val |= (param->frange <<
AG903_SPC_PLL1_CTRL_FR_POS) &
AG903_SPC_PLL1_CTRL_FR_MSK;
557:
if(
true == param->en) {
558: val |= (1 <<
AG903_SPC_PLL1_CTRL_EN_POS);
559: }
560:
AG903_SPC->PLL1_CTRL = val;
561:
562:
return;
563: }
564:
565:
571:
void AG903_SPCPrmGetPll1Ctrl(
AG903_SPCPrmPllnParam* param)
572: {
573: uint32_t val;
574:
575:
ASSERT(NULL != param);
576:
577: val =
AG903_SPC->PLL1_CTRL;
578: param->src = (uint8_t)((val &
AG903_SPC_PLL1_CTRL_SRC_MSK) >>
AG903_SPC_PLL1_CTRL_SRC_POS);
579: param->ns = (uint8_t)((val &
AG903_SPC_PLL1_CTRL_NS_MSK) >>
AG903_SPC_PLL1_CTRL_NS_POS);
580: param->ms = (uint8_t)((val &
AG903_SPC_PLL1_CTRL_MS_MSK) >>
AG903_SPC_PLL1_CTRL_MS_POS);
581: param->div = (uint8_t)((val &
AG903_SPC_PLL1_CTRL_DIV_MSK) >>
AG903_SPC_PLL1_CTRL_DIV_POS);
582: param->frange = (uint8_t)((val &
AG903_SPC_PLL1_CTRL_FR_MSK) >>
AG903_SPC_PLL1_CTRL_FR_POS);
583:
if(
AG903_SPC_PLL1_CTRL_EN_MSK & val) {
584: param->en =
true;
585: }
586:
else {
587: param->en =
false;
588: }
589:
590:
return;
591: }
592:
593:
599:
void AG903_SPCPrmSetPll2Ctrl(
AG903_SPCPrmPllnParam* param)
600: {
601: uint32_t val = 0;
602:
603: val |= (param->src <<
AG903_SPC_PLL2_CTRL_SRC_POS) &
AG903_SPC_PLL2_CTRL_SRC_MSK;
604: val |= (param->ns <<
AG903_SPC_PLL2_CTRL_NS_POS) &
AG903_SPC_PLL2_CTRL_NS_MSK;
605: val |= (param->ms <<
AG903_SPC_PLL2_CTRL_MS_POS) &
AG903_SPC_PLL2_CTRL_MS_MSK;
606: val |= (param->div <<
AG903_SPC_PLL2_CTRL_DIV_POS) &
AG903_SPC_PLL2_CTRL_DIV_MSK;
607: val |= (param->frange <<
AG903_SPC_PLL2_CTRL_FR_POS) &
AG903_SPC_PLL2_CTRL_FR_MSK;
608:
if(
true == param->en) {
609: val |= (1 <<
AG903_SPC_PLL2_CTRL_EN_POS);
610: }
611:
AG903_SPC->PLL2_CTRL = val;
612:
613:
return;
614: }
615:
616:
622:
void AG903_SPCPrmGetPll2Ctrl(
AG903_SPCPrmPllnParam* param)
623: {
624: uint32_t val;
625:
626:
ASSERT(NULL != param);
627:
628: val =
AG903_SPC->PLL2_CTRL;
629: param->src = (uint8_t)((val &
AG903_SPC_PLL2_CTRL_SRC_MSK) >>
AG903_SPC_PLL2_CTRL_SRC_POS);
630: param->ns = (uint8_t)((val &
AG903_SPC_PLL2_CTRL_NS_MSK) >>
AG903_SPC_PLL2_CTRL_NS_POS);
631: param->ms = (uint8_t)((val &
AG903_SPC_PLL2_CTRL_MS_MSK) >>
AG903_SPC_PLL2_CTRL_MS_POS);
632: param->div = (uint8_t)((val &
AG903_SPC_PLL2_CTRL_DIV_MSK) >>
AG903_SPC_PLL2_CTRL_DIV_POS);
633: param->frange = (uint8_t)((val &
AG903_SPC_PLL2_CTRL_FR_MSK) >>
AG903_SPC_PLL2_CTRL_FR_POS);
634:
if(
AG903_SPC_PLL2_CTRL_EN_MSK & val) {
635: param->en =
true;
636: }
637:
else {
638: param->en =
false;
639: }
640:
641:
return;
642: }
643:
644:
650:
void AG903_SPCPrmSetPll3Ctrl(
AG903_SPCPrmPllnParam* param)
651: {
652: uint32_t val = 0;
653:
654: val |= (param->src <<
AG903_SPC_PLL3_CTRL_SRC_POS) &
AG903_SPC_PLL3_CTRL_SRC_MSK;
655: val |= (param->ns <<
AG903_SPC_PLL3_CTRL_NS_POS) &
AG903_SPC_PLL3_CTRL_NS_MSK;
656: val |= (param->ms <<
AG903_SPC_PLL3_CTRL_MS_POS) &
AG903_SPC_PLL3_CTRL_MS_MSK;
657: val |= (param->div <<
AG903_SPC_PLL3_CTRL_DIV_POS) &
AG903_SPC_PLL3_CTRL_DIV_MSK;
658: val |= (param->frange <<
AG903_SPC_PLL3_CTRL_FR_POS) &
AG903_SPC_PLL3_CTRL_FR_MSK;
659:
if(
true == param->en) {
660: val |= (1 <<
AG903_SPC_PLL3_CTRL_EN_POS);
661: }
662:
AG903_SPC->PLL3_CTRL = val;
663:
664:
return;
665: }
666:
667:
673:
void AG903_SPCPrmGetPll3Ctrl(
AG903_SPCPrmPllnParam* param)
674: {
675: uint32_t val;
676:
677:
ASSERT(NULL != param);
678:
679: val =
AG903_SPC->PLL3_CTRL;
680: param->src = (uint8_t)((val &
AG903_SPC_PLL3_CTRL_SRC_MSK) >>
AG903_SPC_PLL3_CTRL_SRC_POS);
681: param->ns = (uint8_t)((val &
AG903_SPC_PLL3_CTRL_NS_MSK) >>
AG903_SPC_PLL3_CTRL_NS_POS);
682: param->ms = (uint8_t)((val &
AG903_SPC_PLL3_CTRL_MS_MSK) >>
AG903_SPC_PLL3_CTRL_MS_POS);
683: param->div = (uint8_t)((val &
AG903_SPC_PLL3_CTRL_DIV_MSK) >>
AG903_SPC_PLL3_CTRL_DIV_POS);
684: param->frange = (uint8_t)((val &
AG903_SPC_PLL3_CTRL_FR_MSK) >>
AG903_SPC_PLL3_CTRL_FR_POS);
685:
if(
AG903_SPC_PLL3_CTRL_EN_MSK & val) {
686: param->en =
true;
687: }
688:
else {
689: param->en =
false;
690: }
691:
692:
return;
693: }
694:
695:
701:
void AG903_SPCPrmSetPllACtrl(
AG903_SPCPrmPllaParam* param)
702: {
703: uint32_t val = 0;
704:
705: val |= (param->src <<
AG903_SPC_PLLA_CTRL_SRC_POS) &
AG903_SPC_PLLA_CTRL_SRC_MSK;
706: val |= (param->ns <<
AG903_SPC_PLLA_CTRL_NS_POS) &
AG903_SPC_PLLA_CTRL_NS_MSK;
707: val |= (param->ms <<
AG903_SPC_PLLA_CTRL_MS_POS) &
AG903_SPC_PLLA_CTRL_MS_MSK;
708: val |= (param->fr <<
AG903_SPC_PLLA_CTRL_FR_POS) &
AG903_SPC_PLLA_CTRL_FR_MSK;
709: val |= (param->div <<
AG903_SPC_PLLA_CTRL_DIV_POS) &
AG903_SPC_PLLA_CTRL_DIV_MSK;
710: val |= (param->cc <<
AG903_SPC_PLLA_CTRL_CC_POS) &
AG903_SPC_PLLA_CTRL_CC_MSK;
711:
if(
true == param->en) {
712: val |= (1 <<
AG903_SPC_PLLA_CTRL_EN_POS);
713: }
714:
AG903_SPC->PLLA_CTRL = val;
715:
716:
return;
717: }
718:
719:
725:
void AG903_SPCPrmGetPllACtrl(
AG903_SPCPrmPllaParam* param)
726: {
727: uint32_t val;
728:
729:
ASSERT(NULL != param);
730:
731: val =
AG903_SPC->PLLA_CTRL;
732: param->src = (uint8_t)((val &
AG903_SPC_PLLA_CTRL_SRC_MSK) >>
AG903_SPC_PLLA_CTRL_SRC_POS);
733: param->ns = (uint8_t)((val &
AG903_SPC_PLLA_CTRL_NS_MSK) >>
AG903_SPC_PLLA_CTRL_NS_POS);
734: param->ms = (uint8_t)((val &
AG903_SPC_PLLA_CTRL_MS_MSK) >>
AG903_SPC_PLLA_CTRL_MS_POS);
735: param->div = (uint8_t)((val &
AG903_SPC_PLLA_CTRL_DIV_MSK) >>
AG903_SPC_PLLA_CTRL_DIV_POS);
736: param->fr = (uint8_t)((val &
AG903_SPC_PLLA_CTRL_FR_MSK) >>
AG903_SPC_PLLA_CTRL_FR_POS);
737: param->cc = (uint8_t)((val &
AG903_SPC_PLLA_CTRL_CC_MSK) >>
AG903_SPC_PLLA_CTRL_CC_POS);
738:
if(
AG903_SPC_PLLA_CTRL_EN_MSK & val) {
739: param->en =
true;
740: }
741:
else {
742: param->en =
false;
743: }
744:
745:
return;
746: }
747:
748:
755:
void AG903_SPCPrmSetSwResetMask(uint8_t reg_no, uint32_t msk)
756: {
757:
ASSERT(0 != reg_no);
758:
ASSERT(
AG903_SPC_SWRSTMSK_REG_NUM >= reg_no);
759:
760:
switch(reg_no) {
761:
case 1:
762:
AG903_SPC->SOFTRESET_MASK1 = msk;
763:
break;
764:
case 2:
765:
AG903_SPC->SOFTRESET_MASK2 = msk;
766:
break;
767:
case 3:
768:
AG903_SPC->SOFTRESET_MASK3 = msk;
769:
break;
770:
case 4:
771:
AG903_SPC->SOFTRESET_MASK4 = msk;
772:
break;
773:
case 5:
774:
AG903_SPC->SOFTRESET_MASK5 = msk;
775:
break;
776:
default:
777:
778:
break;
779: }
780:
781:
return;
782: }
783:
784:
791:
void AG903_SPCPrmGetSwResetMask(uint8_t reg_no, uint32_t* msk)
792: {
793:
ASSERT(NULL != msk);
794:
ASSERT(0 != reg_no);
795:
ASSERT(
AG903_SPC_SWRSTMSK_REG_NUM >= reg_no);
796:
797:
switch(reg_no) {
798:
case 1:
799: (*msk) =
AG903_SPC->SOFTRESET_MASK1;
800:
break;
801:
case 2:
802: (*msk) =
AG903_SPC->SOFTRESET_MASK2;
803:
break;
804:
case 3:
805: (*msk) =
AG903_SPC->SOFTRESET_MASK3;
806:
break;
807:
case 4:
808: (*msk) =
AG903_SPC->SOFTRESET_MASK4;
809:
break;
810:
case 5:
811: (*msk) =
AG903_SPC->SOFTRESET_MASK5;
812:
break;
813:
default:
814:
815:
break;
816: }
817:
818:
return;
819: }
820:
821:
828:
void AG903_SPCPrmSetApbSdmcClkCtrl(uint8_t sdmclk, uint32_t pclk)
829: {
830: uint32_t val = 0;
831:
832: val |= (sdmclk <<
AG903_SPC_APB_SDMC_CLK_CTRL_SDMCCLK_EN_POS) &
AG903_SPC_APB_SDMC_CLK_CTRL_SDMCCLK_EN_MSK;
833: val |= (pclk <<
AG903_SPC_APB_SDMC_CLK_CTRL_PCLK_EN_POS) &
AG903_SPC_APB_SDMC_CLK_CTRL_PCLK_EN_MSK;
834:
AG903_SPC->APB_SDMC_CLK_CTRL = val;
835:
836:
return;
837: }
838:
839:
846:
void AG903_SPCPrmGetApbSdmcClkCtrl(uint8_t* sdmclk, uint32_t* pclk)
847: {
848: uint32_t val;
849:
850:
ASSERT(NULL != sdmclk);
851:
ASSERT(NULL != pclk);
852:
853: val =
AG903_SPC->APB_SDMC_CLK_CTRL;
854: (*sdmclk) = (uint8_t)((val &
AG903_SPC_APB_SDMC_CLK_CTRL_SDMCCLK_EN_MSK) >>
AG903_SPC_APB_SDMC_CLK_CTRL_SDMCCLK_EN_POS);
855: (*pclk) = (val &
AG903_SPC_APB_SDMC_CLK_CTRL_PCLK_EN_MSK) >>
AG903_SPC_APB_SDMC_CLK_CTRL_PCLK_EN_POS;
856:
857:
return;
858: }
859:
860:
866:
void AG903_SPCPrmSetMiscClkCtrl(uint32_t sclk)
867: {
868:
AG903_SPC->MISC_CLK_CTRL = sclk;
869:
return;
870: }
871:
872:
878:
void AG903_SPCPrmGetMiscClkCtrl(uint32_t* sclk)
879: {
880:
ASSERT(NULL != sclk);
881: (*sclk) =
AG903_SPC->MISC_CLK_CTRL;
882:
return;
883: }
884:
885:
892:
void AG903_SPCPrmGetPinStatus(uint8_t* test, uint8_t* mode)
893: {
894: uint32_t val;
895:
896:
ASSERT(NULL != test);
897:
ASSERT(NULL != mode);
898:
899: val =
AG903_SPC->PIN_STATUS;
900: (*test) = (uint8_t)((val &
AG903_SPC_PIN_STATUS_TEST_MSK) >>
AG903_SPC_PIN_STATUS_TEST_POS);
901: (*mode) = (uint8_t)((val &
AG903_SPC_PIN_STATUS_MODE_MSK) >>
AG903_SPC_PIN_STATUS_MODE_POS);
902:
return;
903: }
904:
905:
912:
void AG903_SPCPrmSetSdmcMiscCtrl(
AG903_SPCPrmSdmcMiscParam* param)
913: {
914: uint32_t val = 0;
915:
916:
ASSERT(NULL != param);
917:
918: val |= (param->hclk_sel <<
AG903_SPC_SDMC_MISC_CTRL_HCLK_SEL_POS) &
AG903_SPC_SDMC_MISC_CTRL_HCLK_SEL_MSK;
919: val |= (param->rclk_sel <<
AG903_SPC_SDMC_MISC_CTRL_RCLK_SEL_POS) &
AG903_SPC_SDMC_MISC_CTRL_RCLK_SEL_MSK;
920: val |= (param->wclk_sel <<
AG903_SPC_SDMC_MISC_CTRL_WCLK_SEL_POS) &
AG903_SPC_SDMC_MISC_CTRL_WCLK_SEL_MSK;
921: val |= (param->sref_req <<
AG903_SPC_SDMC_MISC_CTRL_SREF_REQ_POS) &
AG903_SPC_SDMC_MISC_CTRL_SREF_REQ_MSK;
922: val |= (param->sref_ack <<
AG903_SPC_SDMC_MISC_CTRL_SREF_ACK_POS) &
AG903_SPC_SDMC_MISC_CTRL_SREF_ACK_MSK;
923: val |= (param->clk_sel <<
AG903_SPC_SDMC_MISC_CTRL_CLK_SEL_POS) &
AG903_SPC_SDMC_MISC_CTRL_CLK_SEL_MSK;
924:
AG903_SPC->SDMC_MISC_CTRL = val;
925:
926:
return;
927: }
928:
929:
935:
void AG903_SPCPrmGetSdmcMiscCtrl(
AG903_SPCPrmSdmcMiscParam* param)
936: {
937: uint32_t val;
938:
939:
ASSERT(NULL != param);
940:
941: val =
AG903_SPC->SDMC_MISC_CTRL;
942: param->hclk_sel = (uint8_t)((val &
AG903_SPC_SDMC_MISC_CTRL_HCLK_SEL_MSK) >>
AG903_SPC_SDMC_MISC_CTRL_HCLK_SEL_POS);
943: param->rclk_sel = (uint8_t)((val &
AG903_SPC_SDMC_MISC_CTRL_RCLK_SEL_MSK) >>
AG903_SPC_SDMC_MISC_CTRL_RCLK_SEL_POS);
944: param->wclk_sel = (uint8_t)((val &
AG903_SPC_SDMC_MISC_CTRL_WCLK_SEL_MSK) >>
AG903_SPC_SDMC_MISC_CTRL_WCLK_SEL_POS);
945: param->sref_ack = (uint8_t)((val &
AG903_SPC_SDMC_MISC_CTRL_SREF_ACK_MSK) >>
AG903_SPC_SDMC_MISC_CTRL_SREF_ACK_POS);
946: param->sref_req = (uint8_t)((val &
AG903_SPC_SDMC_MISC_CTRL_SREF_REQ_MSK) >>
AG903_SPC_SDMC_MISC_CTRL_SREF_REQ_POS);
947: param->clk_sel = (uint8_t)((val &
AG903_SPC_SDMC_MISC_CTRL_CLK_SEL_MSK) >>
AG903_SPC_SDMC_MISC_CTRL_CLK_SEL_POS);
948:
949:
return;
950: }
951:
952:
958:
void AG903_SPCPrmSetDdrMiscCtrl(uint8_t refresh)
959: {
960: uint32_t val;
961:
962: val =
AG903_SPC->DDR_MISC_CTRL;
963:
if(
true == refresh) {
964: val |= (1 <<
AG903_SPC_DDR_MISC_CTRL_REFRESH_POS);
965: }
966:
AG903_SPC->DDR_MISC_CTRL = val;
967:
968:
return;
969: }
970:
971:
978:
void AG903_SPCPrmGetDdrMiscCtrl(uint8_t* init, uint8_t* refresh)
979: {
980: uint32_t val;
981:
982:
ASSERT(NULL != init);
983:
ASSERT(NULL != refresh);
984:
985: val =
AG903_SPC->DDR_MISC_CTRL;
986:
if(
AG903_SPC_DDR_MISC_CTRL_INIT_OK_MSK & val) {
987: (*init) =
true;
988: }
989:
else {
990: (*init) =
false;
991: }
992:
if(
AG903_SPC_DDR_MISC_CTRL_REFRESH_MSK & val) {
993: (*refresh) =
true;
994: }
995:
else {
996: (*refresh) =
false;
997: }
998:
999:
return;
1000: }
1001:
1002:
1008:
void AG903_SPCPrmSetSpiromMiscCtrl(uint8_t addr_cyc)
1009: {
1010:
AG903_SPC->SPIROM_MISC_CTRL = (addr_cyc <<
AG903_SPC_SPIROM_MISC_CTRL_ADDR_CYC_POS) &
AG903_SPC_SPIROM_MISC_CTRL_ADDR_CYC_MSK;
1011:
return;
1012: }
1013:
1014:
1020:
void AG903_SPCPrmGetSpiromMiscCtrl(uint8_t* addr_cyc)
1021: {
1022: uint32_t val;
1023:
1024:
ASSERT(NULL != addr_cyc);
1025:
1026: val =
AG903_SPC->SPIROM_MISC_CTRL;
1027: (*addr_cyc) = (uint8_t)((val &
AG903_SPC_SPIROM_MISC_CTRL_ADDR_CYC_MSK) >>
AG903_SPC_SPIROM_MISC_CTRL_ADDR_CYC_POS);
1028:
1029:
return;
1030: }
1031:
1032:
1038:
void AG903_SPCPrmSetClkSrc(
AG903_SPCPrmClkSel* clk_src)
1039: {
1040: uint32_t val = 0;
1041:
1042:
ASSERT(NULL != clk_src);
1043:
1044: val |= (clk_src->cp1 <<
AG903_SPC_CLK_SEL1_CP1CLK_SEL_POS) &
AG903_SPC_CLK_SEL1_CP1CLK_SEL_MSK;
1045: val |= (clk_src->cp0 <<
AG903_SPC_CLK_SEL1_CP0CLK_SEL_POS) &
AG903_SPC_CLK_SEL1_CP0CLK_SEL_MSK;
1046: val |= (clk_src->lvds <<
AG903_SPC_CLK_SEL1_LVDSCLK_SEL_POS) &
AG903_SPC_CLK_SEL1_LVDSCLK_SEL_MSK;
1047: val |= (clk_src->dt1 <<
AG903_SPC_CLK_SEL1_DT1CLK_SEL_POS) &
AG903_SPC_CLK_SEL1_DT1CLK_SEL_MSK;
1048: val |= (clk_src->dt0 <<
AG903_SPC_CLK_SEL1_DT0CLK_SEL_POS) &
AG903_SPC_CLK_SEL1_DT0CLK_SEL_MSK;
1049: val |= (clk_src->hda <<
AG903_SPC_CLK_SEL1_HDACLK_SEL_POS) &
AG903_SPC_CLK_SEL1_HDACLK_SEL_MSK;
1050:
AG903_SPC->CLK_SEL1 = val;
1051:
1052:
return;
1053: }
1054:
1055:
1061:
void AG903_SPCPrmGetClkSrc(
AG903_SPCPrmClkSel* clk_src)
1062: {
1063: uint32_t val;
1064:
1065:
ASSERT(NULL != clk_src);
1066:
1067: val =
AG903_SPC->CLK_SEL1;
1068: clk_src->cp1 = (uint8_t)((val &
AG903_SPC_CLK_SEL1_CP1CLK_SEL_MSK) >>
AG903_SPC_CLK_SEL1_CP1CLK_SEL_POS);
1069: clk_src->cp0 = (uint8_t)((val &
AG903_SPC_CLK_SEL1_CP0CLK_SEL_MSK) >>
AG903_SPC_CLK_SEL1_CP0CLK_SEL_POS);
1070: clk_src->lvds = (uint8_t)((val &
AG903_SPC_CLK_SEL1_LVDSCLK_SEL_MSK) >>
AG903_SPC_CLK_SEL1_LVDSCLK_SEL_POS);
1071: clk_src->dt1 = (uint8_t)((val &
AG903_SPC_CLK_SEL1_DT1CLK_SEL_MSK) >>
AG903_SPC_CLK_SEL1_DT1CLK_SEL_POS);
1072: clk_src->dt0 = (uint8_t)((val &
AG903_SPC_CLK_SEL1_DT0CLK_SEL_MSK) >>
AG903_SPC_CLK_SEL1_DT0CLK_SEL_POS);
1073: clk_src->hda = (uint8_t)((val &
AG903_SPC_CLK_SEL1_HDACLK_SEL_MSK) >>
AG903_SPC_CLK_SEL1_HDACLK_SEL_POS);
1074:
1075:
return;
1076: }
1077:
1078:
1084:
void AG903_SPCPrmSetSspClkSrc(
AG903_SPCPrmSspClkSel* clk_src)
1085: {
1086: uint32_t val = 0;
1087:
1088:
ASSERT(NULL != clk_src);
1089:
1090: val |= (clk_src->pll3 <<
AG903_SPC_CLK_SSP_SEL_PLL3CLK_SEL_POS) &
AG903_SPC_CLK_SSP_SEL_PLL3CLK_SEL_MSK;
1091: val |= (clk_src->ssp3 <<
AG903_SPC_CLK_SSP_SEL_SSP3CLK_SEL_POS) &
AG903_SPC_CLK_SSP_SEL_SSP3CLK_SEL_MSK;
1092: val |= (clk_src->ssp2 <<
AG903_SPC_CLK_SSP_SEL_SSP2CLK_SEL_POS) &
AG903_SPC_CLK_SSP_SEL_SSP2CLK_SEL_MSK;
1093: val |= (clk_src->ssp1 <<
AG903_SPC_CLK_SSP_SEL_SSP1CLK_SEL_POS) &
AG903_SPC_CLK_SSP_SEL_SSP1CLK_SEL_MSK;
1094: val |= (clk_src->ssp0 <<
AG903_SPC_CLK_SSP_SEL_SSP0CLK_SEL_POS) &
AG903_SPC_CLK_SSP_SEL_SSP0CLK_SEL_MSK;
1095:
AG903_SPC->CLK_SSP_SEL = val;
1096:
1097:
return;
1098: }
1099:
1100:
1106:
void AG903_SPCPrmGetSspClkSrc(
AG903_SPCPrmSspClkSel* clk_src)
1107: {
1108: uint32_t val;
1109:
1110:
ASSERT(NULL != clk_src);
1111:
1112: val =
AG903_SPC->CLK_SSP_SEL;
1113: clk_src->pll3 = (uint8_t)((val &
AG903_SPC_CLK_SSP_SEL_PLL3CLK_SEL_MSK) >>
AG903_SPC_CLK_SSP_SEL_PLL3CLK_SEL_POS);
1114: clk_src->ssp3 = (uint8_t)((val &
AG903_SPC_CLK_SSP_SEL_SSP3CLK_SEL_MSK) >>
AG903_SPC_CLK_SSP_SEL_SSP3CLK_SEL_POS);
1115: clk_src->ssp2 = (uint8_t)((val &
AG903_SPC_CLK_SSP_SEL_SSP2CLK_SEL_MSK) >>
AG903_SPC_CLK_SSP_SEL_SSP2CLK_SEL_POS);
1116: clk_src->ssp1 = (uint8_t)((val &
AG903_SPC_CLK_SSP_SEL_SSP1CLK_SEL_MSK) >>
AG903_SPC_CLK_SSP_SEL_SSP1CLK_SEL_POS);
1117: clk_src->ssp0 = (uint8_t)((val &
AG903_SPC_CLK_SSP_SEL_SSP0CLK_SEL_MSK) >>
AG903_SPC_CLK_SSP_SEL_SSP0CLK_SEL_POS);
1118:
return;
1119: }
1120:
1121:
1127:
void AG903_SPCPrmSetSspClkDiv(
AG903_SPCPrmSspClkDiv* clk_div)
1128: {
1129: uint32_t val = 0;
1130:
1131:
ASSERT(NULL != clk_div);
1132:
1133: val |= (clk_div->ssp3 <<
AG903_SPC_CLK_SSP_DIV_SSP3CLK_DIV_POS) &
AG903_SPC_CLK_SSP_DIV_SSP3CLK_DIV_MSK;
1134: val |= (clk_div->ssp2 <<
AG903_SPC_CLK_SSP_DIV_SSP2CLK_DIV_POS) &
AG903_SPC_CLK_SSP_DIV_SSP2CLK_DIV_MSK;
1135: val |= (clk_div->ssp1 <<
AG903_SPC_CLK_SSP_DIV_SSP1CLK_DIV_POS) &
AG903_SPC_CLK_SSP_DIV_SSP1CLK_DIV_MSK;
1136: val |= (clk_div->ssp0 <<
AG903_SPC_CLK_SSP_DIV_SSP0CLK_DIV_POS) &
AG903_SPC_CLK_SSP_DIV_SSP0CLK_DIV_MSK;
1137:
AG903_SPC->CLK_SSP_DIV = val;
1138:
1139:
return;
1140: }
1141:
1142:
1148:
void AG903_SPCPrmGetSspClkDiv(
AG903_SPCPrmSspClkDiv* clk_div)
1149: {
1150: uint32_t val;
1151:
1152:
ASSERT(NULL != clk_div);
1153:
1154: val =
AG903_SPC->CLK_SSP_DIV;
1155: clk_div->ssp3 = (uint8_t)((val &
AG903_SPC_CLK_SSP_DIV_SSP3CLK_DIV_MSK) >>
AG903_SPC_CLK_SSP_DIV_SSP3CLK_DIV_POS);
1156: clk_div->ssp2 = (uint8_t)((val &
AG903_SPC_CLK_SSP_DIV_SSP2CLK_DIV_MSK) >>
AG903_SPC_CLK_SSP_DIV_SSP2CLK_DIV_POS);
1157: clk_div->ssp1 = (uint8_t)((val &
AG903_SPC_CLK_SSP_DIV_SSP1CLK_DIV_MSK) >>
AG903_SPC_CLK_SSP_DIV_SSP1CLK_DIV_POS);
1158: clk_div->ssp0 = (uint8_t)((val &
AG903_SPC_CLK_SSP_DIV_SSP0CLK_DIV_MSK) >>
AG903_SPC_CLK_SSP_DIV_SSP0CLK_DIV_POS);
1159:
1160:
return;
1161: }
1162:
1163:
1169:
void AG903_SPCPrmSetEtherPhy(uint8_t phy)
1170: {
1171: uint32_t val = 0;
1172:
1173:
if(
AG903_SPC_ETHER_RMII == phy) {
1174: val |= (1 <<
AG903_SPC_ETH_PHY_SEL_RMII_POS);
1175: }
1176:
AG903_SPC->ETH_PHY_SEL = val;
1177:
1178:
return;
1179: }
1180:
1181:
1187:
void AG903_SPCPrmGetEtherPhy(uint8_t* phy)
1188: {
1189: uint32_t val;
1190:
1191:
ASSERT(NULL != phy);
1192:
1193: val =
AG903_SPC->ETH_PHY_SEL;
1194:
if(
AG903_SPC_ETH_PHY_SEL_RMII_MSK & val) {
1195: (*phy) =
AG903_SPC_ETHER_RMII;
1196: }
1197:
else {
1198: (*phy) =
AG903_SPC_ETHER_MII;
1199: }
1200:
return;
1201: }
1202:
1203:
1212:
void AG903_SPCPrmSetCpuMiscCtrl(uint8_t reg_no, uint32_t val)
1213: {
1214:
ASSERT(0 != reg_no);
1215:
ASSERT(
AG903_SPC_CA5CTRL_REG_NUM >= reg_no);
1216:
1217:
switch(reg_no) {
1218:
case 1:
1219:
AG903_SPC->CA5_MISC_CTRL1 = val;
1220:
break;
1221:
case 2:
1222:
AG903_SPC->CA5_MISC_CTRL2 = val;
1223:
break;
1224:
case 3:
1225:
AG903_SPC->CA5_MISC_CTRL3 = val;
1226:
break;
1227:
case 4:
1228:
AG903_SPC->CA5_MISC_CTRL4 = val;
1229:
break;
1230:
case 5:
1231:
AG903_SPC->CA5_MISC_CTRL5 = val;
1232:
break;
1233:
case 6:
1234:
AG903_SPC->CA5_MISC_CTRL6 = val;
1235:
break;
1236:
case 7:
1237:
AG903_SPC->CA5_MISC_CTRL7 = val;
1238:
break;
1239:
case 8:
1240:
AG903_SPC->CA5_MISC_CTRL8 = val;
1241:
break;
1242:
case 9:
1243:
AG903_SPC->CA5_MISC_CTRL9 = val;
1244:
break;
1245:
case 10:
1246:
AG903_SPC->CA5_MISC_CTRL10 = val;
1247:
break;
1248:
case 11:
1249:
AG903_SPC->CA5_MISC_CTRL11 = val;
1250:
break;
1251:
default:
1252:
1253:
break;
1254: }
1255:
1256:
return;
1257: }
1258:
1259:
1268:
void AG903_SPCPrmGetCpuMiscCtrl(uint8_t reg_no, uint32_t* val)
1269: {
1270:
ASSERT(NULL != val);
1271:
ASSERT(0 != reg_no);
1272:
ASSERT(
AG903_SPC_CA5CTRL_REG_NUM >= reg_no);
1273:
1274:
switch(reg_no) {
1275:
case 1:
1276: (*val) =
AG903_SPC->CA5_MISC_CTRL1;
1277:
break;
1278:
case 2:
1279: (*val) =
AG903_SPC->CA5_MISC_CTRL2;
1280:
break;
1281:
case 3:
1282: (*val) =
AG903_SPC->CA5_MISC_CTRL3;
1283:
break;
1284:
case 4:
1285: (*val) =
AG903_SPC->CA5_MISC_CTRL4;
1286:
break;
1287:
case 5:
1288: (*val) =
AG903_SPC->CA5_MISC_CTRL5;
1289:
break;
1290:
case 6:
1291: (*val) =
AG903_SPC->CA5_MISC_CTRL6;
1292:
break;
1293:
case 7:
1294: (*val) =
AG903_SPC->CA5_MISC_CTRL7;
1295:
break;
1296:
case 8:
1297: (*val) =
AG903_SPC->CA5_MISC_CTRL8;
1298:
break;
1299:
case 9:
1300: (*val) =
AG903_SPC->CA5_MISC_CTRL9;
1301:
break;
1302:
case 10:
1303: (*val) =
AG903_SPC->CA5_MISC_CTRL10;
1304:
break;
1305:
case 11:
1306: (*val) =
AG903_SPC->CA5_MISC_CTRL11;
1307:
break;
1308:
default:
1309:
1310:
break;
1311: }
1312:
1313:
return;
1314: }
1315:
1316:
1323:
void AG903_SPCPrmSetVideoAdcCtrl(
AG903_SPCPrmVideoAdcParam* param,
AG903_SPCPrmVideoAdcEnable* enable)
1324: {
1325: uint32_t val;
1326:
1327:
ASSERT(NULL != param);
1328:
ASSERT(NULL != enable);
1329:
1330: val =
AG903_SPC->VIDEOADC_MISC_CTRL5;
1331: val &= ~(
AG903_SPC_VIDEOADC_MISC_CTRL5_INPUT_RANGE_MSK |
1332:
AG903_SPC_VIDEOADC_MISC_CTRL5_REF_BIAS_UP_MSK);
1333: val |= (param->input_range <<
AG903_SPC_VIDEOADC_MISC_CTRL5_INPUT_RANGE_POS) &
1334:
AG903_SPC_VIDEOADC_MISC_CTRL5_INPUT_RANGE_MSK;
1335: val |= (param->ref_bias_up <<
AG903_SPC_VIDEOADC_MISC_CTRL5_REF_BIAS_UP_POS) &
1336:
AG903_SPC_VIDEOADC_MISC_CTRL5_REF_BIAS_UP_MSK;
1337:
AG903_SPC->VIDEOADC_MISC_CTRL5 = val;
1338:
1339: val =
AG903_SPC->VIDEOADC_MISC_CTRL4;
1340: val &= ~(
AG903_SPC_VIDEOADC_MISC_CTRL4_AAF_CTRL_MSK |
1341:
AG903_SPC_VIDEOADC_MISC_CTRL4_QUAN_BIAS_UP_MSK |
1342:
AG903_SPC_VIDEOADC_MISC_CTRL4_CH3_GAIN_MSK);
1343: val |= (param->aaf_ctrl <<
AG903_SPC_VIDEOADC_MISC_CTRL4_AAF_CTRL_POS) &
1344:
AG903_SPC_VIDEOADC_MISC_CTRL4_AAF_CTRL_MSK;
1345: val |= (param->qntzr_bias_up <<
AG903_SPC_VIDEOADC_MISC_CTRL4_QUAN_BIAS_UP_POS) &
1346:
AG903_SPC_VIDEOADC_MISC_CTRL4_QUAN_BIAS_UP_MSK;
1347: val |= (param->gain3 <<
AG903_SPC_VIDEOADC_MISC_CTRL4_CH3_GAIN_POS) &
1348:
AG903_SPC_VIDEOADC_MISC_CTRL4_CH3_GAIN_MSK;
1349:
AG903_SPC->VIDEOADC_MISC_CTRL4 = val;
1350:
1351: val =
AG903_SPC->VIDEOADC_MISC_CTRL3;
1352: val &= ~(
AG903_SPC_VIDEOADC_MISC_CTRL3_CH2_GAIN_MSK |
1353:
AG903_SPC_VIDEOADC_MISC_CTRL3_CH1_GAIN_MSK |
1354:
AG903_SPC_VIDEOADC_MISC_CTRL3_CH0_GAIN_MSK |
1355:
AG903_SPC_VIDEOADC_MISC_CTRL3_CH3_CLAMP_MSK);
1356: val |= (param->gain2 <<
AG903_SPC_VIDEOADC_MISC_CTRL3_CH2_GAIN_POS) &
1357:
AG903_SPC_VIDEOADC_MISC_CTRL3_CH2_GAIN_MSK;
1358: val |= (param->gain1 <<
AG903_SPC_VIDEOADC_MISC_CTRL3_CH1_GAIN_POS) &
1359:
AG903_SPC_VIDEOADC_MISC_CTRL3_CH1_GAIN_MSK;
1360: val |= (param->gain0 <<
AG903_SPC_VIDEOADC_MISC_CTRL3_CH0_GAIN_POS) &
1361:
AG903_SPC_VIDEOADC_MISC_CTRL3_CH0_GAIN_MSK;
1362: val |= (param->clmp_lv3 <<
AG903_SPC_VIDEOADC_MISC_CTRL3_CH3_CLAMP_POS) &
1363:
AG903_SPC_VIDEOADC_MISC_CTRL3_CH3_CLAMP_MSK;
1364:
AG903_SPC->VIDEOADC_MISC_CTRL3 = val;
1365:
1366: val = 0;
1367: val |= (param->clmp_lv2 <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_CLAMP_POS) &
1368:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_CLAMP_MSK;
1369: val |= (param->clmp_lv1 <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_CLAMP_POS) &
1370:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_CLAMP_MSK;
1371: val |= (param->clmp_lv0 <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_CLAMP_POS) &
1372:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_CLAMP_MSK;
1373: val |= (param->clmp_imp <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CLAMP_IMP_POS) &
1374:
AG903_SPC_VIDEOADC_MISC_CTRL2_CLAMP_IMP_MSK;
1375: val |= (enable->ch3 <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH3_ENABLE_POS) &
1376:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH3_ENABLE_MSK;
1377: val |= (enable->ch2 <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_ENABLE_POS) &
1378:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_ENABLE_MSK;
1379: val |= (enable->ch1 <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_ENABLE_POS) &
1380:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_ENABLE_MSK;
1381: val |= (enable->ch0 <<
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_ENABLE_POS) &
1382:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_ENABLE_MSK;
1383:
AG903_SPC->VIDEOADC_MISC_CTRL2 = val;
1384:
1385: val = 0;
1386: val |= (param->clmp_en3 <<
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN3_POS) &
1387:
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN3_MSK;
1388: val |= (param->clmp_en2 <<
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN2_POS) &
1389:
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN2_MSK;
1390: val |= (param->clmp_en1 <<
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN1_POS) &
1391:
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN1_MSK;
1392: val |= (param->clmp_en0 <<
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN0_POS) &
1393:
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN0_MSK;
1394: val |= (enable->adc <<
AG903_SPC_VIDEOADC_MISC_CTRL1_ENABLE_POS) &
1395:
AG903_SPC_VIDEOADC_MISC_CTRL1_ENABLE_MSK;
1396:
AG903_SPC->VIDEOADC_MISC_CTRL1 = val;
1397:
1398:
return;
1399: }
1400:
1401:
1408:
void AG903_SPCPrmGetVideoAdcCtrl(
AG903_SPCPrmVideoAdcParam* param,
AG903_SPCPrmVideoAdcEnable* enable)
1409: {
1410: uint32_t val;
1411:
1412:
ASSERT(NULL != param);
1413:
ASSERT(NULL != enable);
1414:
1415: val =
AG903_SPC->VIDEOADC_MISC_CTRL5;
1416: param->input_range = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL5_INPUT_RANGE_MSK) >>
1417:
AG903_SPC_VIDEOADC_MISC_CTRL5_INPUT_RANGE_POS);
1418: param->ref_bias_up = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL5_REF_BIAS_UP_MSK) >>
1419:
AG903_SPC_VIDEOADC_MISC_CTRL5_REF_BIAS_UP_POS);
1420:
1421: val =
AG903_SPC->VIDEOADC_MISC_CTRL4;
1422: param->aaf_ctrl = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL4_AAF_CTRL_MSK) >>
1423:
AG903_SPC_VIDEOADC_MISC_CTRL4_AAF_CTRL_POS);
1424: param->qntzr_bias_up = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL4_QUAN_BIAS_UP_MSK) >>
1425:
AG903_SPC_VIDEOADC_MISC_CTRL4_QUAN_BIAS_UP_POS);
1426: param->gain3 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL4_CH3_GAIN_MSK) >>
1427:
AG903_SPC_VIDEOADC_MISC_CTRL4_CH3_GAIN_POS);
1428:
1429: val =
AG903_SPC->VIDEOADC_MISC_CTRL3;
1430: param->gain2 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL3_CH2_GAIN_MSK) >>
1431:
AG903_SPC_VIDEOADC_MISC_CTRL3_CH2_GAIN_POS);
1432: param->gain1 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL3_CH1_GAIN_MSK) >>
1433:
AG903_SPC_VIDEOADC_MISC_CTRL3_CH1_GAIN_POS);
1434: param->gain0 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL3_CH0_GAIN_MSK) >>
1435:
AG903_SPC_VIDEOADC_MISC_CTRL3_CH0_GAIN_POS);
1436: param->clmp_lv3 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL3_CH3_CLAMP_MSK) >>
1437:
AG903_SPC_VIDEOADC_MISC_CTRL3_CH3_CLAMP_POS);
1438:
1439: val =
AG903_SPC->VIDEOADC_MISC_CTRL2;
1440: param->clmp_lv2 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_CLAMP_MSK) >>
1441:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_CLAMP_POS);
1442: param->clmp_lv1 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_CLAMP_MSK) >>
1443:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_CLAMP_POS);
1444: param->clmp_lv0 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_CLAMP_MSK) >>
1445:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_CLAMP_POS);
1446: param->clmp_imp = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL2_CLAMP_IMP_MSK) >>
1447:
AG903_SPC_VIDEOADC_MISC_CTRL2_CLAMP_IMP_POS);
1448: enable->ch3 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL2_CH3_ENABLE_MSK) >>
1449:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH3_ENABLE_POS);
1450: enable->ch2 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_ENABLE_MSK) >>
1451:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH2_ENABLE_POS);
1452: enable->ch1 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_ENABLE_MSK) >>
1453:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH1_ENABLE_POS);
1454: enable->ch0 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_ENABLE_MSK) >>
1455:
AG903_SPC_VIDEOADC_MISC_CTRL2_CH0_ENABLE_POS);
1456:
1457: val =
AG903_SPC->VIDEOADC_MISC_CTRL1;
1458: param->clmp_en3 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN3_MSK) >>
1459:
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN3_POS);
1460: param->clmp_en2 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN2_MSK) >>
1461:
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN2_POS);
1462: param->clmp_en1 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN1_MSK) >>
1463:
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN1_POS);
1464: param->clmp_en0 = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN0_MSK) >>
1465:
AG903_SPC_VIDEOADC_MISC_CTRL1_CLAMP_EN0_POS);
1466: enable->adc = (uint8_t)((val &
AG903_SPC_VIDEOADC_MISC_CTRL1_ENABLE_MSK) >>
1467:
AG903_SPC_VIDEOADC_MISC_CTRL1_ENABLE_POS);
1468:
1469:
return;
1470: }
1471:
1472:
1479:
void AG903_SPCPrmSetLvdsTx(uint8_t rf_ch0, uint8_t rf_ch1)
1480: {
1481: uint32_t val = 0;
1482:
1483: val |= ((rf_ch0 <<
AG903_SPC_LVDS_TX_SETUP_RF_0_POS) &
AG903_SPC_LVDS_TX_SETUP_RF_0_MSK);
1484: val |= ((rf_ch1 <<
AG903_SPC_LVDS_TX_SETUP_RF_1_POS) &
AG903_SPC_LVDS_TX_SETUP_RF_1_MSK);
1485:
AG903_SPC->LVDS_TX_SETUP = val;
1486:
return;
1487: }
1488:
1489:
1496:
void AG903_SPCPrmGetLvdsTx(uint8_t* rf_ch0, uint8_t* rf_ch1)
1497: {
1498: uint32_t val;
1499:
1500:
ASSERT(NULL != rf_ch0);
1501:
ASSERT(NULL != rf_ch1);
1502:
1503: val =
AG903_SPC->LVDS_TX_SETUP;
1504: (*rf_ch0) = (uint8_t)((val &
AG903_SPC_LVDS_TX_SETUP_RF_0_MSK) >>
AG903_SPC_LVDS_TX_SETUP_RF_0_POS);
1505: (*rf_ch1) = (uint8_t)((val &
AG903_SPC_LVDS_TX_SETUP_RF_1_MSK) >>
AG903_SPC_LVDS_TX_SETUP_RF_1_POS);
1506:
return;
1507: }
1508:
1509:
1516:
void AG903_SPCPrmSetUsbMiscCtrl1(uint8_t clk_div, uint8_t clk_sel)
1517: {
1518: uint32_t val;
1519:
1520: val =
AG903_SPC->USB_MISC_CTRL1;
1521:
if(
true == clk_div) {
1522: val |= (1 <<
AG903_SPC_USB_MISC_CTRL1_CLK_DIV_POS);
1523: }
1524:
if(
AG903_SPC_USBCTRL_CLKSEL_XOUT ==clk_sel) {
1525: val |= (1 <<
AG903_SPC_USB_MISC_CTRL1_CLK_SEL_POS);
1526: }
1527:
AG903_SPC->USB_MISC_CTRL1 = val;
1528:
1529:
return;
1530: }
1531:
1532:
1541:
void AG903_SPCPrmGetUsbMiscCtrl1(uint8_t* clk_div, uint8_t* clk_sel, uint8_t* vbus, uint8_t* vprtct)
1542: {
1543: uint32_t val;
1544:
1545:
ASSERT(NULL != clk_div);
1546:
ASSERT(NULL != clk_sel);
1547:
ASSERT(NULL != vbus);
1548:
ASSERT(NULL != vprtct);
1549:
1550: val =
AG903_SPC->USB_MISC_CTRL1;
1551:
if(
AG903_SPC_USB_MISC_CTRL1_CLK_DIV_MSK & val) {
1552: (*clk_div) =
true;
1553: }
1554:
else {
1555: (*clk_div) =
false;
1556: }
1557:
if(
AG903_SPC_USB_MISC_CTRL1_CLK_SEL_MSK & val) {
1558: (*clk_sel) =
AG903_SPC_USBCTRL_CLKSEL_XOUT;
1559: }
1560:
else {
1561: (*clk_sel) =
AG903_SPC_USBCTRL_CLKSEL_MIIRXCLK;
1562: }
1563:
if(
AG903_SPC_USB_MISC_CTRL1_VBUS_outen_MSK & val) {
1564: (*vbus) =
true;
1565: }
1566:
else {
1567: (*vbus) =
false;
1568: }
1569:
if(
AG903_SPC_USB_MISC_CTRL1_VPRTCT_state_MSK & val) {
1570: (*vprtct) =
true;
1571: }
1572:
else {
1573: (*vprtct) =
false;
1574: }
1575:
1576:
return;
1577: }
1578:
1579:
1585:
void AG903_SPCPrmSetUsbMiscCtrl2(
AG903_SPCPrmUsbMiscCtrl* param)
1586: {
1587: uint32_t val = 0;
1588:
1589:
ASSERT(NULL != param);
1590:
1591:
if(
true != param->suspend) {
1592: val |= (1 <<
AG903_SPC_USB_MISC_CTRL2_suspendm_POS);
1593: }
1594:
if(
true == param->wakeup) {
1595: val |= (1 <<
AG903_SPC_USB_MISC_CTRL2_wakeup_POS);
1596: }
1597: val |= (param->squelch <<
AG903_SPC_USB_MISC_CTRL2_TC_TB_TA_POS) &
AG903_SPC_USB_MISC_CTRL2_TC_TB_TA_MSK;
1598:
if(
true == param->pll_aliv) {
1599: val |= (1 <<
AG903_SPC_USB_MISC_CTRL2_PLLALIV_POS);
1600: }
1601:
if(
AG903_SPC_USBCTRL_XTLSEL_30MHZ == param->xtl_sel) {
1602: val |= (1 <<
AG903_SPC_USB_MISC_CTRL2_XTLSEL_POS);
1603: }
1604:
if(
true == param->oscout) {
1605: val |= (1 <<
AG903_SPC_USB_MISC_CTRL2_OSCOUTEN_POS);
1606: }
1607: val |= (1 <<
AG903_SPC_USB_MISC_CTRL2_OUTCLKSEL_POS);
1608:
AG903_SPC->USB_MISC_CTRL2 = val;
1609:
1610:
return;
1611: }
1612:
1613:
1619:
void AG903_SPCPrmGetUsbMiscCtrl2(
AG903_SPCPrmUsbMiscCtrl* param)
1620: {
1621: uint32_t val = 0;
1622:
1623:
ASSERT(NULL != param);
1624:
1625: val =
AG903_SPC->USB_MISC_CTRL2;
1626:
if(
AG903_SPC_USB_MISC_CTRL2_suspendm_MSK & val) {
1627: param->suspend =
false;
1628: }
1629:
else {
1630: param->suspend =
true;
1631: }
1632:
if(
AG903_SPC_USB_MISC_CTRL2_wakeup_MSK & val) {
1633: param->wakeup =
true;
1634: }
1635:
else {
1636: param->wakeup =
false;
1637: }
1638: param->squelch = (uint8_t)((val &
AG903_SPC_USB_MISC_CTRL2_TC_TB_TA_MSK) >>
AG903_SPC_USB_MISC_CTRL2_TC_TB_TA_POS);
1639:
if(
AG903_SPC_USB_MISC_CTRL2_PLLALIV_MSK & val) {
1640: param->pll_aliv =
true;
1641: }
1642:
else {
1643: param->pll_aliv =
false;
1644: }
1645:
if(
AG903_SPC_USB_MISC_CTRL2_XTLSEL_MSK & val) {
1646: param->xtl_sel =
AG903_SPC_USBCTRL_XTLSEL_30MHZ;
1647: }
1648:
else {
1649: param->xtl_sel =
AG903_SPC_USBCTRL_XTLSEL_12MHZ;
1650: }
1651:
if(
AG903_SPC_USB_MISC_CTRL2_OSCOUTEN_MSK & val) {
1652: param->oscout =
true;
1653: }
1654:
else {
1655: param->oscout =
false;
1656: }
1657:
1658:
return;
1659: }
1660:
1661:
1668:
void AG903_SPCPrmSetDdrPhySetup(uint8_t pd_gain, uint8_t afl_gain)
1669: {
1670: uint32_t val;
1671:
1672: val =
AG903_SPC->DDR_PHY_SETUP;
1673: val &= ~(
AG903_SPC_DDR_PHY_SETUP_AFL_GAIN_MSK |
AG903_SPC_DDR_PHY_SETUP_PD_GAIN_MSK);
1674: val |= (pd_gain <<
AG903_SPC_DDR_PHY_SETUP_PD_GAIN_POS) &
AG903_SPC_DDR_PHY_SETUP_PD_GAIN_MSK;
1675: val |= (afl_gain <<
AG903_SPC_DDR_PHY_SETUP_AFL_GAIN_POS) &
AG903_SPC_DDR_PHY_SETUP_AFL_GAIN_MSK;
1676:
AG903_SPC->DDR_PHY_SETUP = val;
1677:
1678:
return;
1679: }
1680:
1681:
1688:
void AG903_SPCPrmGetDdrPhySetup(uint8_t* pd_gain, uint8_t* afl_gain)
1689: {
1690: uint32_t val;
1691:
1692:
ASSERT(NULL != pd_gain);
1693:
ASSERT(NULL != afl_gain);
1694:
1695: val =
AG903_SPC->DDR_PHY_SETUP;
1696: (*pd_gain) = (uint8_t)((val &
AG903_SPC_DDR_PHY_SETUP_PD_GAIN_MSK) >>
AG903_SPC_DDR_PHY_SETUP_PD_GAIN_POS);
1697: (*afl_gain) = (uint8_t)((val &
AG903_SPC_DDR_PHY_SETUP_AFL_GAIN_MSK) >>
AG903_SPC_DDR_PHY_SETUP_AFL_GAIN_POS);
1698:
1699:
return;
1700: }
1701:
1702:
1710:
void AG903_SPCPrmSetBootSwapCtrl(uint8_t swap)
1711: {
1712: uint32_t val = 0;
1713:
1714:
if(
true==swap) {
1715: val |= (1 <<
AG903_SPC_BOOT_SWAP_CTRL_BOOTSWAP_POS);
1716: }
1717:
AG903_SPC->BOOT_SWAP_CTRL = val;
1718:
1719:
return;
1720: }
1721:
1722:
1730:
void AG903_SPCPrmGetBootSwapCtrl(uint8_t* swap)
1731: {
1732: uint32_t val;
1733:
1734:
ASSERT(NULL != swap);
1735:
1736: val =
AG903_SPC->BOOT_SWAP_CTRL;
1737:
if(
AG903_SPC_BOOT_SWAP_CTRL_BOOTSWAP_MSK & val) {
1738: (*swap) =
true;
1739: }
1740:
else {
1741: (*swap) =
false;
1742: }
1743:
return;
1744: }
1745:
1746:
1752:
void AG903_SPCPrmSetIdeClk(uint8_t clk_sel)
1753: {
1754: uint32_t val = 0;
1755:
1756: val |= (clk_sel <<
AG903_SPC_IDE_CLK_SEL_IDECLK_SEL_POS) &
AG903_SPC_IDE_CLK_SEL_IDECLK_SEL_MSK;
1757:
AG903_SPC->IDE_CLK_SEL = val;
1758:
return;
1759: }
1760:
1761:
1767:
void AG903_SPCPrmGetIdeClk(uint8_t* clk_sel)
1768: {
1769: uint32_t val;
1770:
1771:
ASSERT(NULL != clk_sel);
1772:
1773: val =
AG903_SPC->IDE_CLK_SEL;
1774: (*clk_sel) = (uint8_t)((val &
AG903_SPC_IDE_CLK_SEL_IDECLK_SEL_MSK) >>
AG903_SPC_IDE_CLK_SEL_IDECLK_SEL_POS);
1775:
return;
1776: }
1777: