AG903ライブラリリファレンス
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AG903_eqsreg.h
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1: 8: 9: 13: 14:
#ifndef
_AG903_EQS_REGMAP_H_ 15:
#define
_AG903_EQS_REGMAP_H_ 16: 17: 18:
#include
"AG903_regmap.h" 19: 20:
#ifndef
__I
21: 22:
#define
__I
volatile
const
23:
#endif
24:
#ifndef
__O
25: 26:
#define
__O
volatile
27:
#endif
28:
#ifndef
__IO
29: 30:
#define
__IO
volatile
31:
#endif
32: 33: 34:
typedef
struct
{ 35: 36:
union
{ 37:
__IO
uint32_t MOD; 38: 39:
struct
{ 40:
__IO
uint32_t CM : 1; 41: } MOD_bits; 42: }; 43: 44:
union
{ 45:
__IO
uint32_t DIVIDE; 46: 47:
struct
{ 48:
__IO
uint32_t DIV : 16; 49: } DIVIDE_bits; 50: }; 51: 52:
union
{ 53:
__IO
uint32_t WAITCYCLE; 54: 55:
struct
{ 56:
__IO
uint32_t COUNT : 16; 57: } WAITCYCLE_bits; 58: }; 59: 60:
__I
uint32_t RESERVED1[5]; 61: 62:
union
{ 63:
__IO
uint32_t RDFMT0; 64: 65:
struct
{ 66:
__IO
uint32_t CMD : 8; 67:
__IO
uint32_t WW : 2; 68: uint32_t : 6; 69:
__IO
uint32_t AW : 2; 70: uint32_t : 6; 71:
__IO
uint32_t FC : 1; 72: } RDFMT0_bits; 73: }; 74: 75:
union
{ 76:
__IO
uint32_t WRFMT0; 77: 78:
struct
{ 79:
__IO
uint32_t CMD : 8; 80:
__IO
uint32_t WW : 2; 81:
__IO
uint32_t DW : 1; 82: uint32_t : 5; 83:
__IO
uint32_t AW : 2; 84: uint32_t : 6; 85:
__IO
uint32_t FC : 1; 86: } WRFMT0_bits; 87: }; 88: 89:
union
{ 90:
__IO
uint32_t RDFMT1; 91: 92:
struct
{ 93:
__IO
uint32_t CMD : 8; 94:
__IO
uint32_t WW : 2; 95: uint32_t : 6; 96:
__IO
uint32_t AW : 2; 97: uint32_t : 6; 98:
__IO
uint32_t FC : 1; 99: } RDFMT1_bits; 100: }; 101: 102:
union
{ 103:
__IO
uint32_t WRFMT1; 104: 105:
struct
{ 106:
__IO
uint32_t CMD : 8; 107:
__IO
uint32_t WW : 2; 108:
__IO
uint32_t DW : 1; 109: uint32_t : 5; 110:
__IO
uint32_t AW : 2; 111: uint32_t : 6; 112:
__IO
uint32_t FC : 1; 113: } WRFMT1_bits; 114: }; 115: 116:
union
{ 117:
__IO
uint32_t RDFMT2; 118: 119:
struct
{ 120:
__IO
uint32_t CMD : 8; 121:
__IO
uint32_t WW : 2; 122: uint32_t : 6; 123:
__IO
uint32_t AW : 2; 124: uint32_t : 6; 125:
__IO
uint32_t FC : 1; 126: } RDFMT2_bits; 127: }; 128: 129:
union
{ 130:
__IO
uint32_t WRFMT2; 131: 132:
struct
{ 133:
__IO
uint32_t CMD : 8; 134:
__IO
uint32_t WW : 2; 135:
__IO
uint32_t DW : 1; 136: uint32_t : 5; 137:
__IO
uint32_t AW : 2; 138: uint32_t : 6; 139:
__IO
uint32_t FC : 1; 140: } WRFMT2_bits; 141: }; 142: 143:
union
{ 144:
__IO
uint32_t RDFMT3; 145: 146:
struct
{ 147:
__IO
uint32_t CMD : 8; 148:
__IO
uint32_t WW : 2; 149: uint32_t : 6; 150:
__IO
uint32_t AW : 2; 151: uint32_t : 6; 152:
__IO
uint32_t FC : 1; 153: } RDFMT3_bits; 154: }; 155: 156:
union
{ 157:
__IO
uint32_t WRFMT3; 158: 159:
struct
{ 160:
__IO
uint32_t CMD : 8; 161:
__IO
uint32_t WW : 2; 162:
__IO
uint32_t DW : 1; 163: uint32_t : 5; 164:
__IO
uint32_t AW : 2; 165: uint32_t : 6; 166:
__IO
uint32_t FC : 1; 167: } WRFMT3_bits; 168: }; 169: 170: 171: }
AG903_EQS_Type
; 172: 173:
#define
AG903_EQS
((
volatile
AG903_EQS_Type
*)
AG903_EQS_BASE
) 174: 175: 176:
#define
AG903_EQS_MOD_CM_POS
0 177:
#define
AG903_EQS_MOD_CM_MSK
(0x1UL <<
AG903_EQS_MOD_CM_POS
) 178: 179:
#define
AG903_EQS_DIVIDE_DIV_POS
0 180:
#define
AG903_EQS_DIVIDE_DIV_MSK
(0xffffUL <<
AG903_EQS_DIVIDE_DIV_POS
) 181: 182:
#define
AG903_EQS_WAITCYCLE_COUNT_POS
0 183:
#define
AG903_EQS_WAITCYCLE_COUNT_MSK
(0xffffUL <<
AG903_EQS_WAITCYCLE_COUNT_POS
) 184: 185:
#define
AG903_EQS_RDFMT0_CMD_POS
0 186:
#define
AG903_EQS_RDFMT0_CMD_MSK
(0xffUL <<
AG903_EQS_RDFMT0_CMD_POS
) 187:
#define
AG903_EQS_RDFMT0_WW_POS
8 188:
#define
AG903_EQS_RDFMT0_WW_MSK
(0x3UL <<
AG903_EQS_RDFMT0_WW_POS
) 189:
#define
AG903_EQS_RDFMT0_AW_POS
16 190:
#define
AG903_EQS_RDFMT0_AW_MSK
(0x3UL <<
AG903_EQS_RDFMT0_AW_POS
) 191:
#define
AG903_EQS_RDFMT0_FC_POS
24 192:
#define
AG903_EQS_RDFMT0_FC_MSK
(0x1UL <<
AG903_EQS_RDFMT0_FC_POS
) 193: 194:
#define
AG903_EQS_WRFMT0_CMD_POS
0 195:
#define
AG903_EQS_WRFMT0_CMD_MSK
(0xffUL <<
AG903_EQS_WRFMT0_CMD_POS
) 196:
#define
AG903_EQS_WRFMT0_WW_POS
8 197:
#define
AG903_EQS_WRFMT0_WW_MSK
(0x3UL <<
AG903_EQS_WRFMT0_WW_POS
) 198:
#define
AG903_EQS_WRFMT0_DW_POS
10 199:
#define
AG903_EQS_WRFMT0_DW_MSK
(0x1UL <<
AG903_EQS_WRFMT0_DW_POS
) 200:
#define
AG903_EQS_WRFMT0_AW_POS
16 201:
#define
AG903_EQS_WRFMT0_AW_MSK
(0x3UL <<
AG903_EQS_WRFMT0_AW_POS
) 202:
#define
AG903_EQS_WRFMT0_FC_POS
24 203:
#define
AG903_EQS_WRFMT0_FC_MSK
(0x1UL <<
AG903_EQS_WRFMT0_FC_POS
) 204: 205:
#define
AG903_EQS_RDFMT1_CMD_POS
0 206:
#define
AG903_EQS_RDFMT1_CMD_MSK
(0xffUL <<
AG903_EQS_RDFMT1_CMD_POS
) 207:
#define
AG903_EQS_RDFMT1_WW_POS
8 208:
#define
AG903_EQS_RDFMT1_WW_MSK
(0x3UL <<
AG903_EQS_RDFMT1_WW_POS
) 209:
#define
AG903_EQS_RDFMT1_AW_POS
16 210:
#define
AG903_EQS_RDFMT1_AW_MSK
(0x3UL <<
AG903_EQS_RDFMT1_AW_POS
) 211:
#define
AG903_EQS_RDFMT1_FC_POS
24 212:
#define
AG903_EQS_RDFMT1_FC_MSK
(0x1UL <<
AG903_EQS_RDFMT1_FC_POS
) 213: 214:
#define
AG903_EQS_WRFMT1_CMD_POS
0 215:
#define
AG903_EQS_WRFMT1_CMD_MSK
(0xffUL <<
AG903_EQS_WRFMT1_CMD_POS
) 216:
#define
AG903_EQS_WRFMT1_WW_POS
8 217:
#define
AG903_EQS_WRFMT1_WW_MSK
(0x3UL <<
AG903_EQS_WRFMT1_WW_POS
) 218:
#define
AG903_EQS_WRFMT1_DW_POS
10 219:
#define
AG903_EQS_WRFMT1_DW_MSK
(0x1UL <<
AG903_EQS_WRFMT1_DW_POS
) 220:
#define
AG903_EQS_WRFMT1_AW_POS
16 221:
#define
AG903_EQS_WRFMT1_AW_MSK
(0x3UL <<
AG903_EQS_WRFMT1_AW_POS
) 222:
#define
AG903_EQS_WRFMT1_FC_POS
24 223:
#define
AG903_EQS_WRFMT1_FC_MSK
(0x1UL <<
AG903_EQS_WRFMT1_FC_POS
) 224: 225:
#define
AG903_EQS_RDFMT2_CMD_POS
0 226:
#define
AG903_EQS_RDFMT2_CMD_MSK
(0xffUL <<
AG903_EQS_RDFMT2_CMD_POS
) 227:
#define
AG903_EQS_RDFMT2_WW_POS
8 228:
#define
AG903_EQS_RDFMT2_WW_MSK
(0x3UL <<
AG903_EQS_RDFMT2_WW_POS
) 229:
#define
AG903_EQS_RDFMT2_AW_POS
16 230:
#define
AG903_EQS_RDFMT2_AW_MSK
(0x3UL <<
AG903_EQS_RDFMT2_AW_POS
) 231:
#define
AG903_EQS_RDFMT2_FC_POS
24 232:
#define
AG903_EQS_RDFMT2_FC_MSK
(0x1UL <<
AG903_EQS_RDFMT2_FC_POS
) 233: 234:
#define
AG903_EQS_WRFMT2_CMD_POS
0 235:
#define
AG903_EQS_WRFMT2_CMD_MSK
(0xffUL <<
AG903_EQS_WRFMT2_CMD_POS
) 236:
#define
AG903_EQS_WRFMT2_WW_POS
8 237:
#define
AG903_EQS_WRFMT2_WW_MSK
(0x3UL <<
AG903_EQS_WRFMT2_WW_POS
) 238:
#define
AG903_EQS_WRFMT2_DW_POS
10 239:
#define
AG903_EQS_WRFMT2_DW_MSK
(0x1UL <<
AG903_EQS_WRFMT2_DW_POS
) 240:
#define
AG903_EQS_WRFMT2_AW_POS
16 241:
#define
AG903_EQS_WRFMT2_AW_MSK
(0x3UL <<
AG903_EQS_WRFMT2_AW_POS
) 242:
#define
AG903_EQS_WRFMT2_FC_POS
24 243:
#define
AG903_EQS_WRFMT2_FC_MSK
(0x1UL <<
AG903_EQS_WRFMT2_FC_POS
) 244: 245:
#define
AG903_EQS_RDFMT3_CMD_POS
0 246:
#define
AG903_EQS_RDFMT3_CMD_MSK
(0xffUL <<
AG903_EQS_RDFMT3_CMD_POS
) 247:
#define
AG903_EQS_RDFMT3_WW_POS
8 248:
#define
AG903_EQS_RDFMT3_WW_MSK
(0x3UL <<
AG903_EQS_RDFMT3_WW_POS
) 249:
#define
AG903_EQS_RDFMT3_AW_POS
16 250:
#define
AG903_EQS_RDFMT3_AW_MSK
(0x3UL <<
AG903_EQS_RDFMT3_AW_POS
) 251:
#define
AG903_EQS_RDFMT3_FC_POS
24 252:
#define
AG903_EQS_RDFMT3_FC_MSK
(0x1UL <<
AG903_EQS_RDFMT3_FC_POS
) 253: 254:
#define
AG903_EQS_WRFMT3_CMD_POS
0 255:
#define
AG903_EQS_WRFMT3_CMD_MSK
(0xffUL <<
AG903_EQS_WRFMT3_CMD_POS
) 256:
#define
AG903_EQS_WRFMT3_WW_POS
8 257:
#define
AG903_EQS_WRFMT3_WW_MSK
(0x3UL <<
AG903_EQS_WRFMT3_WW_POS
) 258:
#define
AG903_EQS_WRFMT3_DW_POS
10 259:
#define
AG903_EQS_WRFMT3_DW_MSK
(0x1UL <<
AG903_EQS_WRFMT3_DW_POS
) 260:
#define
AG903_EQS_WRFMT3_AW_POS
16 261:
#define
AG903_EQS_WRFMT3_AW_MSK
(0x3UL <<
AG903_EQS_WRFMT3_AW_POS
) 262:
#define
AG903_EQS_WRFMT3_FC_POS
24 263:
#define
AG903_EQS_WRFMT3_FC_MSK
(0x1UL <<
AG903_EQS_WRFMT3_FC_POS
) 264: 265:
#endif
266:
Copyright (c) 2017-2025 Axell Corporation. All rights reserved.
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