AG903ライブラリリファレンス
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uartprm.c

UART Primitive

UART Primitive Layer

none

AXELL CORPORATION

2017_02_22 初版 

2017_10_26 Ver2.0 

2019_12_27 [SDK3.0] UARTのFCRレジスタでのライトアクセスの不具合を修正 (#2575) 

2019_12_27 [SDK3.0] AG903仕様書AX51903_DS06.pdfの修正を反映 (#2633) 

2020_07_22 [SDK3.1] UARTのDMAモード2を使用不可に変更 (#2900)

1: 12: 13: 17: 18: 19: #include "AG903_errno.h" 20: #include "AG903_common.h" 21: #include "uart/uartprm.h" 22: #include "register/AG903_uartreg.h" 23: 24: 25: #define AG903_UART_READ_REG(CH,REG) (AG903_UARTn(CH)->REG) 26: #define AG903_UART_READ_FLD(CH,REG,POS,MSK) (((AG903_UARTn(CH)->REG)&MSK) >> POS) 27: #define AG903_UART_WRITE_REG(CH,REG,VAL) (AG903_UARTn(CH)->REG = (VAL)) 28: #define AG903_UART_CLR_REG(CH,REG,VAL) (AG903_UARTn(CH)->REG &= (~VAL)) 29: #define AG903_UART_SET_REG(CH,REG,VAL) (AG903_UARTn(CH)->REG |= (VAL)) 30: #define AG903_UART_RMW_VAR(VAR,F,V) do{(VAR) &= ~(F##_MSK); (VAR) |= ((V)<<F##_POS); }while(0) 31: 32: static const uint8_t UartLCRSetTbl[AG903_UART_PARITY_TYPE_MAX][AG903_UART_WORDLEN_TYPE_MAX] = { 33: {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}, 34: {0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}, 35: {0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}, 36: }; 37: 38: static const uint8_t UartFifoTrglSetTbl[AG903_UART_RXTRGL_MAX][AG903_UART_TXTRGL_MAX] = { 39: {0x00, 0x10, 0x20, 0x30}, 40: {0x40, 0x50, 0x60, 0x70}, 41: {0x80, 0x90, 0xA0, 0xB0}, 42: {0xC0, 0xD0, 0xE0, 0xF0}, 43: }; 44: 45: static uint8_t fcr_reg[AG903_UART_CH_NUM] = 46: {0x00,0x00,0x00,0x00}; 47: 48: 57: void AG903_UARTPrmSetDivisor(uint8_t ch, uint8_t pscale, uint16_t div) 58: { 59: ASSERT(AG903_UART_CH_NUM > ch); 60: ASSERT(AG903_UART_PSR_MAXNUM >= pscale); 61: 62: AG903_UART_SET_REG(ch,LCR,(1<<AG903_UARTn_LCR_DLAB_POS)); 63: 64: AG903_UART_WRITE_REG(ch,PSR,pscale); 65: AG903_UART_WRITE_REG(ch,DLL,div); 66: AG903_UART_WRITE_REG(ch,DLM,(div>>8)); 67: 68: AG903_UART_CLR_REG(ch,LCR,(1<<AG903_UARTn_LCR_DLAB_POS)); 69: return; 70: } 71: 72: 81: void AG903_UARTPrmSetWordLength(uint8_t ch, uint8_t parity_type, uint8_t length_type) 82: { 83: ASSERT(AG903_UART_CH_NUM > ch); 84: ASSERT(AG903_UART_PARITY_TYPE_MAX > parity_type); 85: ASSERT(AG903_UART_WORDLEN_TYPE_MAX > length_type); 86: 87: AG903_UART_CLR_REG(ch,LCR,(AG903_UARTn_LCR_WL0_MSK|AG903_UARTn_LCR_WL1_MSK|AG903_UARTn_LCR_Stop_Bits_MSK| 88: AG903_UARTn_LCR_Parity_Enable_MSK|AG903_UARTn_LCR_Even_Parity_MSK|AG903_UARTn_LCR_Stick_Parity_MSK)); 89: AG903_UART_SET_REG(ch,LCR,UartLCRSetTbl[parity_type][length_type]); 90: return; 91: } 92: 93: 100: void AG903_UARTPrmDisableFifo(uint8_t ch) 101: { 102: ASSERT(AG903_UART_CH_NUM > ch); 103: AG903_UART_RMW_VAR(fcr_reg[ch],AG903_UARTn_FCR_FIFO_Enable,0); 104: AG903_UART_WRITE_REG(ch,FCR,fcr_reg[ch]); 105: return; 106: } 107: 108: 115: void AG903_UARTPrmEnableFifo(uint8_t ch) 116: { 117: ASSERT(AG903_UART_CH_NUM > ch); 118: AG903_UART_RMW_VAR(fcr_reg[ch],AG903_UARTn_FCR_FIFO_Enable,1); 119: AG903_UART_WRITE_REG(ch,FCR,fcr_reg[ch]); 120: return; 121: } 122: 123: 133: void AG903_UARTPrmSetFifoTrigger(uint8_t ch, uint8_t rx_trgl, uint8_t tx_trgl) 134: { 135: ASSERT(AG903_UART_CH_NUM > ch); 136: ASSERT(AG903_UART_RXTRGL_MAX > rx_trgl); 137: (void)tx_trgl; 138: 139: fcr_reg[ch] &= ~(AG903_UARTn_FCR_RXFIFO_TRGL_MSK); 140: fcr_reg[ch] |= UartFifoTrglSetTbl[rx_trgl][0] & AG903_UARTn_FCR_RXFIFO_TRGL_MSK; 141: AG903_UART_WRITE_REG(ch,FCR,fcr_reg[ch]); 142: return; 143: } 144: 145: 154: void AG903_UARTPrmResetFifo(uint8_t ch, uint8_t bit) 155: { 156: ASSERT(AG903_UART_CH_NUM > ch); 157: 158: if(AG903_UART_RXFIFO_BIT & bit) { 159: AG903_UART_RMW_VAR(fcr_reg[ch],AG903_UARTn_FCR_RX_FIFO_Reset,1); 160: AG903_UART_WRITE_REG(ch,FCR,fcr_reg[ch]); 161: 162: AG903_UART_RMW_VAR(fcr_reg[ch],AG903_UARTn_FCR_RX_FIFO_Reset,0); 163: } 164: if(AG903_UART_TXFIFO_BIT & bit) { 165: AG903_UART_RMW_VAR(fcr_reg[ch],AG903_UARTn_FCR_TX_FIFO_Reset,1); 166: AG903_UART_WRITE_REG(ch,FCR,fcr_reg[ch]); 167: 168: AG903_UART_RMW_VAR(fcr_reg[ch],AG903_UARTn_FCR_TX_FIFO_Reset,0); 169: } 170: 171: return; 172: } 173: 174: 182: void AG903_UARTPrmDisableFlowControl(uint8_t ch, uint8_t bit) 183: { 184: ASSERT(AG903_UART_CH_NUM > ch); 185: AG903_UART_CLR_REG(ch,IER,(bit&0xF0)); 186: return; 187: } 188: 189: 197: void AG903_UARTPrmEnableFlowControl(uint8_t ch, uint8_t bit) 198: { 199: ASSERT(AG903_UART_CH_NUM > ch); 200: AG903_UART_SET_REG(ch,IER,(bit&0xF0)); 201: return; 202: } 203: 204: 215: void AG903_UARTPrmSetDmaMode(uint8_t ch, uint8_t mode) 216: { 217: ASSERT(AG903_UART_CH_NUM > ch); 218: ASSERT(AG903_UART_DMA_MODE_MAX > mode); 219: 220: AG903_UART_CLR_REG(ch,MCR,(1<<AG903_UARTn_MCR_DMAmode2_POS)); 221: if(AG903_UART_DMA_MODE1 == mode) { 222: AG903_UART_RMW_VAR(fcr_reg[ch],AG903_UARTn_FCR_DMA_Mode,1); 223: AG903_UART_WRITE_REG(ch,FCR,fcr_reg[ch]); 224: } 225: else { 226: AG903_UART_RMW_VAR(fcr_reg[ch],AG903_UARTn_FCR_DMA_Mode,0); 227: AG903_UART_WRITE_REG(ch,FCR,fcr_reg[ch]); 228: } 229: return; 230: } 231: 232: 240: void AG903_UARTPrmSetBreak(uint8_t ch, _Bool enable) 241: { 242: ASSERT(AG903_UART_CH_NUM > ch); 243: 244: if(true == enable) { 245: AG903_UART_SET_REG(ch,LCR,(1<<AG903_UARTn_LCR_Set_Break_POS)); 246: } 247: else { 248: AG903_UART_CLR_REG(ch,LCR,(1<<AG903_UARTn_LCR_Set_Break_POS)); 249: } 250: return; 251: } 252: 253: 261: void AG903_UARTPrmDisableInt(uint8_t ch, uint32_t bit) 262: { 263: ASSERT(AG903_UART_CH_NUM > ch); 264: AG903_UART_CLR_REG(ch,IER,(bit&0x0F)); 265: 266: return; 267: } 268: 269: 277: void AG903_UARTPrmEnableInt(uint8_t ch, uint32_t bit) 278: { 279: ASSERT(AG903_UART_CH_NUM > ch); 280: AG903_UART_SET_REG(ch,IER,(bit&0x0F)); 281: return; 282: } 283: 284: 292: void AG903_UARTPrmSendData(uint8_t ch, uint8_t* buf, uint32_t sndsz) 293: { 294: uint32_t loop; 295: 296: ASSERT(AG903_UART_CH_NUM > ch); 297: ASSERT(AG903_UART_FIFO_SIZE >= sndsz); 298: ASSERT(NULL != buf); 299: 300: for(loop=0; loop<sndsz; loop++) { 301: AG903_UART_WRITE_REG(ch,THR,(*buf)); 302: buf++; 303: } 304: 305: return; 306: } 307: 308: 315: void AG903_UARTPrmGetReceiveData(uint8_t ch, uint8_t* buf) 316: { 317: ASSERT(AG903_UART_CH_NUM > ch); 318: (*buf) = AG903_UART_READ_REG(ch,RBR); 319: return; 320: } 321: 322: 329: void AG903_UARTPrmGetIntType(uint8_t ch, uint8_t* type) 330: { 331: uint8_t val; 332: 333: ASSERT(AG903_UART_CH_NUM > ch); 334: val = AG903_UART_READ_REG(ch,IIR); 335: (*type) = (val&0x0F); 336: 337: return; 338: } 339: 340: 347: void AG903_UARTPrmGetLineStatus(uint8_t ch, uint8_t* status) 348: { 349: ASSERT(AG903_UART_CH_NUM > ch); 350: (*status) = AG903_UART_READ_REG(ch,LSR); 351: return; 352: } 353: 354: 361: void AG903_UARTPrmDisableRS485(uint8_t ch) 362: { 363: ASSERT(AG903_UART_CH_NUM > ch); 364: AG903_UART_CLR_REG(ch,MOD,(1<<AG903_UARTn_MOD_FC_POS)); 365: return; 366: } 367: 368: 375: void AG903_UARTPrmEnableRS485(uint8_t ch) 376: { 377: ASSERT(AG903_UART_CH_NUM > ch); 378: AG903_UART_SET_REG(ch,MOD,(1<<AG903_UARTn_MOD_FC_POS)); 379: return; 380: } 381: 382: 389: void AG903_UARTPrmDisableTimeoutDetect(uint8_t ch) 390: { 391: ASSERT(AG903_UART_CH_NUM > ch); 392: AG903_UART_CLR_REG(ch,MOD,(1<<AG903_UARTn_MOD_TD_POS)); 393: return; 394: } 395: 396: 403: void AG903_UARTPrmEnableTimeoutDetect(uint8_t ch) 404: { 405: ASSERT(AG903_UART_CH_NUM > ch); 406: AG903_UART_SET_REG(ch,MOD,(1<<AG903_UARTn_MOD_TD_POS)); 407: return; 408: } 409: 410: 418: void AG903_UARTPrmDisableTimeoutIntMask(uint8_t ch, uint32_t bit) 419: { 420: ASSERT(AG903_UART_CH_NUM > ch); 421: AG903_UART_CLR_REG(ch,INTMASK,bit); 422: return; 423: } 424: 425: 433: void AG903_UARTPrmEnableTimeoutIntMask(uint8_t ch, uint32_t bit) 434: { 435: ASSERT(AG903_UART_CH_NUM > ch); 436: AG903_UART_SET_REG(ch,INTMASK,bit); 437: return; 438: } 439: 440: 449: void AG903_UARTPrmSetAutoMode(uint8_t ch, _Bool hold, _Bool setup) 450: { 451: ASSERT(AG903_UART_CH_NUM > ch); 452: 453: if(true == hold) { 454: AG903_UART_CLR_REG(ch,MOD,(1<<AG903_UARTn_MOD_HM_POS)); 455: } 456: else { 457: AG903_UART_SET_REG(ch,MOD,(1<<AG903_UARTn_MOD_HM_POS)); 458: } 459: 460: if(true == setup) { 461: AG903_UART_CLR_REG(ch,MOD,(1<<AG903_UARTn_MOD_SM_POS)); 462: } 463: else { 464: AG903_UART_SET_REG(ch,MOD,(1<<AG903_UARTn_MOD_SM_POS)); 465: } 466: return; 467: } 468: 469: 476: void AG903_UARTPrmSetSetuptime(uint8_t ch, uint32_t setup_time) 477: { 478: ASSERT(AG903_UART_CH_NUM > ch); 479: AG903_UART_WRITE_REG(ch,SETUPTIME,setup_time); 480: return; 481: } 482: 483: 490: void AG903_UARTPrmSetHoldtime(uint8_t ch, uint32_t hold_time) 491: { 492: ASSERT(AG903_UART_CH_NUM > ch); 493: AG903_UART_WRITE_REG(ch,HOLDTIME,hold_time); 494: return; 495: } 496: 497: 504: void AG903_UARTPrmSetReceivetime(uint8_t ch, uint32_t rcv_time) 505: { 506: ASSERT(AG903_UART_CH_NUM > ch); 507: AG903_UART_WRITE_REG(ch,RECEIVETIME,rcv_time); 508: return; 509: } 510: 511: 518: void AG903_UARTPrmSetCharainterval(uint8_t ch, uint32_t chara_interval) 519: { 520: ASSERT(AG903_UART_CH_NUM > ch); 521: AG903_UART_WRITE_REG(ch,CHARINTERVAL,chara_interval); 522: return; 523: } 524: 525: 532: void AG903_UARTPrmSetTimeout(uint8_t ch, uint32_t timeout) 533: { 534: ASSERT(AG903_UART_CH_NUM > ch); 535: AG903_UART_WRITE_REG(ch,TIMEOUT,timeout); 536: return; 537: } 538: 539: 547: void AG903_UARTPrmClerTimeoutStatus(uint8_t ch, uint32_t bit) 548: { 549: ASSERT(AG903_UART_CH_NUM > ch); 550: AG903_UART_SET_REG(ch,CLR,bit); 551: return; 552: } 553: 554: 561: void AG903_UARTPrmGetRs485Status(uint8_t ch, uint32_t* status) 562: { 563: ASSERT(AG903_UART_CH_NUM > ch); 564: (*status) = AG903_UART_READ_REG(ch,STAT); 565: return; 566: }
 
名前 
説明 
 
UARTnCLRのレジスタWrite(指定ビットをSet) 
 
UARTnFCRレジスタのFIFO_EnableビットClear 
 
UARTnIERレジスタのDSREn,DTREn,CTSEn,RTSEnビットのClear 
 
UARTnIERレジスタのMODEM_Status,Receiver_Line_Status,THR_Empty,Receiver_Data_AvailableビットClear 
 
UARTnMODレジスタのFCビットClear 
 
UARTnMODレジスタのTDビットClear 
 
UARTnINTMASKのレジスタWrite(指定ビットをClear) 
 
UARTnFCRレジスタのFIFO_EnableビットSet 
 
UARTnIERレジスタのDSREn,DTREn,CTSEn,RTSEnビットのSet 
 
UARTnIERレジスタのMODEM_Status,Receiver_Line_Status,THR_Empty,Receiver_Data_AvailableビットSet 
 
UARTnMODレジスタのFCビットSet 
 
UARTnMODレジスタのTDビットSet 
 
UARTnINTMASKのレジスタWrite(指定ビットをSet) 
 
UARTnIIRのレジスタRead 
 
UARTnLSRのレジスタRead 
 
UARTnRBRのレジスタRead 
 
UARTnSTATのレジスタRead 
 
UARTnFCRレジスタのTX_FIFO_Reset,RX_FIFO_Resetフィールド設定 
 
UARTnTHRのレジスタWrite 
 
UARTnMODレジスタのHMビット,SMビットSet/Clear 
 
UARTnLCRレジスタのSet_BreakビットSet/Clear 
 
UARTnCHARINTERVALのレジスタWrite 
 
UARTnDLL/UARTnDLM,UARTnPSRのレジスタWrite 
 
UARTnFCRレジスタのDMA_ModeビットSet 
 
UARTnFCRレジスタのRXFIFO_TRGLフィールド設定 
 
UARTnHOLDTIMEのレジスタWrite 
 
UARTnRECEIVETIMEのレジスタWrite 
 
UARTnSETUPTIMEのレジスタWrite 
 
UARTnTIMEOUTのレジスタWrite 
 
UARTnLCRのレジスタWrite 
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