AG903ライブラリリファレンス
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AG903_dtareg.h
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1: 8: 9: 13: 14:
#ifndef
_AG903_DTA_REGMAP_H_ 15:
#define
_AG903_DTA_REGMAP_H_ 16: 17: 18:
#include
"AG903_regmap.h" 19: 20:
#ifndef
__I
21: 22:
#define
__I
volatile
const
23:
#endif
24:
#ifndef
__O
25: 26:
#define
__O
volatile
27:
#endif
28:
#ifndef
__IO
29: 30:
#define
__IO
volatile
31:
#endif
32: 33: 34:
typedef
struct
{ 35: 36:
union
{ 37:
__O
uint32_t EXEC; 38: 39:
struct
{ 40:
__O
uint32_t EN : 1; 41: } EXEC_bits; 42: }; 43: 44:
union
{ 45:
__I
uint32_t STAT; 46: 47:
struct
{ 48:
__I
uint32_t BSY : 2; 49: } STAT_bits; 50: }; 51: 52:
union
{ 53:
__IO
uint32_t MODE; 54: 55:
struct
{ 56:
__IO
uint32_t DEC : 1; 57:
__IO
uint32_t D2 : 1; 58: uint32_t : 6; 59:
__IO
uint32_t DPMD : 2; 60: uint32_t : 6; 61:
__IO
uint32_t SSWP : 2; 62: uint32_t : 6; 63:
__IO
uint32_t DSWP : 3; 64: } MODE_bits; 65: }; 66: 67:
__I
uint32_t RESERVED1[1]; 68: 69:
union
{ 70:
__I
uint32_t INTS; 71: 72:
struct
{ 73:
__I
uint32_t STA : 5; 74: } INTS_bits; 75: }; 76: 77:
union
{ 78:
__O
uint32_t INTC; 79: 80:
struct
{ 81:
__O
uint32_t CLR : 5; 82: } INTC_bits; 83: }; 84: 85:
union
{ 86:
__IO
uint32_t INTM; 87: 88:
struct
{ 89:
__IO
uint32_t MSK : 5; 90: } INTM_bits; 91: }; 92: 93:
__I
uint32_t RESERVED2[1]; 94: 95:
union
{ 96:
__IO
uint32_t SRCA; 97: }; 98: 99:
union
{ 100:
__IO
uint32_t SRCS; 101: 102:
struct
{ 103:
__IO
uint32_t STR : 16; 104: } SRCS_bits; 105: }; 106: 107:
union
{ 108:
__IO
uint32_t DSTA; 109: }; 110: 111:
union
{ 112:
__IO
uint32_t DSTS; 113: 114:
struct
{ 115:
__IO
uint32_t STR : 16; 116: } DSTS_bits; 117: }; 118: 119:
union
{ 120:
__IO
uint32_t SIZ1; 121: 122:
struct
{ 123:
__IO
uint32_t SIZ : 26; 124: } SIZ1_bits; 125: }; 126: 127:
union
{ 128:
__IO
uint32_t SIZ2; 129: 130:
struct
{ 131:
__IO
uint32_t HSIZ : 12; 132: uint32_t : 4; 133:
__IO
uint32_t VSIZ : 12; 134: } SIZ2_bits; 135: }; 136: 137:
__I
uint32_t RESERVED3[2]; 138: 139:
union
{ 140:
__IO
uint32_t DPORT; 141: }; 142: 143:
union
{ 144:
__I
uint32_t DPSTA; 145: 146:
struct
{ 147:
__I
uint32_t AVAI : 6; 148: } DPSTA_bits; 149: }; 150: 151:
union
{ 152:
__I
uint32_t SRCM; 153: }; 154: 155:
union
{ 156:
__I
uint32_t DSTM; 157: }; 158: 159: 160: }
AG903_DTA_Type
; 161: 162:
#define
AG903_DTA
((
volatile
AG903_DTA_Type
*)
AG903_DTA_BASE
) 163: 164: 165:
#define
AG903_DTA_EXEC_EN_POS
0 166:
#define
AG903_DTA_EXEC_EN_MSK
(0x1UL <<
AG903_DTA_EXEC_EN_POS
) 167: 168:
#define
AG903_DTA_STAT_BSY_POS
0 169:
#define
AG903_DTA_STAT_BSY_MSK
(0x3UL <<
AG903_DTA_STAT_BSY_POS
) 170: 171:
#define
AG903_DTA_MODE_DEC_POS
0 172:
#define
AG903_DTA_MODE_DEC_MSK
(0x1UL <<
AG903_DTA_MODE_DEC_POS
) 173:
#define
AG903_DTA_MODE_D2_POS
1 174:
#define
AG903_DTA_MODE_D2_MSK
(0x1UL <<
AG903_DTA_MODE_D2_POS
) 175:
#define
AG903_DTA_MODE_DPMD_POS
8 176:
#define
AG903_DTA_MODE_DPMD_MSK
(0x3UL <<
AG903_DTA_MODE_DPMD_POS
) 177:
#define
AG903_DTA_MODE_SSWP_POS
16 178:
#define
AG903_DTA_MODE_SSWP_MSK
(0x3UL <<
AG903_DTA_MODE_SSWP_POS
) 179:
#define
AG903_DTA_MODE_DSWP_POS
24 180:
#define
AG903_DTA_MODE_DSWP_MSK
(0x7UL <<
AG903_DTA_MODE_DSWP_POS
) 181: 182:
#define
AG903_DTA_INTS_STA_POS
0 183:
#define
AG903_DTA_INTS_STA_MSK
(0x1fUL <<
AG903_DTA_INTS_STA_POS
) 184: 185:
#define
AG903_DTA_INTC_CLR_POS
0 186:
#define
AG903_DTA_INTC_CLR_MSK
(0x1fUL <<
AG903_DTA_INTC_CLR_POS
) 187: 188:
#define
AG903_DTA_INTM_MSK_POS
0 189:
#define
AG903_DTA_INTM_MSK_MSK
(0x1fUL <<
AG903_DTA_INTM_MSK_POS
) 190: 191:
#define
AG903_DTA_SRCA_ADR_POS
0 192:
#define
AG903_DTA_SRCA_ADR_MSK
(0xffffffffUL <<
AG903_DTA_SRCA_ADR_POS
) 193: 194:
#define
AG903_DTA_SRCS_STR_POS
0 195:
#define
AG903_DTA_SRCS_STR_MSK
(0xffffUL <<
AG903_DTA_SRCS_STR_POS
) 196: 197:
#define
AG903_DTA_DSTA_ADR_POS
0 198:
#define
AG903_DTA_DSTA_ADR_MSK
(0xffffffffUL <<
AG903_DTA_DSTA_ADR_POS
) 199: 200:
#define
AG903_DTA_DSTS_STR_POS
0 201:
#define
AG903_DTA_DSTS_STR_MSK
(0xffffUL <<
AG903_DTA_DSTS_STR_POS
) 202: 203:
#define
AG903_DTA_SIZ1_SIZ_POS
0 204:
#define
AG903_DTA_SIZ1_SIZ_MSK
(0x3ffffffUL <<
AG903_DTA_SIZ1_SIZ_POS
) 205: 206:
#define
AG903_DTA_SIZ2_HSIZ_POS
0 207:
#define
AG903_DTA_SIZ2_HSIZ_MSK
(0xfffUL <<
AG903_DTA_SIZ2_HSIZ_POS
) 208:
#define
AG903_DTA_SIZ2_VSIZ_POS
16 209:
#define
AG903_DTA_SIZ2_VSIZ_MSK
(0xfffUL <<
AG903_DTA_SIZ2_VSIZ_POS
) 210: 211:
#define
AG903_DTA_DPORT_DAT_POS
0 212:
#define
AG903_DTA_DPORT_DAT_MSK
(0xffffffffUL <<
AG903_DTA_DPORT_DAT_POS
) 213: 214:
#define
AG903_DTA_DPSTA_AVAI_POS
0 215:
#define
AG903_DTA_DPSTA_AVAI_MSK
(0x3fUL <<
AG903_DTA_DPSTA_AVAI_POS
) 216: 217:
#define
AG903_DTA_SRCM_ADR_POS
0 218:
#define
AG903_DTA_SRCM_ADR_MSK
(0xffffffffUL <<
AG903_DTA_SRCM_ADR_POS
) 219: 220:
#define
AG903_DTA_DSTM_ADR_POS
0 221:
#define
AG903_DTA_DSTM_ADR_MSK
(0xffffffffUL <<
AG903_DTA_DSTM_ADR_POS
) 222: 223:
#endif
224:
Copyright (c) 2017-2025 Axell Corporation. All rights reserved.
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