AG903ライブラリリファレンス
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AG903_atareg.h
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1: 8: 9: 13: 14:
#ifndef
_AG903_ATA_REGMAP_H_ 15:
#define
_AG903_ATA_REGMAP_H_ 16: 17: 18:
#include
"AG903_regmap.h" 19: 20:
#ifndef
__I
21: 22:
#define
__I
volatile
const
23:
#endif
24:
#ifndef
__O
25: 26:
#define
__O
volatile
27:
#endif
28:
#ifndef
__IO
29: 30:
#define
__IO
volatile
31:
#endif
32: 33: 34:
typedef
struct
{ 35: 36:
union
{ 37:
__I
uint32_t Read_FIFO; 38:
__O
uint32_t Write_FIFO; 39: }; 40: 41:
union
{ 42:
__I
uint32_t Status_Register; 43: 44:
struct
{ 45:
__I
uint32_t CSEL : 1; 46:
__I
uint32_t CSX : 2; 47:
__I
uint32_t DMACKX : 1; 48:
__I
uint32_t DMARQ : 1; 49:
__I
uint32_t INTRQ : 1; 50:
__I
uint32_t DIORX : 1; 51:
__I
uint32_t IORDY : 1; 52:
__I
uint32_t DIOWX : 1; 53:
__I
uint32_t PDIAG : 1; 54:
__I
uint32_t DASPX : 1; 55:
__I
uint32_t DEV : 1; 56:
__I
uint32_t PIO : 1; 57:
__I
uint32_t DMA : 1; 58:
__I
uint32_t WFE : 1; 59:
__I
uint32_t REF : 1; 60:
__I
uint32_t Counter : 14; 61:
__I
uint32_t ERR : 1; 62:
__I
uint32_t AER : 1; 63: } Status_Register_bits; 64: 65:
__O
uint32_t Command_FIFO; 66: }; 67: 68:
union
{ 69:
__IO
uint32_t Control_Register; 70: 71:
struct
{ 72:
__IO
uint32_t type0 : 3; 73:
__IO
uint32_t IRE0 : 1; 74: uint32_t : 1; 75:
__IO
uint32_t E0 : 1; 76: uint32_t : 3; 77:
__IO
uint32_t RAFIE : 1; 78:
__IO
uint32_t RNEIE : 1; 79:
__IO
uint32_t WAEIE : 1; 80:
__IO
uint32_t WNFIE : 1; 81: uint32_t : 1; 82:
__IO
uint32_t AERIE : 1; 83:
__IO
uint32_t IIE : 1; 84:
__IO
uint32_t type1 : 3; 85:
__IO
uint32_t IRE1 : 1; 86: uint32_t : 1; 87:
__IO
uint32_t E1 : 1; 88: uint32_t : 3; 89:
__IO
uint32_t DRE : 1; 90:
__IO
uint32_t DTE : 1; 91: uint32_t : 1; 92:
__IO
uint32_t TERIE : 1; 93:
__IO
uint32_t T : 1; 94:
__IO
uint32_t SRST : 1; 95:
__IO
uint32_t RST : 1; 96: } Control_Register_bits; 97: }; 98: 99:
union
{ 100:
__IO
uint32_t IRQ_Register; 101: 102:
struct
{ 103:
__IO
uint32_t rxthresh : 10; 104:
__IO
uint32_t RFAFIRQ : 1; 105:
__IO
uint32_t RFNEIRQ : 1; 106:
__IO
uint32_t WFAEIRQ : 1; 107:
__IO
uint32_t WFNFIRQ : 1; 108: uint32_t : 1; 109:
__IO
uint32_t IIRQ : 1; 110:
__IO
uint32_t txthresh : 10; 111: uint32_t : 2; 112:
__IO
uint32_t TERMERR : 1; 113:
__IO
uint32_t AHBERR : 1; 114: } IRQ_Register_bits; 115: }; 116: 117:
union
{ 118:
__IO
uint32_t Command_Timing_0; 119: 120:
struct
{ 121:
__IO
uint32_t T1 : 8; 122:
__IO
uint32_t T2 : 8; 123:
__IO
uint32_t T4 : 8; 124:
__IO
uint32_t TEOC : 8; 125: } Command_Timing_0_bits; 126: }; 127: 128:
union
{ 129:
__IO
uint32_t Data_Timing_PIO_0; 130: 131:
struct
{ 132:
__IO
uint32_t T1 : 8; 133:
__IO
uint32_t T2 : 8; 134:
__IO
uint32_t T4 : 8; 135:
__IO
uint32_t TEOC : 8; 136: } Data_Timing_PIO_0_bits; 137: 138:
__IO
uint32_t Data_Timing_UDMA_0; 139: 140:
struct
{ 141:
__IO
uint32_t TENV : 4; 142:
__IO
uint32_t TMLI : 4; 143:
__IO
uint32_t TCYC : 8; 144:
__IO
uint32_t TACK : 4; 145:
__IO
uint32_t TCVS : 4; 146:
__IO
uint32_t TRP : 8; 147: } Data_Timing_UDMA_0_bits; 148: }; 149: 150:
union
{ 151:
__IO
uint32_t Command_Timing_1; 152: 153:
struct
{ 154:
__IO
uint32_t T1 : 8; 155:
__IO
uint32_t T2 : 8; 156:
__IO
uint32_t T4 : 8; 157:
__IO
uint32_t TEOC : 8; 158: } Command_Timing_1_bits; 159: }; 160: 161:
union
{ 162:
__IO
uint32_t Data_Timing_PIO_1; 163: 164:
struct
{ 165:
__IO
uint32_t T1 : 8; 166:
__IO
uint32_t T2 : 8; 167:
__IO
uint32_t T4 : 8; 168:
__IO
uint32_t TEOC : 8; 169: } Data_Timing_PIO_1_bits; 170: 171:
__IO
uint32_t Data_Timing_UDMA_1; 172: 173:
struct
{ 174:
__IO
uint32_t TENV : 4; 175:
__IO
uint32_t TMLI : 4; 176:
__IO
uint32_t TCYC : 8; 177:
__IO
uint32_t TACK : 4; 178:
__IO
uint32_t TCVS : 4; 179:
__IO
uint32_t TRP : 8; 180: } Data_Timing_UDMA_1_bits; 181: }; 182: 183:
union
{ 184:
__IO
uint32_t AHB_Timeout; 185: 186:
struct
{ 187:
__IO
uint32_t WRITE_VALUE : 15; 188:
__IO
uint32_t WRITE_ENABLE : 1; 189:
__IO
uint32_t READ_VALUE : 15; 190:
__IO
uint32_t READ_ENABLE : 1; 191: } AHB_Timeout_bits; 192: }; 193: 194:
__I
uint32_t RESERVED1[3]; 195: 196:
union
{ 197:
__I
uint32_t Feature_CFIFO; 198: 199:
struct
{ 200:
__I
uint32_t CFIFO_DEPTH : 8; 201:
__I
uint32_t CFIFO_WIDTH : 8; 202: } Feature_CFIFO_bits; 203: }; 204: 205:
union
{ 206:
__I
uint32_t Feature_WFIFO; 207: 208:
struct
{ 209:
__I
uint32_t WFIFO_DEPTH : 8; 210:
__I
uint32_t WFIFO_WIDTH : 8; 211: } Feature_WFIFO_bits; 212: }; 213: 214:
union
{ 215:
__I
uint32_t Feature_RFIFO; 216: 217:
struct
{ 218:
__I
uint32_t RFIFO_DEPTH : 8; 219:
__I
uint32_t RFIFO_WIDTH : 8; 220: } Feature_RFIFO_bits; 221: }; 222: 223:
union
{ 224:
__I
uint32_t Revision; 225: }; 226: 227: 228: }
AG903_ATA_Type
; 229: 230:
#define
AG903_ATA
((
volatile
AG903_ATA_Type
*)
AG903_ATA_BASE
) 231: 232: 233:
#define
AG903_ATA_Read_FIFO_DATA_POS
0 234:
#define
AG903_ATA_Read_FIFO_DATA_MSK
(0xffffffffUL <<
AG903_ATA_Read_FIFO_DATA_POS
) 235: 236:
#define
AG903_ATA_Write_FIFO_DATA_POS
0 237:
#define
AG903_ATA_Write_FIFO_DATA_MSK
(0xffffffffUL <<
AG903_ATA_Write_FIFO_DATA_POS
) 238: 239:
#define
AG903_ATA_Status_Register_CSEL_POS
0 240:
#define
AG903_ATA_Status_Register_CSEL_MSK
(0x1UL <<
AG903_ATA_Status_Register_CSEL_POS
) 241:
#define
AG903_ATA_Status_Register_CSX_POS
1 242:
#define
AG903_ATA_Status_Register_CSX_MSK
(0x3UL <<
AG903_ATA_Status_Register_CSX_POS
) 243:
#define
AG903_ATA_Status_Register_DMACKX_POS
3 244:
#define
AG903_ATA_Status_Register_DMACKX_MSK
(0x1UL <<
AG903_ATA_Status_Register_DMACKX_POS
) 245:
#define
AG903_ATA_Status_Register_DMARQ_POS
4 246:
#define
AG903_ATA_Status_Register_DMARQ_MSK
(0x1UL <<
AG903_ATA_Status_Register_DMARQ_POS
) 247:
#define
AG903_ATA_Status_Register_INTRQ_POS
5 248:
#define
AG903_ATA_Status_Register_INTRQ_MSK
(0x1UL <<
AG903_ATA_Status_Register_INTRQ_POS
) 249:
#define
AG903_ATA_Status_Register_DIORX_POS
6 250:
#define
AG903_ATA_Status_Register_DIORX_MSK
(0x1UL <<
AG903_ATA_Status_Register_DIORX_POS
) 251:
#define
AG903_ATA_Status_Register_IORDY_POS
7 252:
#define
AG903_ATA_Status_Register_IORDY_MSK
(0x1UL <<
AG903_ATA_Status_Register_IORDY_POS
) 253:
#define
AG903_ATA_Status_Register_DIOWX_POS
8 254:
#define
AG903_ATA_Status_Register_DIOWX_MSK
(0x1UL <<
AG903_ATA_Status_Register_DIOWX_POS
) 255:
#define
AG903_ATA_Status_Register_PDIAG_POS
9 256:
#define
AG903_ATA_Status_Register_PDIAG_MSK
(0x1UL <<
AG903_ATA_Status_Register_PDIAG_POS
) 257:
#define
AG903_ATA_Status_Register_DASPX_POS
10 258:
#define
AG903_ATA_Status_Register_DASPX_MSK
(0x1UL <<
AG903_ATA_Status_Register_DASPX_POS
) 259:
#define
AG903_ATA_Status_Register_DEV_POS
11 260:
#define
AG903_ATA_Status_Register_DEV_MSK
(0x1UL <<
AG903_ATA_Status_Register_DEV_POS
) 261:
#define
AG903_ATA_Status_Register_PIO_POS
12 262:
#define
AG903_ATA_Status_Register_PIO_MSK
(0x1UL <<
AG903_ATA_Status_Register_PIO_POS
) 263:
#define
AG903_ATA_Status_Register_DMA_POS
13 264:
#define
AG903_ATA_Status_Register_DMA_MSK
(0x1UL <<
AG903_ATA_Status_Register_DMA_POS
) 265:
#define
AG903_ATA_Status_Register_WFE_POS
14 266:
#define
AG903_ATA_Status_Register_WFE_MSK
(0x1UL <<
AG903_ATA_Status_Register_WFE_POS
) 267:
#define
AG903_ATA_Status_Register_REF_POS
15 268:
#define
AG903_ATA_Status_Register_REF_MSK
(0x1UL <<
AG903_ATA_Status_Register_REF_POS
) 269:
#define
AG903_ATA_Status_Register_Counter_POS
16 270:
#define
AG903_ATA_Status_Register_Counter_MSK
(0x3fffUL <<
AG903_ATA_Status_Register_Counter_POS
) 271:
#define
AG903_ATA_Status_Register_ERR_POS
30 272:
#define
AG903_ATA_Status_Register_ERR_MSK
(0x1UL <<
AG903_ATA_Status_Register_ERR_POS
) 273:
#define
AG903_ATA_Status_Register_AER_POS
31 274:
#define
AG903_ATA_Status_Register_AER_MSK
(0x1UL <<
AG903_ATA_Status_Register_AER_POS
) 275: 276:
#define
AG903_ATA_Command_FIFO_DATA_POS
0 277:
#define
AG903_ATA_Command_FIFO_DATA_MSK
(0xffffffffUL <<
AG903_ATA_Command_FIFO_DATA_POS
) 278: 279:
#define
AG903_ATA_Control_Register_type0_POS
0 280:
#define
AG903_ATA_Control_Register_type0_MSK
(0x7UL <<
AG903_ATA_Control_Register_type0_POS
) 281:
#define
AG903_ATA_Control_Register_IRE0_POS
3 282:
#define
AG903_ATA_Control_Register_IRE0_MSK
(0x1UL <<
AG903_ATA_Control_Register_IRE0_POS
) 283:
#define
AG903_ATA_Control_Register_E0_POS
5 284:
#define
AG903_ATA_Control_Register_E0_MSK
(0x1UL <<
AG903_ATA_Control_Register_E0_POS
) 285:
#define
AG903_ATA_Control_Register_RAFIE_POS
9 286:
#define
AG903_ATA_Control_Register_RAFIE_MSK
(0x1UL <<
AG903_ATA_Control_Register_RAFIE_POS
) 287:
#define
AG903_ATA_Control_Register_RNEIE_POS
10 288:
#define
AG903_ATA_Control_Register_RNEIE_MSK
(0x1UL <<
AG903_ATA_Control_Register_RNEIE_POS
) 289:
#define
AG903_ATA_Control_Register_WAEIE_POS
11 290:
#define
AG903_ATA_Control_Register_WAEIE_MSK
(0x1UL <<
AG903_ATA_Control_Register_WAEIE_POS
) 291:
#define
AG903_ATA_Control_Register_WNFIE_POS
12 292:
#define
AG903_ATA_Control_Register_WNFIE_MSK
(0x1UL <<
AG903_ATA_Control_Register_WNFIE_POS
) 293:
#define
AG903_ATA_Control_Register_AERIE_POS
14 294:
#define
AG903_ATA_Control_Register_AERIE_MSK
(0x1UL <<
AG903_ATA_Control_Register_AERIE_POS
) 295:
#define
AG903_ATA_Control_Register_IIE_POS
15 296:
#define
AG903_ATA_Control_Register_IIE_MSK
(0x1UL <<
AG903_ATA_Control_Register_IIE_POS
) 297:
#define
AG903_ATA_Control_Register_type1_POS
16 298:
#define
AG903_ATA_Control_Register_type1_MSK
(0x7UL <<
AG903_ATA_Control_Register_type1_POS
) 299:
#define
AG903_ATA_Control_Register_IRE1_POS
19 300:
#define
AG903_ATA_Control_Register_IRE1_MSK
(0x1UL <<
AG903_ATA_Control_Register_IRE1_POS
) 301:
#define
AG903_ATA_Control_Register_E1_POS
21 302:
#define
AG903_ATA_Control_Register_E1_MSK
(0x1UL <<
AG903_ATA_Control_Register_E1_POS
) 303:
#define
AG903_ATA_Control_Register_DRE_POS
25 304:
#define
AG903_ATA_Control_Register_DRE_MSK
(0x1UL <<
AG903_ATA_Control_Register_DRE_POS
) 305:
#define
AG903_ATA_Control_Register_DTE_POS
26 306:
#define
AG903_ATA_Control_Register_DTE_MSK
(0x1UL <<
AG903_ATA_Control_Register_DTE_POS
) 307:
#define
AG903_ATA_Control_Register_TERIE_POS
28 308:
#define
AG903_ATA_Control_Register_TERIE_MSK
(0x1UL <<
AG903_ATA_Control_Register_TERIE_POS
) 309:
#define
AG903_ATA_Control_Register_T_POS
29 310:
#define
AG903_ATA_Control_Register_T_MSK
(0x1UL <<
AG903_ATA_Control_Register_T_POS
) 311:
#define
AG903_ATA_Control_Register_SRST_POS
30 312:
#define
AG903_ATA_Control_Register_SRST_MSK
(0x1UL <<
AG903_ATA_Control_Register_SRST_POS
) 313:
#define
AG903_ATA_Control_Register_RST_POS
31 314:
#define
AG903_ATA_Control_Register_RST_MSK
(0x1UL <<
AG903_ATA_Control_Register_RST_POS
) 315: 316:
#define
AG903_ATA_IRQ_Register_rxthresh_POS
0 317:
#define
AG903_ATA_IRQ_Register_rxthresh_MSK
(0x3ffUL <<
AG903_ATA_IRQ_Register_rxthresh_POS
) 318:
#define
AG903_ATA_IRQ_Register_RFAFIRQ_POS
10 319:
#define
AG903_ATA_IRQ_Register_RFAFIRQ_MSK
(0x1UL <<
AG903_ATA_IRQ_Register_RFAFIRQ_POS
) 320:
#define
AG903_ATA_IRQ_Register_RFNEIRQ_POS
11 321:
#define
AG903_ATA_IRQ_Register_RFNEIRQ_MSK
(0x1UL <<
AG903_ATA_IRQ_Register_RFNEIRQ_POS
) 322:
#define
AG903_ATA_IRQ_Register_WFAEIRQ_POS
12 323:
#define
AG903_ATA_IRQ_Register_WFAEIRQ_MSK
(0x1UL <<
AG903_ATA_IRQ_Register_WFAEIRQ_POS
) 324:
#define
AG903_ATA_IRQ_Register_WFNFIRQ_POS
13 325:
#define
AG903_ATA_IRQ_Register_WFNFIRQ_MSK
(0x1UL <<
AG903_ATA_IRQ_Register_WFNFIRQ_POS
) 326:
#define
AG903_ATA_IRQ_Register_IIRQ_POS
15 327:
#define
AG903_ATA_IRQ_Register_IIRQ_MSK
(0x1UL <<
AG903_ATA_IRQ_Register_IIRQ_POS
) 328:
#define
AG903_ATA_IRQ_Register_txthresh_POS
16 329:
#define
AG903_ATA_IRQ_Register_txthresh_MSK
(0x3ffUL <<
AG903_ATA_IRQ_Register_txthresh_POS
) 330:
#define
AG903_ATA_IRQ_Register_TERMERR_POS
28 331:
#define
AG903_ATA_IRQ_Register_TERMERR_MSK
(0x1UL <<
AG903_ATA_IRQ_Register_TERMERR_POS
) 332:
#define
AG903_ATA_IRQ_Register_AHBERR_POS
29 333:
#define
AG903_ATA_IRQ_Register_AHBERR_MSK
(0x1UL <<
AG903_ATA_IRQ_Register_AHBERR_POS
) 334: 335:
#define
AG903_ATA_Command_Timing_0_T1_POS
0 336:
#define
AG903_ATA_Command_Timing_0_T1_MSK
(0xffUL <<
AG903_ATA_Command_Timing_0_T1_POS
) 337:
#define
AG903_ATA_Command_Timing_0_T2_POS
8 338:
#define
AG903_ATA_Command_Timing_0_T2_MSK
(0xffUL <<
AG903_ATA_Command_Timing_0_T2_POS
) 339:
#define
AG903_ATA_Command_Timing_0_T4_POS
16 340:
#define
AG903_ATA_Command_Timing_0_T4_MSK
(0xffUL <<
AG903_ATA_Command_Timing_0_T4_POS
) 341:
#define
AG903_ATA_Command_Timing_0_TEOC_POS
24 342:
#define
AG903_ATA_Command_Timing_0_TEOC_MSK
(0xffUL <<
AG903_ATA_Command_Timing_0_TEOC_POS
) 343: 344:
#define
AG903_ATA_Data_Timing_PIO_0_T1_POS
0 345:
#define
AG903_ATA_Data_Timing_PIO_0_T1_MSK
(0xffUL <<
AG903_ATA_Data_Timing_PIO_0_T1_POS
) 346:
#define
AG903_ATA_Data_Timing_PIO_0_T2_POS
8 347:
#define
AG903_ATA_Data_Timing_PIO_0_T2_MSK
(0xffUL <<
AG903_ATA_Data_Timing_PIO_0_T2_POS
) 348:
#define
AG903_ATA_Data_Timing_PIO_0_T4_POS
16 349:
#define
AG903_ATA_Data_Timing_PIO_0_T4_MSK
(0xffUL <<
AG903_ATA_Data_Timing_PIO_0_T4_POS
) 350:
#define
AG903_ATA_Data_Timing_PIO_0_TEOC_POS
24 351:
#define
AG903_ATA_Data_Timing_PIO_0_TEOC_MSK
(0xffUL <<
AG903_ATA_Data_Timing_PIO_0_TEOC_POS
) 352: 353:
#define
AG903_ATA_Data_Timing_UDMA_0_TENV_POS
0 354:
#define
AG903_ATA_Data_Timing_UDMA_0_TENV_MSK
(0xfUL <<
AG903_ATA_Data_Timing_UDMA_0_TENV_POS
) 355:
#define
AG903_ATA_Data_Timing_UDMA_0_TMLI_POS
4 356:
#define
AG903_ATA_Data_Timing_UDMA_0_TMLI_MSK
(0xfUL <<
AG903_ATA_Data_Timing_UDMA_0_TMLI_POS
) 357:
#define
AG903_ATA_Data_Timing_UDMA_0_TCYC_POS
8 358:
#define
AG903_ATA_Data_Timing_UDMA_0_TCYC_MSK
(0xffUL <<
AG903_ATA_Data_Timing_UDMA_0_TCYC_POS
) 359:
#define
AG903_ATA_Data_Timing_UDMA_0_TACK_POS
16 360:
#define
AG903_ATA_Data_Timing_UDMA_0_TACK_MSK
(0xfUL <<
AG903_ATA_Data_Timing_UDMA_0_TACK_POS
) 361:
#define
AG903_ATA_Data_Timing_UDMA_0_TCVS_POS
20 362:
#define
AG903_ATA_Data_Timing_UDMA_0_TCVS_MSK
(0xfUL <<
AG903_ATA_Data_Timing_UDMA_0_TCVS_POS
) 363:
#define
AG903_ATA_Data_Timing_UDMA_0_TRP_POS
24 364:
#define
AG903_ATA_Data_Timing_UDMA_0_TRP_MSK
(0xffUL <<
AG903_ATA_Data_Timing_UDMA_0_TRP_POS
) 365: 366:
#define
AG903_ATA_Command_Timing_1_T1_POS
0 367:
#define
AG903_ATA_Command_Timing_1_T1_MSK
(0xffUL <<
AG903_ATA_Command_Timing_1_T1_POS
) 368:
#define
AG903_ATA_Command_Timing_1_T2_POS
8 369:
#define
AG903_ATA_Command_Timing_1_T2_MSK
(0xffUL <<
AG903_ATA_Command_Timing_1_T2_POS
) 370:
#define
AG903_ATA_Command_Timing_1_T4_POS
16 371:
#define
AG903_ATA_Command_Timing_1_T4_MSK
(0xffUL <<
AG903_ATA_Command_Timing_1_T4_POS
) 372:
#define
AG903_ATA_Command_Timing_1_TEOC_POS
24 373:
#define
AG903_ATA_Command_Timing_1_TEOC_MSK
(0xffUL <<
AG903_ATA_Command_Timing_1_TEOC_POS
) 374: 375:
#define
AG903_ATA_Data_Timing_PIO_1_T1_POS
0 376:
#define
AG903_ATA_Data_Timing_PIO_1_T1_MSK
(0xffUL <<
AG903_ATA_Data_Timing_PIO_1_T1_POS
) 377:
#define
AG903_ATA_Data_Timing_PIO_1_T2_POS
8 378:
#define
AG903_ATA_Data_Timing_PIO_1_T2_MSK
(0xffUL <<
AG903_ATA_Data_Timing_PIO_1_T2_POS
) 379:
#define
AG903_ATA_Data_Timing_PIO_1_T4_POS
16 380:
#define
AG903_ATA_Data_Timing_PIO_1_T4_MSK
(0xffUL <<
AG903_ATA_Data_Timing_PIO_1_T4_POS
) 381:
#define
AG903_ATA_Data_Timing_PIO_1_TEOC_POS
24 382:
#define
AG903_ATA_Data_Timing_PIO_1_TEOC_MSK
(0xffUL <<
AG903_ATA_Data_Timing_PIO_1_TEOC_POS
) 383: 384:
#define
AG903_ATA_Data_Timing_UDMA_1_TENV_POS
0 385:
#define
AG903_ATA_Data_Timing_UDMA_1_TENV_MSK
(0xfUL <<
AG903_ATA_Data_Timing_UDMA_1_TENV_POS
) 386:
#define
AG903_ATA_Data_Timing_UDMA_1_TMLI_POS
4 387:
#define
AG903_ATA_Data_Timing_UDMA_1_TMLI_MSK
(0xfUL <<
AG903_ATA_Data_Timing_UDMA_1_TMLI_POS
) 388:
#define
AG903_ATA_Data_Timing_UDMA_1_TCYC_POS
8 389:
#define
AG903_ATA_Data_Timing_UDMA_1_TCYC_MSK
(0xffUL <<
AG903_ATA_Data_Timing_UDMA_1_TCYC_POS
) 390:
#define
AG903_ATA_Data_Timing_UDMA_1_TACK_POS
16 391:
#define
AG903_ATA_Data_Timing_UDMA_1_TACK_MSK
(0xfUL <<
AG903_ATA_Data_Timing_UDMA_1_TACK_POS
) 392:
#define
AG903_ATA_Data_Timing_UDMA_1_TCVS_POS
20 393:
#define
AG903_ATA_Data_Timing_UDMA_1_TCVS_MSK
(0xfUL <<
AG903_ATA_Data_Timing_UDMA_1_TCVS_POS
) 394:
#define
AG903_ATA_Data_Timing_UDMA_1_TRP_POS
24 395:
#define
AG903_ATA_Data_Timing_UDMA_1_TRP_MSK
(0xffUL <<
AG903_ATA_Data_Timing_UDMA_1_TRP_POS
) 396: 397:
#define
AG903_ATA_AHB_Timeout_WRITE_VALUE_POS
0 398:
#define
AG903_ATA_AHB_Timeout_WRITE_VALUE_MSK
(0x7fffUL <<
AG903_ATA_AHB_Timeout_WRITE_VALUE_POS
) 399:
#define
AG903_ATA_AHB_Timeout_WRITE_ENABLE_POS
15 400:
#define
AG903_ATA_AHB_Timeout_WRITE_ENABLE_MSK
(0x1UL <<
AG903_ATA_AHB_Timeout_WRITE_ENABLE_POS
) 401:
#define
AG903_ATA_AHB_Timeout_READ_VALUE_POS
16 402:
#define
AG903_ATA_AHB_Timeout_READ_VALUE_MSK
(0x7fffUL <<
AG903_ATA_AHB_Timeout_READ_VALUE_POS
) 403:
#define
AG903_ATA_AHB_Timeout_READ_ENABLE_POS
31 404:
#define
AG903_ATA_AHB_Timeout_READ_ENABLE_MSK
(0x1UL <<
AG903_ATA_AHB_Timeout_READ_ENABLE_POS
) 405: 406:
#define
AG903_ATA_Feature_CFIFO_CFIFO_DEPTH_POS
0 407:
#define
AG903_ATA_Feature_CFIFO_CFIFO_DEPTH_MSK
(0xffUL <<
AG903_ATA_Feature_CFIFO_CFIFO_DEPTH_POS
) 408:
#define
AG903_ATA_Feature_CFIFO_CFIFO_WIDTH_POS
8 409:
#define
AG903_ATA_Feature_CFIFO_CFIFO_WIDTH_MSK
(0xffUL <<
AG903_ATA_Feature_CFIFO_CFIFO_WIDTH_POS
) 410: 411:
#define
AG903_ATA_Feature_WFIFO_WFIFO_DEPTH_POS
0 412:
#define
AG903_ATA_Feature_WFIFO_WFIFO_DEPTH_MSK
(0xffUL <<
AG903_ATA_Feature_WFIFO_WFIFO_DEPTH_POS
) 413:
#define
AG903_ATA_Feature_WFIFO_WFIFO_WIDTH_POS
8 414:
#define
AG903_ATA_Feature_WFIFO_WFIFO_WIDTH_MSK
(0xffUL <<
AG903_ATA_Feature_WFIFO_WFIFO_WIDTH_POS
) 415: 416:
#define
AG903_ATA_Feature_RFIFO_RFIFO_DEPTH_POS
0 417:
#define
AG903_ATA_Feature_RFIFO_RFIFO_DEPTH_MSK
(0xffUL <<
AG903_ATA_Feature_RFIFO_RFIFO_DEPTH_POS
) 418:
#define
AG903_ATA_Feature_RFIFO_RFIFO_WIDTH_POS
8 419:
#define
AG903_ATA_Feature_RFIFO_RFIFO_WIDTH_MSK
(0xffUL <<
AG903_ATA_Feature_RFIFO_RFIFO_WIDTH_POS
) 420: 421:
#define
AG903_ATA_Revision_REVISION_NUMBER_POS
0 422:
#define
AG903_ATA_Revision_REVISION_NUMBER_MSK
(0xffffffffUL <<
AG903_ATA_Revision_REVISION_NUMBER_POS
) 423: 424:
#endif
425:
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