1: int32_t AG903_OSWprInitMemory(uintptr_t ramtop, uint32_t ramsize)
2: {
3:
4: uint32_t* wp;
5: uint32_t ttbcr, ttbr0, ttbr1;
6: uint32_t loop, cnt;
7: uint32_t l1offset;
8: uint32_t setval;
9: uint8_t ttbcrn;
10:
11:
if( (0>=ramtop) || (0>=ramsize) ||
12: (0xFFFFF&ramtop) || (0xFFFFF&ramsize) ) {
13:
return -
AG903_EINVAL;
14: }
15: OSW_GetTtbInfo(&ttbcr, &ttbr0, &ttbr1);
16: ttbcrn = (uint8_t)(ttbcr&0x03);
17: OswMemMap.ttbr0 = ttbr0&(0xFFFFFF80<<(7-ttbcrn));
18: OswMemMap.ttbr0sz = (0x4000>>ttbcrn);
19: OswMemMap.ttbr1 = ttbr1&0xFFFFFC00;
20: OswMemMap.ttbr1sz = 0x4000;
21: OswMemMap.l2tblsz = 0x1000*((ramsize>>22)+1);
22: OswMemMap.l2tbl = (uintptr_t)(ramtop+ramsize-OswMemMap.l2tblsz);
23: OswMemMap.ramtop = ramtop;
24: OswMemMap.ramend = OswMemMap.l2tbl-1;
25:
26:
27: setval = (ramtop |
AG903_OSW_MEMTYPE_NORMAL_CACHE_ON);
28: cnt = (ramsize>>12);
29: wp = (uint32_t*)OswMemMap.l2tbl;
30:
for(loop=0; loop<cnt; loop++) {
31: (*wp) = setval;
32: setval += 0x1000;
33: wp++;
34: }
35:
36:
37: OSW_CleanDataCache(OswMemMap.ttbr0, OswMemMap.ttbr0sz);
38: OSW_InvalidDataCache(OswMemMap.ttbr0, OswMemMap.ttbr0sz);
39: OSW_CleanDataCache(OswMemMap.ttbr1, OswMemMap.ttbr1sz);
40: OSW_InvalidDataCache(OswMemMap.ttbr1, OswMemMap.ttbr1sz);
41: OSW_CleanDataCache(OswMemMap.l2tbl, OswMemMap.l2tblsz);
42: OSW_InvalidDataCache(OswMemMap.l2tbl, OswMemMap.l2tblsz);
43:
44:
45: setval = (OswMemMap.l2tbl | 0x01);
46: cnt = (ramsize>>20);
47: l1offset = (ramtop>>18);
48:
if(OswMemMap.ttbr0sz > l1offset) {
49: wp = (uint32_t*)(OswMemMap.ttbr0+l1offset);
50: }
51:
else {
52: wp = (uint32_t*)(OswMemMap.ttbr1+(l1offset-OswMemMap.ttbr0sz));
53: }
54:
for(loop=0; loop<cnt; loop++) {
55: (*wp) = setval;
56: setval += 0x400;
57:
if(++wp == (uint32_t*)(OswMemMap.ttbr0+OswMemMap.ttbr0sz)) {
58: wp = (uint32_t*)OswMemMap.ttbr1;
59: }
60: }
61:
62: _kernel_invalid_tlb();
63:
64:
return AG903_ENONE;
65: }