AG903ライブラリリファレンス
内容インデックスホーム
前へ上へ次へ
AG903_smcreg.h

SMC Register Definition

SMC Register Definition

none

AXELL CORPORATION

2017_10_20 Auto-generated.

1: 8: 9: 13: 14: #ifndef _AG903_SMC_REGMAP_H_ 15: #define _AG903_SMC_REGMAP_H_ 16: 17: 18: #include "AG903_regmap.h" 19: 20: #ifndef __I 21: 22: #define __I volatile const 23: #endif 24: #ifndef __O 25: 26: #define __O volatile 27: #endif 28: #ifndef __IO 29: 30: #define __IO volatile 31: #endif 32: 33: 34: typedef struct { 35: 36: union { 37: __IO uint32_t CONFIG_0; 38: 39: struct { 40: __IO uint32_t BNK_MBW : 2; 41: uint32_t : 2; 42: __IO uint32_t BNK_SIZE : 4; 43: __IO uint32_t BNK_TYP3 : 1; 44: __IO uint32_t BNK_TYP2 : 1; 45: __IO uint32_t BNK_TYP1 : 1; 46: __IO uint32_t BNK_WPROT : 1; 47: uint32_t : 3; 48: __IO uint32_t BNK_BASE : 13; 49: __IO uint32_t BNK_EN : 1; 50: } CONFIG_0_bits; 51: }; 52: 53: union { 54: __IO uint32_t TIMING_0; 55: 56: struct { 57: __IO uint32_t TRNA : 4; 58: __IO uint32_t AHT : 2; 59: __IO uint32_t WTC : 2; 60: __IO uint32_t AT2 : 2; 61: uint32_t : 2; 62: __IO uint32_t AT1 : 4; 63: __IO uint32_t CTW : 2; 64: __IO uint32_t AST : 2; 65: __IO uint32_t RBE : 1; 66: uint32_t : 3; 67: __IO uint32_t EAT1 : 4; 68: __IO uint32_t ETRNA : 4; 69: } TIMING_0_bits; 70: }; 71: 72: union { 73: __IO uint32_t CONFIG_1; 74: 75: struct { 76: __IO uint32_t BNK_MBW : 2; 77: uint32_t : 2; 78: __IO uint32_t BNK_SIZE : 4; 79: __IO uint32_t BNK_TYP3 : 1; 80: __IO uint32_t BNK_TYP2 : 1; 81: __IO uint32_t BNK_TYP1 : 1; 82: __IO uint32_t BNK_WPROT : 1; 83: uint32_t : 3; 84: __IO uint32_t BNK_BASE : 13; 85: __IO uint32_t BNK_EN : 1; 86: } CONFIG_1_bits; 87: }; 88: 89: union { 90: __IO uint32_t TIMING_1; 91: 92: struct { 93: __IO uint32_t TRNA : 4; 94: __IO uint32_t AHT : 2; 95: __IO uint32_t WTC : 2; 96: __IO uint32_t AT2 : 2; 97: uint32_t : 2; 98: __IO uint32_t AT1 : 4; 99: __IO uint32_t CTW : 2; 100: __IO uint32_t AST : 2; 101: __IO uint32_t RBE : 1; 102: uint32_t : 3; 103: __IO uint32_t EAT1 : 4; 104: __IO uint32_t ETRNA : 4; 105: } TIMING_1_bits; 106: }; 107: 108: union { 109: __IO uint32_t CONFIG_2; 110: 111: struct { 112: __IO uint32_t BNK_MBW : 2; 113: uint32_t : 2; 114: __IO uint32_t BNK_SIZE : 4; 115: __IO uint32_t BNK_TYP3 : 1; 116: __IO uint32_t BNK_TYP2 : 1; 117: __IO uint32_t BNK_TYP1 : 1; 118: __IO uint32_t BNK_WPROT : 1; 119: uint32_t : 3; 120: __IO uint32_t BNK_BASE : 13; 121: __IO uint32_t BNK_EN : 1; 122: } CONFIG_2_bits; 123: }; 124: 125: union { 126: __IO uint32_t TIMING_2; 127: 128: struct { 129: __IO uint32_t TRNA : 4; 130: __IO uint32_t AHT : 2; 131: __IO uint32_t WTC : 2; 132: __IO uint32_t AT2 : 2; 133: uint32_t : 2; 134: __IO uint32_t AT1 : 4; 135: __IO uint32_t CTW : 2; 136: __IO uint32_t AST : 2; 137: __IO uint32_t RBE : 1; 138: uint32_t : 3; 139: __IO uint32_t EAT1 : 4; 140: __IO uint32_t ETRNA : 4; 141: } TIMING_2_bits; 142: }; 143: 144: union { 145: __IO uint32_t CONFIG_3; 146: 147: struct { 148: __IO uint32_t BNK_MBW : 2; 149: uint32_t : 2; 150: __IO uint32_t BNK_SIZE : 4; 151: __IO uint32_t BNK_TYP3 : 1; 152: __IO uint32_t BNK_TYP2 : 1; 153: __IO uint32_t BNK_TYP1 : 1; 154: __IO uint32_t BNK_WPROT : 1; 155: uint32_t : 3; 156: __IO uint32_t BNK_BASE : 13; 157: __IO uint32_t BNK_EN : 1; 158: } CONFIG_3_bits; 159: }; 160: 161: union { 162: __IO uint32_t TIMING_3; 163: 164: struct { 165: __IO uint32_t TRNA : 4; 166: __IO uint32_t AHT : 2; 167: __IO uint32_t WTC : 2; 168: __IO uint32_t AT2 : 2; 169: uint32_t : 2; 170: __IO uint32_t AT1 : 4; 171: __IO uint32_t CTW : 2; 172: __IO uint32_t AST : 2; 173: __IO uint32_t RBE : 1; 174: uint32_t : 3; 175: __IO uint32_t EAT1 : 4; 176: __IO uint32_t ETRNA : 4; 177: } TIMING_3_bits; 178: }; 179: 180: __I uint32_t RESERVED1[8]; 181: 182: union { 183: __IO uint32_t SHADOW_STATUS; 184: 185: struct { 186: __IO uint32_t SSR_BNKNUM : 3; 187: uint32_t : 1; 188: __IO uint32_t SSR_REQM : 1; 189: __IO uint32_t SSR_REQ : 1; 190: uint32_t : 2; 191: __I uint32_t SSR_STS : 1; 192: } SHADOW_STATUS_bits; 193: }; 194: 195: union { 196: __IO uint32_t EBI_CONTROL; 197: 198: struct { 199: __IO uint32_t EBI_Burst_Control : 1; 200: } EBI_CONTROL_bits; 201: }; 202: 203: __I uint32_t RESERVED2[14]; 204: 205: union { 206: __I uint32_t REVISION; 207: 208: struct { 209: __I uint32_t REV_VER : 8; 210: __I uint32_t MINOR_VER : 8; 211: __I uint32_t MAJOR_VER : 8; 212: } REVISION_bits; 213: }; 214: 215: union { 216: __I uint32_t FEATURE; 217: 218: struct { 219: __I uint32_t EBNK_CNT : 8; 220: __I uint32_t FIFO_DEPTH : 8; 221: __I uint32_t ADC_SKM : 1; 222: } FEATURE_bits; 223: }; 224: 225: 226: }AG903_SMC_Type; 227: 228: #define AG903_SMC ((volatile AG903_SMC_Type *) AG903_SMC_BASE) 229: 230: 231: #define AG903_SMC_CONFIG_0_BNK_MBW_POS 0 232: #define AG903_SMC_CONFIG_0_BNK_MBW_MSK (0x3UL << AG903_SMC_CONFIG_0_BNK_MBW_POS) 233: #define AG903_SMC_CONFIG_0_BNK_SIZE_POS 4 234: #define AG903_SMC_CONFIG_0_BNK_SIZE_MSK (0xfUL << AG903_SMC_CONFIG_0_BNK_SIZE_POS) 235: #define AG903_SMC_CONFIG_0_BNK_TYP3_POS 8 236: #define AG903_SMC_CONFIG_0_BNK_TYP3_MSK (0x1UL << AG903_SMC_CONFIG_0_BNK_TYP3_POS) 237: #define AG903_SMC_CONFIG_0_BNK_TYP2_POS 9 238: #define AG903_SMC_CONFIG_0_BNK_TYP2_MSK (0x1UL << AG903_SMC_CONFIG_0_BNK_TYP2_POS) 239: #define AG903_SMC_CONFIG_0_BNK_TYP1_POS 10 240: #define AG903_SMC_CONFIG_0_BNK_TYP1_MSK (0x1UL << AG903_SMC_CONFIG_0_BNK_TYP1_POS) 241: #define AG903_SMC_CONFIG_0_BNK_WPROT_POS 11 242: #define AG903_SMC_CONFIG_0_BNK_WPROT_MSK (0x1UL << AG903_SMC_CONFIG_0_BNK_WPROT_POS) 243: #define AG903_SMC_CONFIG_0_BNK_BASE_POS 15 244: #define AG903_SMC_CONFIG_0_BNK_BASE_MSK (0x1fffUL << AG903_SMC_CONFIG_0_BNK_BASE_POS) 245: #define AG903_SMC_CONFIG_0_BNK_EN_POS 28 246: #define AG903_SMC_CONFIG_0_BNK_EN_MSK (0x1UL << AG903_SMC_CONFIG_0_BNK_EN_POS) 247: 248: #define AG903_SMC_TIMING_0_TRNA_POS 0 249: #define AG903_SMC_TIMING_0_TRNA_MSK (0xfUL << AG903_SMC_TIMING_0_TRNA_POS) 250: #define AG903_SMC_TIMING_0_AHT_POS 4 251: #define AG903_SMC_TIMING_0_AHT_MSK (0x3UL << AG903_SMC_TIMING_0_AHT_POS) 252: #define AG903_SMC_TIMING_0_WTC_POS 6 253: #define AG903_SMC_TIMING_0_WTC_MSK (0x3UL << AG903_SMC_TIMING_0_WTC_POS) 254: #define AG903_SMC_TIMING_0_AT2_POS 8 255: #define AG903_SMC_TIMING_0_AT2_MSK (0x3UL << AG903_SMC_TIMING_0_AT2_POS) 256: #define AG903_SMC_TIMING_0_AT1_POS 12 257: #define AG903_SMC_TIMING_0_AT1_MSK (0xfUL << AG903_SMC_TIMING_0_AT1_POS) 258: #define AG903_SMC_TIMING_0_CTW_POS 16 259: #define AG903_SMC_TIMING_0_CTW_MSK (0x3UL << AG903_SMC_TIMING_0_CTW_POS) 260: #define AG903_SMC_TIMING_0_AST_POS 18 261: #define AG903_SMC_TIMING_0_AST_MSK (0x3UL << AG903_SMC_TIMING_0_AST_POS) 262: #define AG903_SMC_TIMING_0_RBE_POS 20 263: #define AG903_SMC_TIMING_0_RBE_MSK (0x1UL << AG903_SMC_TIMING_0_RBE_POS) 264: #define AG903_SMC_TIMING_0_EAT1_POS 24 265: #define AG903_SMC_TIMING_0_EAT1_MSK (0xfUL << AG903_SMC_TIMING_0_EAT1_POS) 266: #define AG903_SMC_TIMING_0_ETRNA_POS 28 267: #define AG903_SMC_TIMING_0_ETRNA_MSK (0xfUL << AG903_SMC_TIMING_0_ETRNA_POS) 268: 269: #define AG903_SMC_CONFIG_1_BNK_MBW_POS 0 270: #define AG903_SMC_CONFIG_1_BNK_MBW_MSK (0x3UL << AG903_SMC_CONFIG_1_BNK_MBW_POS) 271: #define AG903_SMC_CONFIG_1_BNK_SIZE_POS 4 272: #define AG903_SMC_CONFIG_1_BNK_SIZE_MSK (0xfUL << AG903_SMC_CONFIG_1_BNK_SIZE_POS) 273: #define AG903_SMC_CONFIG_1_BNK_TYP3_POS 8 274: #define AG903_SMC_CONFIG_1_BNK_TYP3_MSK (0x1UL << AG903_SMC_CONFIG_1_BNK_TYP3_POS) 275: #define AG903_SMC_CONFIG_1_BNK_TYP2_POS 9 276: #define AG903_SMC_CONFIG_1_BNK_TYP2_MSK (0x1UL << AG903_SMC_CONFIG_1_BNK_TYP2_POS) 277: #define AG903_SMC_CONFIG_1_BNK_TYP1_POS 10 278: #define AG903_SMC_CONFIG_1_BNK_TYP1_MSK (0x1UL << AG903_SMC_CONFIG_1_BNK_TYP1_POS) 279: #define AG903_SMC_CONFIG_1_BNK_WPROT_POS 11 280: #define AG903_SMC_CONFIG_1_BNK_WPROT_MSK (0x1UL << AG903_SMC_CONFIG_1_BNK_WPROT_POS) 281: #define AG903_SMC_CONFIG_1_BNK_BASE_POS 15 282: #define AG903_SMC_CONFIG_1_BNK_BASE_MSK (0x1fffUL << AG903_SMC_CONFIG_1_BNK_BASE_POS) 283: #define AG903_SMC_CONFIG_1_BNK_EN_POS 28 284: #define AG903_SMC_CONFIG_1_BNK_EN_MSK (0x1UL << AG903_SMC_CONFIG_1_BNK_EN_POS) 285: 286: #define AG903_SMC_TIMING_1_TRNA_POS 0 287: #define AG903_SMC_TIMING_1_TRNA_MSK (0xfUL << AG903_SMC_TIMING_1_TRNA_POS) 288: #define AG903_SMC_TIMING_1_AHT_POS 4 289: #define AG903_SMC_TIMING_1_AHT_MSK (0x3UL << AG903_SMC_TIMING_1_AHT_POS) 290: #define AG903_SMC_TIMING_1_WTC_POS 6 291: #define AG903_SMC_TIMING_1_WTC_MSK (0x3UL << AG903_SMC_TIMING_1_WTC_POS) 292: #define AG903_SMC_TIMING_1_AT2_POS 8 293: #define AG903_SMC_TIMING_1_AT2_MSK (0x3UL << AG903_SMC_TIMING_1_AT2_POS) 294: #define AG903_SMC_TIMING_1_AT1_POS 12 295: #define AG903_SMC_TIMING_1_AT1_MSK (0xfUL << AG903_SMC_TIMING_1_AT1_POS) 296: #define AG903_SMC_TIMING_1_CTW_POS 16 297: #define AG903_SMC_TIMING_1_CTW_MSK (0x3UL << AG903_SMC_TIMING_1_CTW_POS) 298: #define AG903_SMC_TIMING_1_AST_POS 18 299: #define AG903_SMC_TIMING_1_AST_MSK (0x3UL << AG903_SMC_TIMING_1_AST_POS) 300: #define AG903_SMC_TIMING_1_RBE_POS 20 301: #define AG903_SMC_TIMING_1_RBE_MSK (0x1UL << AG903_SMC_TIMING_1_RBE_POS) 302: #define AG903_SMC_TIMING_1_EAT1_POS 24 303: #define AG903_SMC_TIMING_1_EAT1_MSK (0xfUL << AG903_SMC_TIMING_1_EAT1_POS) 304: #define AG903_SMC_TIMING_1_ETRNA_POS 28 305: #define AG903_SMC_TIMING_1_ETRNA_MSK (0xfUL << AG903_SMC_TIMING_1_ETRNA_POS) 306: 307: #define AG903_SMC_CONFIG_2_BNK_MBW_POS 0 308: #define AG903_SMC_CONFIG_2_BNK_MBW_MSK (0x3UL << AG903_SMC_CONFIG_2_BNK_MBW_POS) 309: #define AG903_SMC_CONFIG_2_BNK_SIZE_POS 4 310: #define AG903_SMC_CONFIG_2_BNK_SIZE_MSK (0xfUL << AG903_SMC_CONFIG_2_BNK_SIZE_POS) 311: #define AG903_SMC_CONFIG_2_BNK_TYP3_POS 8 312: #define AG903_SMC_CONFIG_2_BNK_TYP3_MSK (0x1UL << AG903_SMC_CONFIG_2_BNK_TYP3_POS) 313: #define AG903_SMC_CONFIG_2_BNK_TYP2_POS 9 314: #define AG903_SMC_CONFIG_2_BNK_TYP2_MSK (0x1UL << AG903_SMC_CONFIG_2_BNK_TYP2_POS) 315: #define AG903_SMC_CONFIG_2_BNK_TYP1_POS 10 316: #define AG903_SMC_CONFIG_2_BNK_TYP1_MSK (0x1UL << AG903_SMC_CONFIG_2_BNK_TYP1_POS) 317: #define AG903_SMC_CONFIG_2_BNK_WPROT_POS 11 318: #define AG903_SMC_CONFIG_2_BNK_WPROT_MSK (0x1UL << AG903_SMC_CONFIG_2_BNK_WPROT_POS) 319: #define AG903_SMC_CONFIG_2_BNK_BASE_POS 15 320: #define AG903_SMC_CONFIG_2_BNK_BASE_MSK (0x1fffUL << AG903_SMC_CONFIG_2_BNK_BASE_POS) 321: #define AG903_SMC_CONFIG_2_BNK_EN_POS 28 322: #define AG903_SMC_CONFIG_2_BNK_EN_MSK (0x1UL << AG903_SMC_CONFIG_2_BNK_EN_POS) 323: 324: #define AG903_SMC_TIMING_2_TRNA_POS 0 325: #define AG903_SMC_TIMING_2_TRNA_MSK (0xfUL << AG903_SMC_TIMING_2_TRNA_POS) 326: #define AG903_SMC_TIMING_2_AHT_POS 4 327: #define AG903_SMC_TIMING_2_AHT_MSK (0x3UL << AG903_SMC_TIMING_2_AHT_POS) 328: #define AG903_SMC_TIMING_2_WTC_POS 6 329: #define AG903_SMC_TIMING_2_WTC_MSK (0x3UL << AG903_SMC_TIMING_2_WTC_POS) 330: #define AG903_SMC_TIMING_2_AT2_POS 8 331: #define AG903_SMC_TIMING_2_AT2_MSK (0x3UL << AG903_SMC_TIMING_2_AT2_POS) 332: #define AG903_SMC_TIMING_2_AT1_POS 12 333: #define AG903_SMC_TIMING_2_AT1_MSK (0xfUL << AG903_SMC_TIMING_2_AT1_POS) 334: #define AG903_SMC_TIMING_2_CTW_POS 16 335: #define AG903_SMC_TIMING_2_CTW_MSK (0x3UL << AG903_SMC_TIMING_2_CTW_POS) 336: #define AG903_SMC_TIMING_2_AST_POS 18 337: #define AG903_SMC_TIMING_2_AST_MSK (0x3UL << AG903_SMC_TIMING_2_AST_POS) 338: #define AG903_SMC_TIMING_2_RBE_POS 20 339: #define AG903_SMC_TIMING_2_RBE_MSK (0x1UL << AG903_SMC_TIMING_2_RBE_POS) 340: #define AG903_SMC_TIMING_2_EAT1_POS 24 341: #define AG903_SMC_TIMING_2_EAT1_MSK (0xfUL << AG903_SMC_TIMING_2_EAT1_POS) 342: #define AG903_SMC_TIMING_2_ETRNA_POS 28 343: #define AG903_SMC_TIMING_2_ETRNA_MSK (0xfUL << AG903_SMC_TIMING_2_ETRNA_POS) 344: 345: #define AG903_SMC_CONFIG_3_BNK_MBW_POS 0 346: #define AG903_SMC_CONFIG_3_BNK_MBW_MSK (0x3UL << AG903_SMC_CONFIG_3_BNK_MBW_POS) 347: #define AG903_SMC_CONFIG_3_BNK_SIZE_POS 4 348: #define AG903_SMC_CONFIG_3_BNK_SIZE_MSK (0xfUL << AG903_SMC_CONFIG_3_BNK_SIZE_POS) 349: #define AG903_SMC_CONFIG_3_BNK_TYP3_POS 8 350: #define AG903_SMC_CONFIG_3_BNK_TYP3_MSK (0x1UL << AG903_SMC_CONFIG_3_BNK_TYP3_POS) 351: #define AG903_SMC_CONFIG_3_BNK_TYP2_POS 9 352: #define AG903_SMC_CONFIG_3_BNK_TYP2_MSK (0x1UL << AG903_SMC_CONFIG_3_BNK_TYP2_POS) 353: #define AG903_SMC_CONFIG_3_BNK_TYP1_POS 10 354: #define AG903_SMC_CONFIG_3_BNK_TYP1_MSK (0x1UL << AG903_SMC_CONFIG_3_BNK_TYP1_POS) 355: #define AG903_SMC_CONFIG_3_BNK_WPROT_POS 11 356: #define AG903_SMC_CONFIG_3_BNK_WPROT_MSK (0x1UL << AG903_SMC_CONFIG_3_BNK_WPROT_POS) 357: #define AG903_SMC_CONFIG_3_BNK_BASE_POS 15 358: #define AG903_SMC_CONFIG_3_BNK_BASE_MSK (0x1fffUL << AG903_SMC_CONFIG_3_BNK_BASE_POS) 359: #define AG903_SMC_CONFIG_3_BNK_EN_POS 28 360: #define AG903_SMC_CONFIG_3_BNK_EN_MSK (0x1UL << AG903_SMC_CONFIG_3_BNK_EN_POS) 361: 362: #define AG903_SMC_TIMING_3_TRNA_POS 0 363: #define AG903_SMC_TIMING_3_TRNA_MSK (0xfUL << AG903_SMC_TIMING_3_TRNA_POS) 364: #define AG903_SMC_TIMING_3_AHT_POS 4 365: #define AG903_SMC_TIMING_3_AHT_MSK (0x3UL << AG903_SMC_TIMING_3_AHT_POS) 366: #define AG903_SMC_TIMING_3_WTC_POS 6 367: #define AG903_SMC_TIMING_3_WTC_MSK (0x3UL << AG903_SMC_TIMING_3_WTC_POS) 368: #define AG903_SMC_TIMING_3_AT2_POS 8 369: #define AG903_SMC_TIMING_3_AT2_MSK (0x3UL << AG903_SMC_TIMING_3_AT2_POS) 370: #define AG903_SMC_TIMING_3_AT1_POS 12 371: #define AG903_SMC_TIMING_3_AT1_MSK (0xfUL << AG903_SMC_TIMING_3_AT1_POS) 372: #define AG903_SMC_TIMING_3_CTW_POS 16 373: #define AG903_SMC_TIMING_3_CTW_MSK (0x3UL << AG903_SMC_TIMING_3_CTW_POS) 374: #define AG903_SMC_TIMING_3_AST_POS 18 375: #define AG903_SMC_TIMING_3_AST_MSK (0x3UL << AG903_SMC_TIMING_3_AST_POS) 376: #define AG903_SMC_TIMING_3_RBE_POS 20 377: #define AG903_SMC_TIMING_3_RBE_MSK (0x1UL << AG903_SMC_TIMING_3_RBE_POS) 378: #define AG903_SMC_TIMING_3_EAT1_POS 24 379: #define AG903_SMC_TIMING_3_EAT1_MSK (0xfUL << AG903_SMC_TIMING_3_EAT1_POS) 380: #define AG903_SMC_TIMING_3_ETRNA_POS 28 381: #define AG903_SMC_TIMING_3_ETRNA_MSK (0xfUL << AG903_SMC_TIMING_3_ETRNA_POS) 382: 383: #define AG903_SMC_SHADOW_STATUS_SSR_BNKNUM_POS 0 384: #define AG903_SMC_SHADOW_STATUS_SSR_BNKNUM_MSK (0x7UL << AG903_SMC_SHADOW_STATUS_SSR_BNKNUM_POS) 385: #define AG903_SMC_SHADOW_STATUS_SSR_REQM_POS 4 386: #define AG903_SMC_SHADOW_STATUS_SSR_REQM_MSK (0x1UL << AG903_SMC_SHADOW_STATUS_SSR_REQM_POS) 387: #define AG903_SMC_SHADOW_STATUS_SSR_REQ_POS 5 388: #define AG903_SMC_SHADOW_STATUS_SSR_REQ_MSK (0x1UL << AG903_SMC_SHADOW_STATUS_SSR_REQ_POS) 389: #define AG903_SMC_SHADOW_STATUS_SSR_STS_POS 8 390: #define AG903_SMC_SHADOW_STATUS_SSR_STS_MSK (0x1UL << AG903_SMC_SHADOW_STATUS_SSR_STS_POS) 391: 392: #define AG903_SMC_EBI_CONTROL_EBI_Burst_Control_POS 0 393: #define AG903_SMC_EBI_CONTROL_EBI_Burst_Control_MSK (0x1UL << AG903_SMC_EBI_CONTROL_EBI_Burst_Control_POS) 394: 395: #define AG903_SMC_REVISION_REV_VER_POS 0 396: #define AG903_SMC_REVISION_REV_VER_MSK (0xffUL << AG903_SMC_REVISION_REV_VER_POS) 397: #define AG903_SMC_REVISION_MINOR_VER_POS 8 398: #define AG903_SMC_REVISION_MINOR_VER_MSK (0xffUL << AG903_SMC_REVISION_MINOR_VER_POS) 399: #define AG903_SMC_REVISION_MAJOR_VER_POS 16 400: #define AG903_SMC_REVISION_MAJOR_VER_MSK (0xffUL << AG903_SMC_REVISION_MAJOR_VER_POS) 401: 402: #define AG903_SMC_FEATURE_EBNK_CNT_POS 0 403: #define AG903_SMC_FEATURE_EBNK_CNT_MSK (0xffUL << AG903_SMC_FEATURE_EBNK_CNT_POS) 404: #define AG903_SMC_FEATURE_FIFO_DEPTH_POS 8 405: #define AG903_SMC_FEATURE_FIFO_DEPTH_MSK (0xffUL << AG903_SMC_FEATURE_FIFO_DEPTH_POS) 406: #define AG903_SMC_FEATURE_ADC_SKM_POS 16 407: #define AG903_SMC_FEATURE_ADC_SKM_MSK (0x1UL << AG903_SMC_FEATURE_ADC_SKM_POS) 408: 409: #endif 410:
名前 
説明 
SMC Base Address 
SMCCONFIG_0 BNK_BASE-bit mask 
SMCCONFIG_0 BNK_BASE-bit position 
SMCCONFIG_0 BNK_EN-bit mask 
SMCCONFIG_0 BNK_EN-bit position 
SMCCONFIG_0 BNK_MBW-bit mask 
SMCCONFIG_0 BNK_MBW-bit position 
SMCCONFIG_0 BNK_SIZE-bit mask 
SMCCONFIG_0 BNK_SIZE-bit position 
SMCCONFIG_0 BNK_TYP1-bit mask 
SMCCONFIG_0 BNK_TYP1-bit position 
SMCCONFIG_0 BNK_TYP2-bit mask 
SMCCONFIG_0 BNK_TYP2-bit position 
SMCCONFIG_0 BNK_TYP3-bit mask 
SMCCONFIG_0 BNK_TYP3-bit position 
SMCCONFIG_0 BNK_WPROT-bit mask 
SMCCONFIG_0 BNK_WPROT-bit position 
SMCCONFIG_1 BNK_BASE-bit mask 
SMCCONFIG_1 BNK_BASE-bit position 
SMCCONFIG_1 BNK_EN-bit mask 
SMCCONFIG_1 BNK_EN-bit position 
SMCCONFIG_1 BNK_MBW-bit mask 
SMCCONFIG_1 BNK_MBW-bit position 
SMCCONFIG_1 BNK_SIZE-bit mask 
SMCCONFIG_1 BNK_SIZE-bit position 
SMCCONFIG_1 BNK_TYP1-bit mask 
SMCCONFIG_1 BNK_TYP1-bit position 
SMCCONFIG_1 BNK_TYP2-bit mask 
SMCCONFIG_1 BNK_TYP2-bit position 
SMCCONFIG_1 BNK_TYP3-bit mask 
SMCCONFIG_1 BNK_TYP3-bit position 
SMCCONFIG_1 BNK_WPROT-bit mask 
SMCCONFIG_1 BNK_WPROT-bit position 
SMCCONFIG_2 BNK_BASE-bit mask 
SMCCONFIG_2 BNK_BASE-bit position 
SMCCONFIG_2 BNK_EN-bit mask 
SMCCONFIG_2 BNK_EN-bit position 
SMCCONFIG_2 BNK_MBW-bit mask 
SMCCONFIG_2 BNK_MBW-bit position 
SMCCONFIG_2 BNK_SIZE-bit mask 
SMCCONFIG_2 BNK_SIZE-bit position 
SMCCONFIG_2 BNK_TYP1-bit mask 
SMCCONFIG_2 BNK_TYP1-bit position 
SMCCONFIG_2 BNK_TYP2-bit mask 
SMCCONFIG_2 BNK_TYP2-bit position 
SMCCONFIG_2 BNK_TYP3-bit mask 
SMCCONFIG_2 BNK_TYP3-bit position 
SMCCONFIG_2 BNK_WPROT-bit mask 
SMCCONFIG_2 BNK_WPROT-bit position 
SMCCONFIG_3 BNK_BASE-bit mask 
SMCCONFIG_3 BNK_BASE-bit position 
SMCCONFIG_3 BNK_EN-bit mask 
SMCCONFIG_3 BNK_EN-bit position 
SMCCONFIG_3 BNK_MBW-bit mask 
SMCCONFIG_3 BNK_MBW-bit position 
SMCCONFIG_3 BNK_SIZE-bit mask 
SMCCONFIG_3 BNK_SIZE-bit position 
SMCCONFIG_3 BNK_TYP1-bit mask 
SMCCONFIG_3 BNK_TYP1-bit position 
SMCCONFIG_3 BNK_TYP2-bit mask 
SMCCONFIG_3 BNK_TYP2-bit position 
SMCCONFIG_3 BNK_TYP3-bit mask 
SMCCONFIG_3 BNK_TYP3-bit position 
SMCCONFIG_3 BNK_WPROT-bit mask 
SMCCONFIG_3 BNK_WPROT-bit position 
SMCEBI_CONTROL EBI_Burst_Control-bit mask 
SMCEBI_CONTROL EBI_Burst_Control-bit position 
SMCFEATURE ADC_SKM-bit mask 
SMCFEATURE ADC_SKM-bit position 
SMCFEATURE EBNK_CNT-bit mask 
SMCFEATURE EBNK_CNT-bit position 
SMCFEATURE FIFO_DEPTH-bit mask 
SMCFEATURE FIFO_DEPTH-bit position 
SMCREVISION MAJOR_VER-bit mask 
SMCREVISION MAJOR_VER-bit position 
SMCREVISION MINOR_VER-bit mask 
SMCREVISION MINOR_VER-bit position 
SMCREVISION REV_VER-bit mask 
SMCREVISION REV_VER-bit position 
SMCSHADOW_STATUS SSR_BNKNUM-bit mask 
SMCSHADOW_STATUS SSR_BNKNUM-bit position 
SMCSHADOW_STATUS SSR_REQ-bit mask 
SMCSHADOW_STATUS SSR_REQ-bit position 
SMCSHADOW_STATUS SSR_REQM-bit mask 
SMCSHADOW_STATUS SSR_REQM-bit position 
SMCSHADOW_STATUS SSR_STS-bit mask 
SMCSHADOW_STATUS SSR_STS-bit position 
SMCTIMING_0 AHT-bit mask 
SMCTIMING_0 AHT-bit position 
SMCTIMING_0 AST-bit mask 
SMCTIMING_0 AST-bit position 
SMCTIMING_0 AT1-bit mask 
SMCTIMING_0 AT1-bit position 
SMCTIMING_0 AT2-bit mask 
SMCTIMING_0 AT2-bit position 
SMCTIMING_0 CTW-bit mask 
SMCTIMING_0 CTW-bit position 
SMCTIMING_0 EAT1-bit mask 
SMCTIMING_0 EAT1-bit position 
SMCTIMING_0 ETRNA-bit mask 
SMCTIMING_0 ETRNA-bit position 
SMCTIMING_0 RBE-bit mask 
SMCTIMING_0 RBE-bit position 
SMCTIMING_0 TRNA-bit mask 
SMCTIMING_0 TRNA-bit position 
SMCTIMING_0 WTC-bit mask 
SMCTIMING_0 WTC-bit position 
SMCTIMING_1 AHT-bit mask 
SMCTIMING_1 AHT-bit position 
SMCTIMING_1 AST-bit mask 
SMCTIMING_1 AST-bit position 
SMCTIMING_1 AT1-bit mask 
SMCTIMING_1 AT1-bit position 
SMCTIMING_1 AT2-bit mask 
SMCTIMING_1 AT2-bit position 
SMCTIMING_1 CTW-bit mask 
SMCTIMING_1 CTW-bit position 
SMCTIMING_1 EAT1-bit mask 
SMCTIMING_1 EAT1-bit position 
SMCTIMING_1 ETRNA-bit mask 
SMCTIMING_1 ETRNA-bit position 
SMCTIMING_1 RBE-bit mask 
SMCTIMING_1 RBE-bit position 
SMCTIMING_1 TRNA-bit mask 
SMCTIMING_1 TRNA-bit position 
SMCTIMING_1 WTC-bit mask 
SMCTIMING_1 WTC-bit position 
SMCTIMING_2 AHT-bit mask 
SMCTIMING_2 AHT-bit position 
SMCTIMING_2 AST-bit mask 
SMCTIMING_2 AST-bit position 
SMCTIMING_2 AT1-bit mask 
SMCTIMING_2 AT1-bit position 
SMCTIMING_2 AT2-bit mask 
SMCTIMING_2 AT2-bit position 
SMCTIMING_2 CTW-bit mask 
SMCTIMING_2 CTW-bit position 
SMCTIMING_2 EAT1-bit mask 
SMCTIMING_2 EAT1-bit position 
SMCTIMING_2 ETRNA-bit mask 
SMCTIMING_2 ETRNA-bit position 
SMCTIMING_2 RBE-bit mask 
SMCTIMING_2 RBE-bit position 
SMCTIMING_2 TRNA-bit mask 
SMCTIMING_2 TRNA-bit position 
SMCTIMING_2 WTC-bit mask 
SMCTIMING_2 WTC-bit position 
SMCTIMING_3 AHT-bit mask 
SMCTIMING_3 AHT-bit position 
SMCTIMING_3 AST-bit mask 
SMCTIMING_3 AST-bit position 
SMCTIMING_3 AT1-bit mask 
SMCTIMING_3 AT1-bit position 
SMCTIMING_3 AT2-bit mask 
SMCTIMING_3 AT2-bit position 
SMCTIMING_3 CTW-bit mask 
SMCTIMING_3 CTW-bit position 
SMCTIMING_3 EAT1-bit mask 
SMCTIMING_3 EAT1-bit position 
SMCTIMING_3 ETRNA-bit mask 
SMCTIMING_3 ETRNA-bit position 
SMCTIMING_3 RBE-bit mask 
SMCTIMING_3 RBE-bit position 
SMCTIMING_3 TRNA-bit mask 
SMCTIMING_3 TRNA-bit position 
SMCTIMING_3 WTC-bit mask 
SMCTIMING_3 WTC-bit position 
名前 
説明 
SMC Type 
Copyright (c) 2017-2025 Axell Corporation. All rights reserved.