AG903ライブラリリファレンス
Body Source
AG903_dspreg.h
本文ソース
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1: 8: 9: 13: 14:
#ifndef
_AG903_DSP_REGMAP_H_ 15:
#define
_AG903_DSP_REGMAP_H_ 16: 17: 18:
#include
"AG903_regmap.h" 19: 20:
#ifndef
__I
21: 22:
#define
__I
volatile
const
23:
#endif
24:
#ifndef
__O
25: 26:
#define
__O
volatile
27:
#endif
28:
#ifndef
__IO
29: 30:
#define
__IO
volatile
31:
#endif
32: 33: 34:
typedef
struct
{ 35: 36:
union
{ 37:
__IO
uint32_t CTRL; 38: 39:
struct
{ 40:
__IO
uint32_t DON : 1; 41: } CTRL_bits; 42: }; 43: 44:
union
{ 45:
__IO
uint32_t MOD; 46: 47:
struct
{ 48:
__IO
uint32_t DE : 1; 49: uint32_t : 7; 50:
__IO
uint32_t IP : 1; 51: uint32_t : 7; 52:
__IO
uint32_t UPD : 2; 53:
__IO
uint32_t BMR : 1; 54: uint32_t : 5; 55:
__IO
uint32_t LUT : 1; 56:
__IO
uint32_t DITH : 1; 57: } MOD_bits; 58: }; 59: 60:
union
{ 61:
__IO
uint32_t SYNC; 62: 63:
struct
{ 64:
__IO
uint32_t SEL : 5; 65: uint32_t : 3; 66:
__IO
uint32_t DLY : 1; 67: uint32_t : 7; 68:
__IO
uint32_t IP : 1; 69:
__IO
uint32_t VP : 1; 70:
__IO
uint32_t FP : 1; 71: uint32_t : 5; 72:
__IO
uint32_t MSK : 1; 73: } SYNC_bits; 74: }; 75: 76:
union
{ 77:
__IO
uint32_t BGCOL; 78: 79:
struct
{ 80:
__IO
uint32_t B : 8; 81:
__IO
uint32_t G : 8; 82:
__IO
uint32_t R : 8; 83:
__IO
uint32_t A : 8; 84: } BGCOL_bits; 85: }; 86: 87:
union
{ 88:
__IO
uint32_t WINNUM; 89: 90:
struct
{ 91:
__IO
uint32_t CONF : 5; 92: uint32_t : 11; 93:
__IO
uint32_t ACT : 5; 94: } WINNUM_bits; 95: }; 96: 97:
union
{ 98:
__IO
uint32_t WATNUM; 99: 100:
struct
{ 101:
__IO
uint32_t NUM : 8; 102: } WATNUM_bits; 103: }; 104: 105:
union
{ 106:
__IO
uint32_t WATBASE; 107: 108:
struct
{ 109: uint32_t : 3; 110:
__IO
uint32_t ADDR : 29; 111: } WATBASE_bits; 112: }; 113: 114:
union
{ 115:
__IO
uint32_t LSTCTRL; 116: 117:
struct
{ 118:
__IO
uint32_t WAT : 1; 119: uint32_t : 15; 120:
__IO
uint32_t PAL : 1; 121: } LSTCTRL_bits; 122: }; 123: 124:
union
{ 125:
__IO
uint32_t HRZPRM0; 126: 127:
struct
{ 128:
__IO
uint32_t HPW : 11; 129: } HRZPRM0_bits; 130: }; 131: 132:
union
{ 133:
__IO
uint32_t HRZPRM1; 134: 135:
struct
{ 136:
__IO
uint32_t HBP : 11; 137: uint32_t : 5; 138:
__IO
uint32_t HFP : 11; 139: } HRZPRM1_bits; 140: }; 141: 142:
union
{ 143:
__IO
uint32_t VTPRM0; 144: 145:
struct
{ 146:
__IO
uint32_t VPW : 11; 147: uint32_t : 5; 148:
__IO
uint32_t OFP : 1; 149:
__IO
uint32_t OBP : 1; 150:
__IO
uint32_t EFP : 1; 151:
__IO
uint32_t EBP : 1; 152: } VTPRM0_bits; 153: }; 154: 155:
union
{ 156:
__IO
uint32_t VTPRM1; 157: 158:
struct
{ 159:
__IO
uint32_t VBP : 11; 160: uint32_t : 5; 161:
__IO
uint32_t VFP : 11; 162: } VTPRM1_bits; 163: }; 164: 165:
union
{ 166:
__IO
uint32_t FRMSIZE; 167: 168:
struct
{ 169:
__IO
uint32_t HFS : 11; 170: uint32_t : 5; 171:
__IO
uint32_t VFS : 11; 172: } FRMSIZE_bits; 173: }; 174: 175:
__I
uint32_t RESERVED1[1]; 176: 177:
union
{ 178:
__IO
uint32_t CDCTRL; 179: 180:
struct
{ 181:
__IO
uint32_t BE : 1; 182: uint32_t : 7; 183:
__IO
uint32_t GE : 1; 184: uint32_t : 7; 185:
__IO
uint32_t RE : 1; 186: uint32_t : 7; 187:
__IO
uint32_t AE : 1; 188: } CDCTRL_bits; 189: }; 190: 191:
union
{ 192:
__IO
uint32_t COLDET; 193: 194:
struct
{ 195:
__IO
uint32_t B : 8; 196:
__IO
uint32_t G : 8; 197:
__IO
uint32_t R : 8; 198:
__IO
uint32_t A : 8; 199: } COLDET_bits; 200: }; 201: 202:
union
{ 203:
__IO
uint32_t DITHAREA0A; 204: 205:
struct
{ 206:
__IO
uint32_t X0 : 11; 207: uint32_t : 5; 208:
__IO
uint32_t Y0 : 11; 209: } DITHAREA0A_bits; 210: }; 211: 212:
union
{ 213:
__IO
uint32_t DITHAREA0B; 214: 215:
struct
{ 216:
__IO
uint32_t X1 : 11; 217: uint32_t : 5; 218:
__IO
uint32_t Y1 : 11; 219: } DITHAREA0B_bits; 220: }; 221: 222:
union
{ 223:
__IO
uint32_t DITHAREA1A; 224: 225:
struct
{ 226:
__IO
uint32_t X0 : 11; 227: uint32_t : 5; 228:
__IO
uint32_t Y0 : 11; 229: } DITHAREA1A_bits; 230: }; 231: 232:
union
{ 233:
__IO
uint32_t DITHAREA1B; 234: 235:
struct
{ 236:
__IO
uint32_t X1 : 11; 237: uint32_t : 5; 238:
__IO
uint32_t Y1 : 11; 239: } DITHAREA1B_bits; 240: }; 241: 242:
union
{ 243:
__IO
uint32_t DITHAREA2A; 244: 245:
struct
{ 246:
__IO
uint32_t X0 : 11; 247: uint32_t : 5; 248:
__IO
uint32_t Y0 : 11; 249: } DITHAREA2A_bits; 250: }; 251: 252:
union
{ 253:
__IO
uint32_t DITHAREA2B; 254: 255:
struct
{ 256:
__IO
uint32_t X1 : 11; 257: uint32_t : 5; 258:
__IO
uint32_t Y1 : 11; 259: } DITHAREA2B_bits; 260: }; 261: 262:
union
{ 263:
__IO
uint32_t DITHAREA3A; 264: 265:
struct
{ 266:
__IO
uint32_t X0 : 11; 267: uint32_t : 5; 268:
__IO
uint32_t Y0 : 11; 269: } DITHAREA3A_bits; 270: }; 271: 272:
union
{ 273:
__IO
uint32_t DITHAREA3B; 274: 275:
struct
{ 276:
__IO
uint32_t X1 : 11; 277: uint32_t : 5; 278:
__IO
uint32_t Y1 : 11; 279: } DITHAREA3B_bits; 280: }; 281: 282:
union
{ 283:
__I
uint32_t ERRSTAT; 284: 285:
struct
{ 286:
__I
uint32_t LINE : 11; 287: uint32_t : 5; 288:
__I
uint32_t UE : 1; 289: uint32_t : 7; 290:
__I
uint32_t LE : 1; 291:
__I
uint32_t PE : 1; 292: } ERRSTAT_bits; 293: }; 294: 295:
union
{ 296:
__O
uint32_t ERRCLR; 297: 298:
struct
{ 299:
__O
uint32_t LINE : 1; 300: uint32_t : 15; 301:
__O
uint32_t UE : 1; 302: uint32_t : 7; 303:
__O
uint32_t LE : 1; 304:
__O
uint32_t PE : 1; 305: } ERRCLR_bits; 306: }; 307: 308:
union
{ 309:
__IO
uint32_t
INT
; 310: 311:
struct
{ 312:
__IO
uint32_t LINE : 11; 313: uint32_t : 5; 314:
__IO
uint32_t FCNT : 4; 315: uint32_t : 4; 316:
__IO
uint32_t HLINE : 1; 317:
__IO
uint32_t VBLK : 1; 318: } INT_bits; 319: }; 320: 321:
union
{ 322:
__IO
uint32_t TRIGGER; 323: 324:
struct
{ 325:
__IO
uint32_t OUT : 1; 326: uint32_t : 15; 327:
__IO
uint32_t HRZ : 1; 328: uint32_t : 7; 329:
__IO
uint32_t VT : 2; 330: } TRIGGER_bits; 331: }; 332: 333:
union
{ 334:
__I
uint32_t INTSTAT; 335: 336:
struct
{ 337:
__I
uint32_t VBLK : 1; 338: uint32_t : 7; 339:
__I
uint32_t HLINE : 1; 340: uint32_t : 7; 341:
__I
uint32_t DOFF : 1; 342: uint32_t : 7; 343:
__I
uint32_t DREQ : 1; 344: } INTSTAT_bits; 345: }; 346: 347:
union
{ 348:
__O
uint32_t INTCLR; 349: 350:
struct
{ 351:
__O
uint32_t VBLK : 1; 352: uint32_t : 7; 353:
__O
uint32_t HLINE : 1; 354: uint32_t : 7; 355:
__O
uint32_t DOFF : 1; 356: } INTCLR_bits; 357: }; 358: 359:
union
{ 360:
__IO
uint32_t INTMASK; 361: 362:
struct
{ 363:
__IO
uint32_t VBLK : 1; 364: uint32_t : 7; 365:
__IO
uint32_t HLINE : 1; 366: uint32_t : 7; 367:
__IO
uint32_t DOFF : 1; 368: uint32_t : 7; 369:
__IO
uint32_t ERR : 1; 370: } INTMASK_bits; 371: }; 372: 373:
union
{ 374:
__IO
uint32_t DMAREQ; 375: 376:
struct
{ 377:
__IO
uint32_t REQ : 3; 378: } DMAREQ_bits; 379: }; 380: 381:
union
{ 382:
__I
uint32_t HRZSTAT; 383: 384:
struct
{ 385:
__I
uint32_t PIX : 11; 386: uint32_t : 5; 387:
__I
uint32_t STAT : 1; 388: } HRZSTAT_bits; 389: }; 390: 391:
union
{ 392:
__I
uint32_t VTSTAT; 393: 394:
struct
{ 395:
__I
uint32_t LINE : 11; 396: uint32_t : 5; 397:
__I
uint32_t STAT : 1; 398: uint32_t : 7; 399:
__I
uint32_t FCNT : 4; 400: } VTSTAT_bits; 401: }; 402: 403:
__I
uint32_t RESERVED2[30]; 404: 405:
union
{ 406:
__IO
uint32_t LUTR[64]; 407: 408:
struct
{ 409:
__IO
uint32_t R0 : 8; 410:
__IO
uint32_t R1 : 8; 411:
__IO
uint32_t R2 : 8; 412:
__IO
uint32_t R3 : 8; 413: } LUTR_bits[64]; 414: }; 415: 416:
union
{ 417:
__IO
uint32_t LUTG[64]; 418: 419:
struct
{ 420:
__IO
uint32_t G0 : 8; 421:
__IO
uint32_t G1 : 8; 422:
__IO
uint32_t G2 : 8; 423:
__IO
uint32_t G3 : 8; 424: } LUTG_bits[64]; 425: }; 426: 427:
union
{ 428:
__IO
uint32_t LUTB[64]; 429: 430:
struct
{ 431:
__IO
uint32_t B0 : 8; 432:
__IO
uint32_t B1 : 8; 433:
__IO
uint32_t B2 : 8; 434:
__IO
uint32_t B3 : 8; 435: } LUTB_bits[64]; 436: }; 437: 438: 439: }
AG903_DSPn_Type
; 440: 441:
#define
AG903_DSPn
(ch) ((
volatile
AG903_DSPn_Type
*)(
AG903_DSP0_BASE
+ 0x400 * ch)) 442:
#define
AG903_DSPn_CTRL
(ch)
AG903_DSPn
(ch)->CTRL 443:
#define
AG903_DSPn_MOD
(ch)
AG903_DSPn
(ch)->MOD 444:
#define
AG903_DSPn_SYNC
(ch)
AG903_DSPn
(ch)->SYNC 445:
#define
AG903_DSPn_BGCOL
(ch)
AG903_DSPn
(ch)->BGCOL 446:
#define
AG903_DSPn_WINNUM
(ch)
AG903_DSPn
(ch)->WINNUM 447:
#define
AG903_DSPn_WATNUM
(ch)
AG903_DSPn
(ch)->WATNUM 448:
#define
AG903_DSPn_WATBASE
(ch)
AG903_DSPn
(ch)->WATBASE 449:
#define
AG903_DSPn_LSTCTRL
(ch)
AG903_DSPn
(ch)->LSTCTRL 450:
#define
AG903_DSPn_HRZPRM0
(ch)
AG903_DSPn
(ch)->HRZPRM0 451:
#define
AG903_DSPn_HRZPRM1
(ch)
AG903_DSPn
(ch)->HRZPRM1 452:
#define
AG903_DSPn_VTPRM0
(ch)
AG903_DSPn
(ch)->VTPRM0 453:
#define
AG903_DSPn_VTPRM1
(ch)
AG903_DSPn
(ch)->VTPRM1 454:
#define
AG903_DSPn_FRMSIZE
(ch)
AG903_DSPn
(ch)->FRMSIZE 455:
#define
AG903_DSPn_CDCTRL
(ch)
AG903_DSPn
(ch)->CDCTRL 456:
#define
AG903_DSPn_COLDET
(ch)
AG903_DSPn
(ch)->COLDET 457:
#define
AG903_DSPn_DITHAREA0A
(ch)
AG903_DSPn
(ch)->DITHAREA0A 458:
#define
AG903_DSPn_DITHAREA0B
(ch)
AG903_DSPn
(ch)->DITHAREA0B 459:
#define
AG903_DSPn_DITHAREA1A
(ch)
AG903_DSPn
(ch)->DITHAREA1A 460:
#define
AG903_DSPn_DITHAREA1B
(ch)
AG903_DSPn
(ch)->DITHAREA1B 461:
#define
AG903_DSPn_DITHAREA2A
(ch)
AG903_DSPn
(ch)->DITHAREA2A 462:
#define
AG903_DSPn_DITHAREA2B
(ch)
AG903_DSPn
(ch)->DITHAREA2B 463:
#define
AG903_DSPn_DITHAREA3A
(ch)
AG903_DSPn
(ch)->DITHAREA3A 464:
#define
AG903_DSPn_DITHAREA3B
(ch)
AG903_DSPn
(ch)->DITHAREA3B 465:
#define
AG903_DSPn_ERRSTAT
(ch)
AG903_DSPn
(ch)->ERRSTAT 466:
#define
AG903_DSPn_ERRCLR
(ch)
AG903_DSPn
(ch)->ERRCLR 467:
#define
AG903_DSPn_INT
(ch)
AG903_DSPn
(ch)->
INT
468:
#define
AG903_DSPn_TRIGGER
(ch)
AG903_DSPn
(ch)->TRIGGER 469:
#define
AG903_DSPn_INTSTAT
(ch)
AG903_DSPn
(ch)->INTSTAT 470:
#define
AG903_DSPn_INTCLR
(ch)
AG903_DSPn
(ch)->INTCLR 471:
#define
AG903_DSPn_INTMASK
(ch)
AG903_DSPn
(ch)->INTMASK 472:
#define
AG903_DSPn_DMAREQ
(ch)
AG903_DSPn
(ch)->DMAREQ 473:
#define
AG903_DSPn_HRZSTAT
(ch)
AG903_DSPn
(ch)->HRZSTAT 474:
#define
AG903_DSPn_VTSTAT
(ch)
AG903_DSPn
(ch)->VTSTAT 475:
#define
AG903_DSPn_LUTR
(ch)
AG903_DSPn
(ch)->LUTR 476:
#define
AG903_DSPn_LUTG
(ch)
AG903_DSPn
(ch)->LUTG 477:
#define
AG903_DSPn_LUTB
(ch)
AG903_DSPn
(ch)->LUTB 478: 479:
#define
AG903_DSP0
((
volatile
AG903_DSPn_Type
*)
AG903_DSP0_BASE
) 480:
#define
AG903_DSP1
((
volatile
AG903_DSPn_Type
*)
AG903_DSP1_BASE
) 481: 482: 483:
#define
AG903_DSPn_CTRL_DON_POS
0 484:
#define
AG903_DSPn_CTRL_DON_MSK
(0x1UL <<
AG903_DSPn_CTRL_DON_POS
) 485: 486:
#define
AG903_DSPn_MOD_DE_POS
0 487:
#define
AG903_DSPn_MOD_DE_MSK
(0x1UL <<
AG903_DSPn_MOD_DE_POS
) 488:
#define
AG903_DSPn_MOD_IP_POS
8 489:
#define
AG903_DSPn_MOD_IP_MSK
(0x1UL <<
AG903_DSPn_MOD_IP_POS
) 490:
#define
AG903_DSPn_MOD_UPD_POS
16 491:
#define
AG903_DSPn_MOD_UPD_MSK
(0x3UL <<
AG903_DSPn_MOD_UPD_POS
) 492:
#define
AG903_DSPn_MOD_BMR_POS
18 493:
#define
AG903_DSPn_MOD_BMR_MSK
(0x1UL <<
AG903_DSPn_MOD_BMR_POS
) 494:
#define
AG903_DSPn_MOD_LUT_POS
24 495:
#define
AG903_DSPn_MOD_LUT_MSK
(0x1UL <<
AG903_DSPn_MOD_LUT_POS
) 496:
#define
AG903_DSPn_MOD_DITH_POS
25 497:
#define
AG903_DSPn_MOD_DITH_MSK
(0x1UL <<
AG903_DSPn_MOD_DITH_POS
) 498: 499:
#define
AG903_DSPn_SYNC_SEL_POS
0 500:
#define
AG903_DSPn_SYNC_SEL_MSK
(0x1fUL <<
AG903_DSPn_SYNC_SEL_POS
) 501:
#define
AG903_DSPn_SYNC_DLY_POS
8 502:
#define
AG903_DSPn_SYNC_DLY_MSK
(0x1UL <<
AG903_DSPn_SYNC_DLY_POS
) 503:
#define
AG903_DSPn_SYNC_IP_POS
16 504:
#define
AG903_DSPn_SYNC_IP_MSK
(0x1UL <<
AG903_DSPn_SYNC_IP_POS
) 505:
#define
AG903_DSPn_SYNC_VP_POS
17 506:
#define
AG903_DSPn_SYNC_VP_MSK
(0x1UL <<
AG903_DSPn_SYNC_VP_POS
) 507:
#define
AG903_DSPn_SYNC_FP_POS
18 508:
#define
AG903_DSPn_SYNC_FP_MSK
(0x1UL <<
AG903_DSPn_SYNC_FP_POS
) 509:
#define
AG903_DSPn_SYNC_MSK_POS
24 510:
#define
AG903_DSPn_SYNC_MSK_MSK
(0x1UL <<
AG903_DSPn_SYNC_MSK_POS
) 511: 512:
#define
AG903_DSPn_BGCOL_B_POS
0 513:
#define
AG903_DSPn_BGCOL_B_MSK
(0xffUL <<
AG903_DSPn_BGCOL_B_POS
) 514:
#define
AG903_DSPn_BGCOL_G_POS
8 515:
#define
AG903_DSPn_BGCOL_G_MSK
(0xffUL <<
AG903_DSPn_BGCOL_G_POS
) 516:
#define
AG903_DSPn_BGCOL_R_POS
16 517:
#define
AG903_DSPn_BGCOL_R_MSK
(0xffUL <<
AG903_DSPn_BGCOL_R_POS
) 518:
#define
AG903_DSPn_BGCOL_A_POS
24 519:
#define
AG903_DSPn_BGCOL_A_MSK
(0xffUL <<
AG903_DSPn_BGCOL_A_POS
) 520: 521:
#define
AG903_DSPn_WINNUM_CONF_POS
0 522:
#define
AG903_DSPn_WINNUM_CONF_MSK
(0x1fUL <<
AG903_DSPn_WINNUM_CONF_POS
) 523:
#define
AG903_DSPn_WINNUM_ACT_POS
16 524:
#define
AG903_DSPn_WINNUM_ACT_MSK
(0x1fUL <<
AG903_DSPn_WINNUM_ACT_POS
) 525: 526:
#define
AG903_DSPn_WATNUM_NUM_POS
0 527:
#define
AG903_DSPn_WATNUM_NUM_MSK
(0xffUL <<
AG903_DSPn_WATNUM_NUM_POS
) 528: 529:
#define
AG903_DSPn_WATBASE_ADDR_POS
3 530:
#define
AG903_DSPn_WATBASE_ADDR_MSK
(0x1fffffffUL <<
AG903_DSPn_WATBASE_ADDR_POS
) 531: 532:
#define
AG903_DSPn_LSTCTRL_WAT_POS
0 533:
#define
AG903_DSPn_LSTCTRL_WAT_MSK
(0x1UL <<
AG903_DSPn_LSTCTRL_WAT_POS
) 534:
#define
AG903_DSPn_LSTCTRL_PAL_POS
16 535:
#define
AG903_DSPn_LSTCTRL_PAL_MSK
(0x1UL <<
AG903_DSPn_LSTCTRL_PAL_POS
) 536: 537:
#define
AG903_DSPn_HRZPRM0_HPW_POS
0 538:
#define
AG903_DSPn_HRZPRM0_HPW_MSK
(0x7ffUL <<
AG903_DSPn_HRZPRM0_HPW_POS
) 539: 540:
#define
AG903_DSPn_HRZPRM1_HBP_POS
0 541:
#define
AG903_DSPn_HRZPRM1_HBP_MSK
(0x7ffUL <<
AG903_DSPn_HRZPRM1_HBP_POS
) 542:
#define
AG903_DSPn_HRZPRM1_HFP_POS
16 543:
#define
AG903_DSPn_HRZPRM1_HFP_MSK
(0x7ffUL <<
AG903_DSPn_HRZPRM1_HFP_POS
) 544: 545:
#define
AG903_DSPn_VTPRM0_VPW_POS
0 546:
#define
AG903_DSPn_VTPRM0_VPW_MSK
(0x7ffUL <<
AG903_DSPn_VTPRM0_VPW_POS
) 547:
#define
AG903_DSPn_VTPRM0_OFP_POS
16 548:
#define
AG903_DSPn_VTPRM0_OFP_MSK
(0x1UL <<
AG903_DSPn_VTPRM0_OFP_POS
) 549:
#define
AG903_DSPn_VTPRM0_OBP_POS
17 550:
#define
AG903_DSPn_VTPRM0_OBP_MSK
(0x1UL <<
AG903_DSPn_VTPRM0_OBP_POS
) 551:
#define
AG903_DSPn_VTPRM0_EFP_POS
18 552:
#define
AG903_DSPn_VTPRM0_EFP_MSK
(0x1UL <<
AG903_DSPn_VTPRM0_EFP_POS
) 553:
#define
AG903_DSPn_VTPRM0_EBP_POS
19 554:
#define
AG903_DSPn_VTPRM0_EBP_MSK
(0x1UL <<
AG903_DSPn_VTPRM0_EBP_POS
) 555: 556:
#define
AG903_DSPn_VTPRM1_VBP_POS
0 557:
#define
AG903_DSPn_VTPRM1_VBP_MSK
(0x7ffUL <<
AG903_DSPn_VTPRM1_VBP_POS
) 558:
#define
AG903_DSPn_VTPRM1_VFP_POS
16 559:
#define
AG903_DSPn_VTPRM1_VFP_MSK
(0x7ffUL <<
AG903_DSPn_VTPRM1_VFP_POS
) 560: 561:
#define
AG903_DSPn_FRMSIZE_HFS_POS
0 562:
#define
AG903_DSPn_FRMSIZE_HFS_MSK
(0x7ffUL <<
AG903_DSPn_FRMSIZE_HFS_POS
) 563:
#define
AG903_DSPn_FRMSIZE_VFS_POS
16 564:
#define
AG903_DSPn_FRMSIZE_VFS_MSK
(0x7ffUL <<
AG903_DSPn_FRMSIZE_VFS_POS
) 565: 566:
#define
AG903_DSPn_CDCTRL_BE_POS
0 567:
#define
AG903_DSPn_CDCTRL_BE_MSK
(0x1UL <<
AG903_DSPn_CDCTRL_BE_POS
) 568:
#define
AG903_DSPn_CDCTRL_GE_POS
8 569:
#define
AG903_DSPn_CDCTRL_GE_MSK
(0x1UL <<
AG903_DSPn_CDCTRL_GE_POS
) 570:
#define
AG903_DSPn_CDCTRL_RE_POS
16 571:
#define
AG903_DSPn_CDCTRL_RE_MSK
(0x1UL <<
AG903_DSPn_CDCTRL_RE_POS
) 572:
#define
AG903_DSPn_CDCTRL_AE_POS
24 573:
#define
AG903_DSPn_CDCTRL_AE_MSK
(0x1UL <<
AG903_DSPn_CDCTRL_AE_POS
) 574: 575:
#define
AG903_DSPn_COLDET_B_POS
0 576:
#define
AG903_DSPn_COLDET_B_MSK
(0xffUL <<
AG903_DSPn_COLDET_B_POS
) 577:
#define
AG903_DSPn_COLDET_G_POS
8 578:
#define
AG903_DSPn_COLDET_G_MSK
(0xffUL <<
AG903_DSPn_COLDET_G_POS
) 579:
#define
AG903_DSPn_COLDET_R_POS
16 580:
#define
AG903_DSPn_COLDET_R_MSK
(0xffUL <<
AG903_DSPn_COLDET_R_POS
) 581:
#define
AG903_DSPn_COLDET_A_POS
24 582:
#define
AG903_DSPn_COLDET_A_MSK
(0xffUL <<
AG903_DSPn_COLDET_A_POS
) 583: 584:
#define
AG903_DSPn_DITHAREA0A_X0_POS
0 585:
#define
AG903_DSPn_DITHAREA0A_X0_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA0A_X0_POS
) 586:
#define
AG903_DSPn_DITHAREA0A_Y0_POS
16 587:
#define
AG903_DSPn_DITHAREA0A_Y0_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA0A_Y0_POS
) 588: 589:
#define
AG903_DSPn_DITHAREA0B_X1_POS
0 590:
#define
AG903_DSPn_DITHAREA0B_X1_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA0B_X1_POS
) 591:
#define
AG903_DSPn_DITHAREA0B_Y1_POS
16 592:
#define
AG903_DSPn_DITHAREA0B_Y1_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA0B_Y1_POS
) 593: 594:
#define
AG903_DSPn_DITHAREA1A_X0_POS
0 595:
#define
AG903_DSPn_DITHAREA1A_X0_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA1A_X0_POS
) 596:
#define
AG903_DSPn_DITHAREA1A_Y0_POS
16 597:
#define
AG903_DSPn_DITHAREA1A_Y0_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA1A_Y0_POS
) 598: 599:
#define
AG903_DSPn_DITHAREA1B_X1_POS
0 600:
#define
AG903_DSPn_DITHAREA1B_X1_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA1B_X1_POS
) 601:
#define
AG903_DSPn_DITHAREA1B_Y1_POS
16 602:
#define
AG903_DSPn_DITHAREA1B_Y1_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA1B_Y1_POS
) 603: 604:
#define
AG903_DSPn_DITHAREA2A_X0_POS
0 605:
#define
AG903_DSPn_DITHAREA2A_X0_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA2A_X0_POS
) 606:
#define
AG903_DSPn_DITHAREA2A_Y0_POS
16 607:
#define
AG903_DSPn_DITHAREA2A_Y0_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA2A_Y0_POS
) 608: 609:
#define
AG903_DSPn_DITHAREA2B_X1_POS
0 610:
#define
AG903_DSPn_DITHAREA2B_X1_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA2B_X1_POS
) 611:
#define
AG903_DSPn_DITHAREA2B_Y1_POS
16 612:
#define
AG903_DSPn_DITHAREA2B_Y1_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA2B_Y1_POS
) 613: 614:
#define
AG903_DSPn_DITHAREA3A_X0_POS
0 615:
#define
AG903_DSPn_DITHAREA3A_X0_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA3A_X0_POS
) 616:
#define
AG903_DSPn_DITHAREA3A_Y0_POS
16 617:
#define
AG903_DSPn_DITHAREA3A_Y0_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA3A_Y0_POS
) 618: 619:
#define
AG903_DSPn_DITHAREA3B_X1_POS
0 620:
#define
AG903_DSPn_DITHAREA3B_X1_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA3B_X1_POS
) 621:
#define
AG903_DSPn_DITHAREA3B_Y1_POS
16 622:
#define
AG903_DSPn_DITHAREA3B_Y1_MSK
(0x7ffUL <<
AG903_DSPn_DITHAREA3B_Y1_POS
) 623: 624:
#define
AG903_DSPn_ERRSTAT_LINE_POS
0 625:
#define
AG903_DSPn_ERRSTAT_LINE_MSK
(0x7ffUL <<
AG903_DSPn_ERRSTAT_LINE_POS
) 626:
#define
AG903_DSPn_ERRSTAT_UE_POS
16 627:
#define
AG903_DSPn_ERRSTAT_UE_MSK
(0x1UL <<
AG903_DSPn_ERRSTAT_UE_POS
) 628:
#define
AG903_DSPn_ERRSTAT_LE_POS
24 629:
#define
AG903_DSPn_ERRSTAT_LE_MSK
(0x1UL <<
AG903_DSPn_ERRSTAT_LE_POS
) 630:
#define
AG903_DSPn_ERRSTAT_PE_POS
25 631:
#define
AG903_DSPn_ERRSTAT_PE_MSK
(0x1UL <<
AG903_DSPn_ERRSTAT_PE_POS
) 632: 633:
#define
AG903_DSPn_ERRCLR_LINE_POS
0 634:
#define
AG903_DSPn_ERRCLR_LINE_MSK
(0x1UL <<
AG903_DSPn_ERRCLR_LINE_POS
) 635:
#define
AG903_DSPn_ERRCLR_UE_POS
16 636:
#define
AG903_DSPn_ERRCLR_UE_MSK
(0x1UL <<
AG903_DSPn_ERRCLR_UE_POS
) 637:
#define
AG903_DSPn_ERRCLR_LE_POS
24 638:
#define
AG903_DSPn_ERRCLR_LE_MSK
(0x1UL <<
AG903_DSPn_ERRCLR_LE_POS
) 639:
#define
AG903_DSPn_ERRCLR_PE_POS
25 640:
#define
AG903_DSPn_ERRCLR_PE_MSK
(0x1UL <<
AG903_DSPn_ERRCLR_PE_POS
) 641: 642:
#define
AG903_DSPn_INT_LINE_POS
0 643:
#define
AG903_DSPn_INT_LINE_MSK
(0x7ffUL <<
AG903_DSPn_INT_LINE_POS
) 644:
#define
AG903_DSPn_INT_FCNT_POS
16 645:
#define
AG903_DSPn_INT_FCNT_MSK
(0xfUL <<
AG903_DSPn_INT_FCNT_POS
) 646:
#define
AG903_DSPn_INT_HLINE_POS
24 647:
#define
AG903_DSPn_INT_HLINE_MSK
(0x1UL <<
AG903_DSPn_INT_HLINE_POS
) 648:
#define
AG903_DSPn_INT_VBLK_POS
25 649:
#define
AG903_DSPn_INT_VBLK_MSK
(0x1UL <<
AG903_DSPn_INT_VBLK_POS
) 650: 651:
#define
AG903_DSPn_TRIGGER_OUT_POS
0 652:
#define
AG903_DSPn_TRIGGER_OUT_MSK
(0x1UL <<
AG903_DSPn_TRIGGER_OUT_POS
) 653:
#define
AG903_DSPn_TRIGGER_HRZ_POS
16 654:
#define
AG903_DSPn_TRIGGER_HRZ_MSK
(0x1UL <<
AG903_DSPn_TRIGGER_HRZ_POS
) 655:
#define
AG903_DSPn_TRIGGER_VT_POS
24 656:
#define
AG903_DSPn_TRIGGER_VT_MSK
(0x3UL <<
AG903_DSPn_TRIGGER_VT_POS
) 657: 658:
#define
AG903_DSPn_INTSTAT_VBLK_POS
0 659:
#define
AG903_DSPn_INTSTAT_VBLK_MSK
(0x1UL <<
AG903_DSPn_INTSTAT_VBLK_POS
) 660:
#define
AG903_DSPn_INTSTAT_HLINE_POS
8 661:
#define
AG903_DSPn_INTSTAT_HLINE_MSK
(0x1UL <<
AG903_DSPn_INTSTAT_HLINE_POS
) 662:
#define
AG903_DSPn_INTSTAT_DOFF_POS
16 663:
#define
AG903_DSPn_INTSTAT_DOFF_MSK
(0x1UL <<
AG903_DSPn_INTSTAT_DOFF_POS
) 664:
#define
AG903_DSPn_INTSTAT_DREQ_POS
24 665:
#define
AG903_DSPn_INTSTAT_DREQ_MSK
(0x1UL <<
AG903_DSPn_INTSTAT_DREQ_POS
) 666: 667:
#define
AG903_DSPn_INTCLR_VBLK_POS
0 668:
#define
AG903_DSPn_INTCLR_VBLK_MSK
(0x1UL <<
AG903_DSPn_INTCLR_VBLK_POS
) 669:
#define
AG903_DSPn_INTCLR_HLINE_POS
8 670:
#define
AG903_DSPn_INTCLR_HLINE_MSK
(0x1UL <<
AG903_DSPn_INTCLR_HLINE_POS
) 671:
#define
AG903_DSPn_INTCLR_DOFF_POS
16 672:
#define
AG903_DSPn_INTCLR_DOFF_MSK
(0x1UL <<
AG903_DSPn_INTCLR_DOFF_POS
) 673: 674:
#define
AG903_DSPn_INTMASK_VBLK_POS
0 675:
#define
AG903_DSPn_INTMASK_VBLK_MSK
(0x1UL <<
AG903_DSPn_INTMASK_VBLK_POS
) 676:
#define
AG903_DSPn_INTMASK_HLINE_POS
8 677:
#define
AG903_DSPn_INTMASK_HLINE_MSK
(0x1UL <<
AG903_DSPn_INTMASK_HLINE_POS
) 678:
#define
AG903_DSPn_INTMASK_DOFF_POS
16 679:
#define
AG903_DSPn_INTMASK_DOFF_MSK
(0x1UL <<
AG903_DSPn_INTMASK_DOFF_POS
) 680:
#define
AG903_DSPn_INTMASK_ERR_POS
24 681:
#define
AG903_DSPn_INTMASK_ERR_MSK
(0x1UL <<
AG903_DSPn_INTMASK_ERR_POS
) 682: 683:
#define
AG903_DSPn_DMAREQ_REQ_POS
0 684:
#define
AG903_DSPn_DMAREQ_REQ_MSK
(0x7UL <<
AG903_DSPn_DMAREQ_REQ_POS
) 685: 686:
#define
AG903_DSPn_HRZSTAT_PIX_POS
0 687:
#define
AG903_DSPn_HRZSTAT_PIX_MSK
(0x7ffUL <<
AG903_DSPn_HRZSTAT_PIX_POS
) 688:
#define
AG903_DSPn_HRZSTAT_STAT_POS
16 689:
#define
AG903_DSPn_HRZSTAT_STAT_MSK
(0x1UL <<
AG903_DSPn_HRZSTAT_STAT_POS
) 690: 691:
#define
AG903_DSPn_VTSTAT_LINE_POS
0 692:
#define
AG903_DSPn_VTSTAT_LINE_MSK
(0x7ffUL <<
AG903_DSPn_VTSTAT_LINE_POS
) 693:
#define
AG903_DSPn_VTSTAT_STAT_POS
16 694:
#define
AG903_DSPn_VTSTAT_STAT_MSK
(0x1UL <<
AG903_DSPn_VTSTAT_STAT_POS
) 695:
#define
AG903_DSPn_VTSTAT_FCNT_POS
24 696:
#define
AG903_DSPn_VTSTAT_FCNT_MSK
(0xfUL <<
AG903_DSPn_VTSTAT_FCNT_POS
) 697: 698:
#define
AG903_DSPn_LUTR_R0_POS
0 699:
#define
AG903_DSPn_LUTR_R0_MSK
(0xffUL <<
AG903_DSPn_LUTR_R0_POS
) 700:
#define
AG903_DSPn_LUTR_R1_POS
8 701:
#define
AG903_DSPn_LUTR_R1_MSK
(0xffUL <<
AG903_DSPn_LUTR_R1_POS
) 702:
#define
AG903_DSPn_LUTR_R2_POS
16 703:
#define
AG903_DSPn_LUTR_R2_MSK
(0xffUL <<
AG903_DSPn_LUTR_R2_POS
) 704:
#define
AG903_DSPn_LUTR_R3_POS
24 705:
#define
AG903_DSPn_LUTR_R3_MSK
(0xffUL <<
AG903_DSPn_LUTR_R3_POS
) 706: 707:
#define
AG903_DSPn_LUTG_G0_POS
0 708:
#define
AG903_DSPn_LUTG_G0_MSK
(0xffUL <<
AG903_DSPn_LUTG_G0_POS
) 709:
#define
AG903_DSPn_LUTG_G1_POS
8 710:
#define
AG903_DSPn_LUTG_G1_MSK
(0xffUL <<
AG903_DSPn_LUTG_G1_POS
) 711:
#define
AG903_DSPn_LUTG_G2_POS
16 712:
#define
AG903_DSPn_LUTG_G2_MSK
(0xffUL <<
AG903_DSPn_LUTG_G2_POS
) 713:
#define
AG903_DSPn_LUTG_G3_POS
24 714:
#define
AG903_DSPn_LUTG_G3_MSK
(0xffUL <<
AG903_DSPn_LUTG_G3_POS
) 715: 716:
#define
AG903_DSPn_LUTB_B0_POS
0 717:
#define
AG903_DSPn_LUTB_B0_MSK
(0xffUL <<
AG903_DSPn_LUTB_B0_POS
) 718:
#define
AG903_DSPn_LUTB_B1_POS
8 719:
#define
AG903_DSPn_LUTB_B1_MSK
(0xffUL <<
AG903_DSPn_LUTB_B1_POS
) 720:
#define
AG903_DSPn_LUTB_B2_POS
16 721:
#define
AG903_DSPn_LUTB_B2_MSK
(0xffUL <<
AG903_DSPn_LUTB_B2_POS
) 722:
#define
AG903_DSPn_LUTB_B3_POS
24 723:
#define
AG903_DSPn_LUTB_B3_MSK
(0xffUL <<
AG903_DSPn_LUTB_B3_POS
) 724: 725:
#endif
726:
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