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AG903_ddrreg.h

DDR Register Definition

DDR Register Definition

none

AXELL CORPORATION

2017_10_20 Auto-generated.

1: 8: 9: 13: 14: #ifndef _AG903_DDR_REGMAP_H_ 15: #define _AG903_DDR_REGMAP_H_ 16: 17: 18: #include "AG903_regmap.h" 19: 20: #ifndef __I 21: 22: #define __I volatile const 23: #endif 24: #ifndef __O 25: 26: #define __O volatile 27: #endif 28: #ifndef __IO 29: 30: #define __IO volatile 31: #endif 32: 33: 34: typedef struct { 35: 36: union { 37: __IO uint32_t MCCR; 38: 39: struct { 40: __IO uint32_t GDS : 3; 41: uint32_t : 1; 42: __IO uint32_t AMTSEL : 2; 43: uint32_t : 2; 44: __IO uint32_t MW : 2; 45: __IO uint32_t ARCI : 3; 46: __IO uint32_t PRCC : 3; 47: __IO uint32_t DDR : 2; 48: __IO uint32_t FE : 1; 49: __IO uint32_t LPDDR : 1; 50: __IO uint32_t DREO : 1; 51: __IO uint32_t CCL : 2; 52: __IO uint32_t WCYC : 4; 53: __IO uint32_t DBER : 1; 54: __IO uint32_t MREF : 1; 55: } MCCR_bits; 56: }; 57: 58: union { 59: __IO uint32_t MCSR; 60: 61: struct { 62: __IO uint32_t INIC : 1; 63: __IO uint32_t MRSC : 1; 64: __IO uint32_t MCSR : 1; 65: __IO uint32_t ESRC : 1; 66: __IO uint32_t REGM : 2; 67: __IO uint32_t ZQCS : 1; 68: __IO uint32_t ZQCL : 1; 69: __I uint32_t INIOK : 1; 70: __I uint32_t INIS : 1; 71: __I uint32_t SREF : 1; 72: __I uint32_t APDS : 1; 73: __I uint32_t ZQCSS : 1; 74: __I uint32_t ZQCLS : 1; 75: __I uint32_t MCQE : 1; 76: __I uint32_t BCQE : 1; 77: __I uint32_t RLF : 1; 78: __I uint32_t WLF : 1; 79: uint32_t : 6; 80: __IO uint32_t WSTA : 1; 81: uint32_t : 6; 82: __IO uint32_t SRST : 1; 83: } MCSR_bits; 84: }; 85: 86: union { 87: __IO uint32_t MRSVR0; 88: 89: struct { 90: __IO uint32_t MR : 14; 91: uint32_t : 2; 92: __IO uint32_t EXTMR : 14; 93: } MRSVR0_bits; 94: }; 95: 96: union { 97: __IO uint32_t MRSVR1; 98: 99: struct { 100: __IO uint32_t EMR2 : 14; 101: uint32_t : 2; 102: __IO uint32_t EMR3 : 14; 103: } MRSVR1_bits; 104: }; 105: 106: union { 107: __IO uint32_t EXRANKR; 108: 109: struct { 110: __IO uint32_t RNK0_SIZE : 3; 111: uint32_t : 1; 112: __IO uint32_t RNK0_TYPE : 3; 113: uint32_t : 1; 114: __IO uint32_t RNK1_SIZE : 3; 115: uint32_t : 1; 116: __IO uint32_t RNK1_TYPE : 3; 117: uint32_t : 1; 118: __IO uint32_t RNK1_EN : 1; 119: uint32_t : 7; 120: __IO uint32_t RNK0_BASE : 8; 121: } EXRANKR_bits; 122: }; 123: 124: union { 125: __IO uint32_t TMPR0; 126: 127: struct { 128: __IO uint32_t TRAS : 5; 129: uint32_t : 3; 130: __IO uint32_t TRC : 6; 131: uint32_t : 2; 132: __IO uint32_t TFAW : 5; 133: uint32_t : 3; 134: __IO uint32_t TRFC : 8; 135: } TMPR0_bits; 136: }; 137: 138: union { 139: __IO uint32_t TMPR1; 140: 141: struct { 142: __IO uint32_t TRCD : 4; 143: __IO uint32_t TRRD : 4; 144: __IO uint32_t TRP : 4; 145: __IO uint32_t TMRD : 4; 146: __IO uint32_t TMOD : 4; 147: __IO uint32_t TWR : 4; 148: __IO uint32_t TRTP : 3; 149: uint32_t : 1; 150: __IO uint32_t TWTR : 3; 151: } TMPR1_bits; 152: }; 153: 154: union { 155: __IO uint32_t TMPR2; 156: 157: struct { 158: __IO uint32_t TREFI : 8; 159: __IO uint32_t TXSR : 8; 160: uint32_t : 8; 161: __IO uint32_t TRTW : 2; 162: __IO uint32_t TRTR : 2; 163: __IO uint32_t TWTW : 2; 164: __IO uint32_t TWTR : 2; 165: } TMPR2_bits; 166: }; 167: 168: union { 169: __IO uint32_t PHYCR0; 170: 171: struct { 172: __IO uint32_t ODTMD : 3; 173: __IO uint32_t DQSB : 1; 174: __IO uint32_t ODTDM : 1; 175: __IO uint32_t DQSLF : 1; 176: __IO uint32_t IO18V : 1; 177: __IO uint32_t ACPD : 1; 178: __IO uint32_t ODTE : 1; 179: __IO uint32_t CMDE : 1; 180: __IO uint32_t CLKE : 1; 181: __IO uint32_t DQRE : 1; 182: __IO uint32_t CPHS : 1; 183: __IO uint32_t PCU : 1; 184: __IO uint32_t SBIAS : 1; 185: __IO uint32_t ADPD : 1; 186: __I uint32_t FLDC : 1; 187: uint32_t : 7; 188: __I uint32_t FLD0 : 1; 189: __I uint32_t FLD1 : 1; 190: __I uint32_t FLD2 : 1; 191: __I uint32_t FLD3 : 1; 192: __I uint32_t FLD4 : 1; 193: __I uint32_t FLD5 : 1; 194: __I uint32_t FLD6 : 1; 195: __I uint32_t FLD7 : 1; 196: } PHYCR0_bits; 197: }; 198: 199: union { 200: __IO uint32_t PHYRDTR; 201: 202: struct { 203: __IO uint32_t DLLSEL0 : 3; 204: uint32_t : 1; 205: __IO uint32_t DLLSEL1 : 3; 206: uint32_t : 1; 207: __IO uint32_t DLLSEL2 : 3; 208: uint32_t : 1; 209: __IO uint32_t DLLSEL3 : 3; 210: uint32_t : 1; 211: __IO uint32_t DLLSEL4 : 3; 212: uint32_t : 1; 213: __IO uint32_t DLLSEL5 : 3; 214: uint32_t : 1; 215: __IO uint32_t DLLSEL6 : 3; 216: uint32_t : 1; 217: __IO uint32_t DLLSEL7 : 3; 218: } PHYRDTR_bits; 219: }; 220: 221: union { 222: __IO uint32_t COMPBLKCR; 223: 224: struct { 225: __IO uint32_t COMP_SEL : 1; 226: __IO uint32_t DIP : 6; 227: __IO uint32_t DIN : 6; 228: __I uint32_t DOP : 6; 229: __I uint32_t DON : 6; 230: } COMPBLKCR_bits; 231: }; 232: 233: union { 234: __IO uint32_t APDCR; 235: 236: struct { 237: __IO uint32_t PDNT : 12; 238: __IO uint32_t PDNE : 1; 239: uint32_t : 3; 240: __IO uint32_t SREFT : 12; 241: __IO uint32_t SREFE : 1; 242: } APDCR_bits; 243: }; 244: 245: union { 246: __IO uint32_t CHARBRA; 247: 248: struct { 249: __IO uint32_t HP : 8; 250: __IO uint32_t BOA : 8; 251: uint32_t : 8; 252: __IO uint32_t GGCNT : 5; 253: uint32_t : 1; 254: __IO uint32_t IRWG : 1; 255: __IO uint32_t RWG : 1; 256: } CHARBRA_bits; 257: }; 258: 259: union { 260: __IO uint32_t CHGNTRA; 261: 262: struct { 263: __IO uint32_t ARB_CNT0 : 5; 264: uint32_t : 3; 265: __IO uint32_t ARB_CNT1 : 5; 266: uint32_t : 3; 267: __IO uint32_t ARB_CNT2 : 5; 268: uint32_t : 3; 269: __IO uint32_t ARB_CNT3 : 5; 270: } CHGNTRA_bits; 271: }; 272: 273: union { 274: __IO uint32_t CHGNTRB; 275: 276: struct { 277: __IO uint32_t ARB_CNT4 : 5; 278: uint32_t : 3; 279: __IO uint32_t ARB_CNT5 : 5; 280: uint32_t : 3; 281: __IO uint32_t ARB_CNT6 : 5; 282: uint32_t : 3; 283: __IO uint32_t ARB_CNT7 : 5; 284: } CHGNTRB_bits; 285: }; 286: 287: union { 288: __IO uint32_t PHYWRTMR; 289: 290: struct { 291: __IO uint32_t TWLAT : 4; 292: __IO uint32_t TWDEN : 2; 293: uint32_t : 10; 294: __IO uint32_t TRDEN : 4; 295: __IO uint32_t TRDLAT : 4; 296: } PHYWRTMR_bits; 297: }; 298: 299: union { 300: __IO uint32_t FLUSHCR; 301: 302: struct { 303: __IO uint32_t CMDFE : 8; 304: __IO uint32_t FINTE : 8; 305: __IO uint32_t DINTE : 1; 306: } FLUSHCR_bits; 307: }; 308: 309: union { 310: __IO uint32_t FLUSHSR; 311: 312: struct { 313: __IO uint32_t FLUSH_DONE : 8; 314: __IO uint32_t DBGHIT : 1; 315: } FLUSHSR_bits; 316: }; 317: 318: union { 319: __IO uint32_t SPLITCR; 320: 321: struct { 322: __IO uint32_t SD0 : 1; 323: __IO uint32_t SD1 : 1; 324: __IO uint32_t SD2 : 1; 325: __IO uint32_t SD3 : 1; 326: __IO uint32_t SD4 : 1; 327: __IO uint32_t SD5 : 1; 328: __IO uint32_t SD6 : 1; 329: __IO uint32_t SD7 : 1; 330: __IO uint32_t HP0 : 2; 331: __IO uint32_t HP1 : 2; 332: __IO uint32_t HP2 : 2; 333: __IO uint32_t HP3 : 2; 334: __IO uint32_t HP4 : 2; 335: __IO uint32_t HP5 : 2; 336: __IO uint32_t HP6 : 2; 337: __IO uint32_t HP7 : 2; 338: } SPLITCR_bits; 339: }; 340: 341: union { 342: __IO uint32_t UPDCR; 343: 344: struct { 345: __IO uint32_t TDLLUP : 8; 346: __IO uint32_t TWLVUP : 8; 347: __IO uint32_t ZQUD : 2; 348: } UPDCR_bits; 349: }; 350: 351: union { 352: __I uint32_t REVR; 353: 354: struct { 355: __I uint32_t REL_VER : 8; 356: __I uint32_t MINOR_VER : 8; 357: __I uint32_t MAJOR_VER : 8; 358: } REVR_bits; 359: }; 360: 361: union { 362: __I uint32_t FEATR1; 363: 364: struct { 365: __I uint32_t CHCNT : 3; 366: __I uint32_t AMON : 3; 367: __I uint32_t MAXMW : 2; 368: __I uint32_t BT0 : 1; 369: __I uint32_t BT1 : 1; 370: __I uint32_t BT2 : 1; 371: __I uint32_t BT3 : 1; 372: __I uint32_t BT4 : 1; 373: __I uint32_t BT5 : 1; 374: __I uint32_t BT6 : 1; 375: __I uint32_t BT7 : 1; 376: __I uint32_t DW0 : 1; 377: __I uint32_t DW1 : 1; 378: __I uint32_t DW2 : 1; 379: __I uint32_t DW3 : 1; 380: __I uint32_t DW4 : 1; 381: __I uint32_t DW5 : 1; 382: __I uint32_t DW6 : 1; 383: __I uint32_t DW7 : 1; 384: __I uint32_t BNKNM : 1; 385: __I uint32_t BNKSW : 1; 386: } FEATR1_bits; 387: }; 388: 389: union { 390: __I uint32_t FEATR2; 391: 392: struct { 393: __I uint32_t CM0 : 2; 394: __I uint32_t SP0 : 1; 395: __I uint32_t CB0 : 1; 396: __I uint32_t CM1 : 2; 397: __I uint32_t SP1 : 1; 398: __I uint32_t CB1 : 1; 399: __I uint32_t CM2 : 2; 400: __I uint32_t SP2 : 1; 401: __I uint32_t CB2 : 1; 402: __I uint32_t CM3 : 2; 403: __I uint32_t SP3 : 1; 404: __I uint32_t CB3 : 1; 405: __I uint32_t CM4 : 2; 406: __I uint32_t SP4 : 1; 407: __I uint32_t CB4 : 1; 408: __I uint32_t CM5 : 2; 409: __I uint32_t SP5 : 1; 410: __I uint32_t CB5 : 1; 411: __I uint32_t CM6 : 2; 412: __I uint32_t SP6 : 1; 413: __I uint32_t CB6 : 1; 414: __I uint32_t CM7 : 2; 415: __I uint32_t SP7 : 1; 416: __I uint32_t CB7 : 1; 417: } FEATR2_bits; 418: }; 419: 420: union { 421: __IO uint32_t UDEFR; 422: }; 423: 424: union { 425: __IO uint32_t WLEVELCR; 426: 427: struct { 428: __IO uint32_t TWL : 8; 429: uint32_t : 8; 430: __IO uint32_t WHD0 : 1; 431: __IO uint32_t WHD1 : 1; 432: __IO uint32_t WHD2 : 1; 433: __IO uint32_t WHD3 : 1; 434: __IO uint32_t WHD4 : 1; 435: __IO uint32_t WHD5 : 1; 436: __IO uint32_t WHD6 : 1; 437: __IO uint32_t WHD7 : 1; 438: __I uint32_t WLP0 : 1; 439: __I uint32_t WLP1 : 1; 440: __I uint32_t WLP2 : 1; 441: __I uint32_t WLP3 : 1; 442: __I uint32_t WLP4 : 1; 443: __I uint32_t WLP5 : 1; 444: __I uint32_t WLP6 : 1; 445: __I uint32_t WLP7 : 1; 446: } WLEVELCR_bits; 447: }; 448: 449: union { 450: __IO uint32_t WLEVELBHR; 451: 452: struct { 453: __IO uint32_t DELAY4 : 7; 454: uint32_t : 1; 455: __IO uint32_t DELAY5 : 7; 456: uint32_t : 1; 457: __IO uint32_t DELAY6 : 7; 458: uint32_t : 1; 459: __IO uint32_t DELAY7 : 7; 460: } WLEVELBHR_bits; 461: }; 462: 463: union { 464: __IO uint32_t WLEVELBLR; 465: 466: struct { 467: __IO uint32_t DELAY0 : 7; 468: uint32_t : 1; 469: __IO uint32_t DELAY1 : 7; 470: uint32_t : 1; 471: __IO uint32_t DELAY2 : 7; 472: uint32_t : 1; 473: __IO uint32_t DELAY3 : 7; 474: } WLEVELBLR_bits; 475: }; 476: 477: union { 478: __IO uint32_t PHYMISCR1; 479: 480: struct { 481: __IO uint32_t RDQS0 : 1; 482: __IO uint32_t WDQS0 : 1; 483: uint32_t : 2; 484: __IO uint32_t RDQS1 : 1; 485: __IO uint32_t WDQS1 : 1; 486: uint32_t : 2; 487: __IO uint32_t RDQS2 : 1; 488: __IO uint32_t WDQS2 : 1; 489: uint32_t : 2; 490: __IO uint32_t RDQS3 : 1; 491: __IO uint32_t WDQS3 : 1; 492: uint32_t : 2; 493: __IO uint32_t RDQS4 : 1; 494: __IO uint32_t WDQS4 : 1; 495: uint32_t : 2; 496: __IO uint32_t RDQS5 : 1; 497: __IO uint32_t WDQS5 : 1; 498: uint32_t : 2; 499: __IO uint32_t RDQS6 : 1; 500: __IO uint32_t WDQS6 : 1; 501: uint32_t : 2; 502: __IO uint32_t RDQS7 : 1; 503: __IO uint32_t WDQS7 : 1; 504: } PHYMISCR1_bits; 505: }; 506: 507: union { 508: __IO uint32_t RLEVELCR; 509: 510: struct { 511: __IO uint32_t RHD0 : 1; 512: __IO uint32_t RHD1 : 1; 513: __IO uint32_t RHD2 : 1; 514: __IO uint32_t RHD3 : 1; 515: __IO uint32_t RHD4 : 1; 516: __IO uint32_t RHD5 : 1; 517: __IO uint32_t RHD6 : 1; 518: __IO uint32_t RHD7 : 1; 519: uint32_t : 16; 520: __I uint32_t RLP0 : 1; 521: __I uint32_t RLP1 : 1; 522: __I uint32_t RLP2 : 1; 523: __I uint32_t RLP3 : 1; 524: __I uint32_t RLP4 : 1; 525: __I uint32_t RLP5 : 1; 526: __I uint32_t RLP6 : 1; 527: __I uint32_t RLP7 : 1; 528: } RLEVELCR_bits; 529: }; 530: 531: union { 532: __IO uint32_t MSDLYCR; 533: 534: struct { 535: __IO uint32_t MSDLY0 : 4; 536: __IO uint32_t MSDLY1 : 4; 537: __IO uint32_t MSDLY2 : 4; 538: __IO uint32_t MSDLY3 : 4; 539: __IO uint32_t MSDLY4 : 4; 540: __IO uint32_t MSDLY5 : 4; 541: __IO uint32_t MSDLY6 : 4; 542: __IO uint32_t MSDLY7 : 4; 543: } MSDLYCR_bits; 544: }; 545: 546: union { 547: __IO uint32_t WRDLLCR; 548: 549: struct { 550: __IO uint32_t WRDLL0 : 3; 551: uint32_t : 1; 552: __IO uint32_t WRDLL1 : 3; 553: uint32_t : 1; 554: __IO uint32_t WRDLL2 : 3; 555: uint32_t : 1; 556: __IO uint32_t WRDLL3 : 3; 557: uint32_t : 1; 558: __IO uint32_t WRDLL4 : 3; 559: uint32_t : 1; 560: __IO uint32_t WRDLL5 : 3; 561: uint32_t : 1; 562: __IO uint32_t WRDLL6 : 3; 563: uint32_t : 1; 564: __IO uint32_t WRDLL7 : 3; 565: } WRDLLCR_bits; 566: }; 567: 568: union { 569: __IO uint32_t TRAFMR; 570: }; 571: 572: union { 573: __I uint32_t CMDCNTR0; 574: }; 575: 576: union { 577: __I uint32_t CMDCNTR1; 578: }; 579: 580: union { 581: __I uint32_t CMDCNTR2; 582: }; 583: 584: union { 585: __I uint32_t CMDCNTR3; 586: }; 587: 588: union { 589: __I uint32_t CMDCNTR4; 590: }; 591: 592: union { 593: __I uint32_t CMDCNTR5; 594: }; 595: 596: union { 597: __I uint32_t CMDCNTR6; 598: }; 599: 600: union { 601: __I uint32_t CMDCNTR7; 602: }; 603: 604: union { 605: __IO uint32_t AHBRPRER1; 606: 607: struct { 608: __IO uint32_t PFV0 : 4; 609: uint32_t : 3; 610: __IO uint32_t LPF0 : 1; 611: __IO uint32_t PFV1 : 5; 612: uint32_t : 2; 613: __IO uint32_t LPF1 : 1; 614: __IO uint32_t PFV2 : 5; 615: uint32_t : 2; 616: __IO uint32_t LPF2 : 1; 617: __IO uint32_t PFV3 : 5; 618: uint32_t : 2; 619: __IO uint32_t LPF3 : 1; 620: } AHBRPRER1_bits; 621: }; 622: 623: union { 624: __IO uint32_t AHBRPRER2; 625: 626: struct { 627: __IO uint32_t PFV4 : 5; 628: uint32_t : 2; 629: __IO uint32_t LPF4 : 1; 630: __IO uint32_t PFV5 : 5; 631: uint32_t : 2; 632: __IO uint32_t LPF5 : 1; 633: __IO uint32_t PFV6 : 5; 634: uint32_t : 2; 635: __IO uint32_t LPF6 : 1; 636: __IO uint32_t PFV7 : 5; 637: uint32_t : 2; 638: __IO uint32_t LPF7 : 1; 639: } AHBRPRER2_bits; 640: }; 641: 642: union { 643: __IO uint32_t INITWCR1; 644: 645: struct { 646: __IO uint32_t WC200US : 20; 647: } INITWCR1_bits; 648: }; 649: 650: union { 651: __IO uint32_t INITWCR2; 652: 653: struct { 654: __IO uint32_t WC500US : 20; 655: } INITWCR2_bits; 656: }; 657: 658: union { 659: __IO uint32_t QOSCR; 660: 661: struct { 662: __IO uint32_t EN : 1; 663: __IO uint32_t PERI : 2; 664: __IO uint32_t IDRW : 1; 665: } QOSCR_bits; 666: }; 667: 668: union { 669: __IO uint32_t QOSCNTRA; 670: 671: struct { 672: __IO uint32_t CMDCNT0 : 8; 673: __IO uint32_t CMDCNT1 : 8; 674: __IO uint32_t CMDCNT2 : 8; 675: __IO uint32_t CMDCNT3 : 8; 676: } QOSCNTRA_bits; 677: }; 678: 679: union { 680: __IO uint32_t QOSCNTRB; 681: 682: struct { 683: __IO uint32_t CMDCNT4 : 8; 684: __IO uint32_t CMDCNT5 : 8; 685: __IO uint32_t CMDCNT6 : 8; 686: __IO uint32_t CMDCNT7 : 8; 687: } QOSCNTRB_bits; 688: }; 689: 690: union { 691: __IO uint32_t QOSCNTRC; 692: 693: struct { 694: __IO uint32_t WCMDCNT0 : 8; 695: __IO uint32_t WCMDCNT1 : 8; 696: __IO uint32_t WCMDCNT2 : 8; 697: __IO uint32_t WCMDCNT3 : 8; 698: } QOSCNTRC_bits; 699: }; 700: 701: union { 702: __IO uint32_t QOSCNTRD; 703: 704: struct { 705: __IO uint32_t WCMDCNT4 : 8; 706: __IO uint32_t WCMDCNT5 : 8; 707: __IO uint32_t WCMDCNT6 : 8; 708: __IO uint32_t WCMDCNT7 : 8; 709: } QOSCNTRD_bits; 710: }; 711: 712: union { 713: __IO uint32_t CHARBRB; 714: 715: struct { 716: __IO uint32_t WHIPRI : 8; 717: __IO uint32_t WBSTORTARB : 8; 718: uint32_t : 8; 719: __IO uint32_t WGGRTCNT : 5; 720: } CHARBRB_bits; 721: }; 722: 723: union { 724: __IO uint32_t CHGNTRC; 725: 726: struct { 727: __IO uint32_t WARBCNT0 : 5; 728: uint32_t : 3; 729: __IO uint32_t WARBCNT1 : 5; 730: uint32_t : 3; 731: __IO uint32_t WARBCNT2 : 5; 732: uint32_t : 3; 733: __IO uint32_t WARBCNT3 : 5; 734: } CHGNTRC_bits; 735: }; 736: 737: union { 738: __IO uint32_t CHGNTRD; 739: 740: struct { 741: __IO uint32_t WARBCNT4 : 5; 742: uint32_t : 3; 743: __IO uint32_t WARBCNT5 : 5; 744: uint32_t : 3; 745: __IO uint32_t WARBCNT6 : 5; 746: uint32_t : 3; 747: __IO uint32_t WARBCNT7 : 5; 748: } CHGNTRD_bits; 749: }; 750: 751: union { 752: __IO uint32_t DBGADR; 753: }; 754: 755: union { 756: __IO uint32_t DBGADMR; 757: }; 758: 759: union { 760: __IO uint32_t DBGWDR; 761: }; 762: 763: union { 764: __IO uint32_t DBGWDMR; 765: }; 766: 767: union { 768: __IO uint32_t DBGMSTR; 769: 770: struct { 771: __IO uint32_t ID : 16; 772: __IO uint32_t CH : 3; 773: __IO uint32_t EX : 1; 774: } DBGMSTR_bits; 775: }; 776: 777: union { 778: __IO uint32_t DBGACCR; 779: 780: struct { 781: __IO uint32_t RWS : 1; 782: __IO uint32_t LSW : 1; 783: } DBGACCR_bits; 784: }; 785: 786: union { 787: __IO uint32_t DBGPCR; 788: 789: struct { 790: __IO uint32_t ADR : 1; 791: __IO uint32_t WD : 1; 792: __IO uint32_t ID : 1; 793: __IO uint32_t CH : 1; 794: __IO uint32_t RW : 1; 795: } DBGPCR_bits; 796: }; 797: 798: union { 799: __IO uint32_t DBGENR; 800: 801: struct { 802: __IO uint32_t EN : 1; 803: } DBGENR_bits; 804: }; 805: 806: union { 807: __I uint32_t DBGADSR; 808: }; 809: 810: union { 811: __I uint32_t DBGWDSR; 812: }; 813: 814: union { 815: __I uint32_t DBGMSTSR; 816: 817: struct { 818: __I uint32_t IDSTATUS : 16; 819: __I uint32_t CHSTATUS : 3; 820: } DBGMSTSR_bits; 821: }; 822: 823: union { 824: __I uint32_t DBGACCSR; 825: 826: struct { 827: __I uint32_t ST : 1; 828: } DBGACCSR_bits; 829: }; 830: 831: __I uint32_t RESERVED1[12]; 832: 833: union { 834: __IO uint32_t PHYRDTFR; 835: 836: struct { 837: __IO uint32_t RD0 : 3; 838: uint32_t : 1; 839: __IO uint32_t RD1 : 3; 840: uint32_t : 1; 841: __IO uint32_t RD2 : 3; 842: uint32_t : 1; 843: __IO uint32_t RD3 : 3; 844: uint32_t : 1; 845: __IO uint32_t RD4 : 3; 846: uint32_t : 1; 847: __IO uint32_t RD5 : 3; 848: uint32_t : 1; 849: __IO uint32_t RD6 : 3; 850: uint32_t : 1; 851: __IO uint32_t RD7 : 3; 852: } PHYRDTFR_bits; 853: }; 854: 855: union { 856: __IO uint32_t PHYMISCR2; 857: 858: struct { 859: __IO uint32_t RDCA : 3; 860: uint32_t : 1; 861: __IO uint32_t RDDT : 3; 862: uint32_t : 1; 863: __IO uint32_t VREF : 3; 864: uint32_t : 1; 865: __IO uint32_t RLEEN : 1; 866: __IO uint32_t RLGEN : 1; 867: __IO uint32_t IO15V : 1; 868: } PHYMISCR2_bits; 869: }; 870: 871: 872: }AG903_DDR_Type; 873: 874: #define AG903_DDR ((volatile AG903_DDR_Type *) AG903_DDR_BASE) 875: 876: 877: #define AG903_DDR_MCCR_GDS_POS 0 878: #define AG903_DDR_MCCR_GDS_MSK (0x7UL << AG903_DDR_MCCR_GDS_POS) 879: #define AG903_DDR_MCCR_AMTSEL_POS 4 880: #define AG903_DDR_MCCR_AMTSEL_MSK (0x3UL << AG903_DDR_MCCR_AMTSEL_POS) 881: #define AG903_DDR_MCCR_MW_POS 8 882: #define AG903_DDR_MCCR_MW_MSK (0x3UL << AG903_DDR_MCCR_MW_POS) 883: #define AG903_DDR_MCCR_ARCI_POS 10 884: #define AG903_DDR_MCCR_ARCI_MSK (0x7UL << AG903_DDR_MCCR_ARCI_POS) 885: #define AG903_DDR_MCCR_PRCC_POS 13 886: #define AG903_DDR_MCCR_PRCC_MSK (0x7UL << AG903_DDR_MCCR_PRCC_POS) 887: #define AG903_DDR_MCCR_DDR_POS 16 888: #define AG903_DDR_MCCR_DDR_MSK (0x3UL << AG903_DDR_MCCR_DDR_POS) 889: #define AG903_DDR_MCCR_FE_POS 18 890: #define AG903_DDR_MCCR_FE_MSK (0x1UL << AG903_DDR_MCCR_FE_POS) 891: #define AG903_DDR_MCCR_LPDDR_POS 19 892: #define AG903_DDR_MCCR_LPDDR_MSK (0x1UL << AG903_DDR_MCCR_LPDDR_POS) 893: #define AG903_DDR_MCCR_DREO_POS 20 894: #define AG903_DDR_MCCR_DREO_MSK (0x1UL << AG903_DDR_MCCR_DREO_POS) 895: #define AG903_DDR_MCCR_CCL_POS 21 896: #define AG903_DDR_MCCR_CCL_MSK (0x3UL << AG903_DDR_MCCR_CCL_POS) 897: #define AG903_DDR_MCCR_WCYC_POS 23 898: #define AG903_DDR_MCCR_WCYC_MSK (0xfUL << AG903_DDR_MCCR_WCYC_POS) 899: #define AG903_DDR_MCCR_DBER_POS 27 900: #define AG903_DDR_MCCR_DBER_MSK (0x1UL << AG903_DDR_MCCR_DBER_POS) 901: #define AG903_DDR_MCCR_MREF_POS 28 902: #define AG903_DDR_MCCR_MREF_MSK (0x1UL << AG903_DDR_MCCR_MREF_POS) 903: 904: #define AG903_DDR_MCSR_INIC_POS 0 905: #define AG903_DDR_MCSR_INIC_MSK (0x1UL << AG903_DDR_MCSR_INIC_POS) 906: #define AG903_DDR_MCSR_MRSC_POS 1 907: #define AG903_DDR_MCSR_MRSC_MSK (0x1UL << AG903_DDR_MCSR_MRSC_POS) 908: #define AG903_DDR_MCSR_MCSR_POS 2 909: #define AG903_DDR_MCSR_MCSR_MSK (0x1UL << AG903_DDR_MCSR_MCSR_POS) 910: #define AG903_DDR_MCSR_ESRC_POS 3 911: #define AG903_DDR_MCSR_ESRC_MSK (0x1UL << AG903_DDR_MCSR_ESRC_POS) 912: #define AG903_DDR_MCSR_REGM_POS 4 913: #define AG903_DDR_MCSR_REGM_MSK (0x3UL << AG903_DDR_MCSR_REGM_POS) 914: #define AG903_DDR_MCSR_ZQCS_POS 6 915: #define AG903_DDR_MCSR_ZQCS_MSK (0x1UL << AG903_DDR_MCSR_ZQCS_POS) 916: #define AG903_DDR_MCSR_ZQCL_POS 7 917: #define AG903_DDR_MCSR_ZQCL_MSK (0x1UL << AG903_DDR_MCSR_ZQCL_POS) 918: #define AG903_DDR_MCSR_INIOK_POS 8 919: #define AG903_DDR_MCSR_INIOK_MSK (0x1UL << AG903_DDR_MCSR_INIOK_POS) 920: #define AG903_DDR_MCSR_INIS_POS 9 921: #define AG903_DDR_MCSR_INIS_MSK (0x1UL << AG903_DDR_MCSR_INIS_POS) 922: #define AG903_DDR_MCSR_SREF_POS 10 923: #define AG903_DDR_MCSR_SREF_MSK (0x1UL << AG903_DDR_MCSR_SREF_POS) 924: #define AG903_DDR_MCSR_APDS_POS 11 925: #define AG903_DDR_MCSR_APDS_MSK (0x1UL << AG903_DDR_MCSR_APDS_POS) 926: #define AG903_DDR_MCSR_ZQCSS_POS 12 927: #define AG903_DDR_MCSR_ZQCSS_MSK (0x1UL << AG903_DDR_MCSR_ZQCSS_POS) 928: #define AG903_DDR_MCSR_ZQCLS_POS 13 929: #define AG903_DDR_MCSR_ZQCLS_MSK (0x1UL << AG903_DDR_MCSR_ZQCLS_POS) 930: #define AG903_DDR_MCSR_MCQE_POS 14 931: #define AG903_DDR_MCSR_MCQE_MSK (0x1UL << AG903_DDR_MCSR_MCQE_POS) 932: #define AG903_DDR_MCSR_BCQE_POS 15 933: #define AG903_DDR_MCSR_BCQE_MSK (0x1UL << AG903_DDR_MCSR_BCQE_POS) 934: #define AG903_DDR_MCSR_RLF_POS 16 935: #define AG903_DDR_MCSR_RLF_MSK (0x1UL << AG903_DDR_MCSR_RLF_POS) 936: #define AG903_DDR_MCSR_WLF_POS 17 937: #define AG903_DDR_MCSR_WLF_MSK (0x1UL << AG903_DDR_MCSR_WLF_POS) 938: #define AG903_DDR_MCSR_WSTA_POS 24 939: #define AG903_DDR_MCSR_WSTA_MSK (0x1UL << AG903_DDR_MCSR_WSTA_POS) 940: #define AG903_DDR_MCSR_SRST_POS 31 941: #define AG903_DDR_MCSR_SRST_MSK (0x1UL << AG903_DDR_MCSR_SRST_POS) 942: 943: #define AG903_DDR_MRSVR0_MR_POS 0 944: #define AG903_DDR_MRSVR0_MR_MSK (0x3fffUL << AG903_DDR_MRSVR0_MR_POS) 945: #define AG903_DDR_MRSVR0_EXTMR_POS 16 946: #define AG903_DDR_MRSVR0_EXTMR_MSK (0x3fffUL << AG903_DDR_MRSVR0_EXTMR_POS) 947: 948: #define AG903_DDR_MRSVR1_EMR2_POS 0 949: #define AG903_DDR_MRSVR1_EMR2_MSK (0x3fffUL << AG903_DDR_MRSVR1_EMR2_POS) 950: #define AG903_DDR_MRSVR1_EMR3_POS 16 951: #define AG903_DDR_MRSVR1_EMR3_MSK (0x3fffUL << AG903_DDR_MRSVR1_EMR3_POS) 952: 953: #define AG903_DDR_EXRANKR_RNK0_SIZE_POS 0 954: #define AG903_DDR_EXRANKR_RNK0_SIZE_MSK (0x7UL << AG903_DDR_EXRANKR_RNK0_SIZE_POS) 955: #define AG903_DDR_EXRANKR_RNK0_TYPE_POS 4 956: #define AG903_DDR_EXRANKR_RNK0_TYPE_MSK (0x7UL << AG903_DDR_EXRANKR_RNK0_TYPE_POS) 957: #define AG903_DDR_EXRANKR_RNK1_SIZE_POS 8 958: #define AG903_DDR_EXRANKR_RNK1_SIZE_MSK (0x7UL << AG903_DDR_EXRANKR_RNK1_SIZE_POS) 959: #define AG903_DDR_EXRANKR_RNK1_TYPE_POS 12 960: #define AG903_DDR_EXRANKR_RNK1_TYPE_MSK (0x7UL << AG903_DDR_EXRANKR_RNK1_TYPE_POS) 961: #define AG903_DDR_EXRANKR_RNK1_EN_POS 16 962: #define AG903_DDR_EXRANKR_RNK1_EN_MSK (0x1UL << AG903_DDR_EXRANKR_RNK1_EN_POS) 963: #define AG903_DDR_EXRANKR_RNK0_BASE_POS 24 964: #define AG903_DDR_EXRANKR_RNK0_BASE_MSK (0xffUL << AG903_DDR_EXRANKR_RNK0_BASE_POS) 965: 966: #define AG903_DDR_TMPR0_TRAS_POS 0 967: #define AG903_DDR_TMPR0_TRAS_MSK (0x1fUL << AG903_DDR_TMPR0_TRAS_POS) 968: #define AG903_DDR_TMPR0_TRC_POS 8 969: #define AG903_DDR_TMPR0_TRC_MSK (0x3fUL << AG903_DDR_TMPR0_TRC_POS) 970: #define AG903_DDR_TMPR0_TFAW_POS 16 971: #define AG903_DDR_TMPR0_TFAW_MSK (0x1fUL << AG903_DDR_TMPR0_TFAW_POS) 972: #define AG903_DDR_TMPR0_TRFC_POS 24 973: #define AG903_DDR_TMPR0_TRFC_MSK (0xffUL << AG903_DDR_TMPR0_TRFC_POS) 974: 975: #define AG903_DDR_TMPR1_TRCD_POS 0 976: #define AG903_DDR_TMPR1_TRCD_MSK (0xfUL << AG903_DDR_TMPR1_TRCD_POS) 977: #define AG903_DDR_TMPR1_TRRD_POS 4 978: #define AG903_DDR_TMPR1_TRRD_MSK (0xfUL << AG903_DDR_TMPR1_TRRD_POS) 979: #define AG903_DDR_TMPR1_TRP_POS 8 980: #define AG903_DDR_TMPR1_TRP_MSK (0xfUL << AG903_DDR_TMPR1_TRP_POS) 981: #define AG903_DDR_TMPR1_TMRD_POS 12 982: #define AG903_DDR_TMPR1_TMRD_MSK (0xfUL << AG903_DDR_TMPR1_TMRD_POS) 983: #define AG903_DDR_TMPR1_TMOD_POS 16 984: #define AG903_DDR_TMPR1_TMOD_MSK (0xfUL << AG903_DDR_TMPR1_TMOD_POS) 985: #define AG903_DDR_TMPR1_TWR_POS 20 986: #define AG903_DDR_TMPR1_TWR_MSK (0xfUL << AG903_DDR_TMPR1_TWR_POS) 987: #define AG903_DDR_TMPR1_TRTP_POS 24 988: #define AG903_DDR_TMPR1_TRTP_MSK (0x7UL << AG903_DDR_TMPR1_TRTP_POS) 989: #define AG903_DDR_TMPR1_TWTR_POS 28 990: #define AG903_DDR_TMPR1_TWTR_MSK (0x7UL << AG903_DDR_TMPR1_TWTR_POS) 991: 992: #define AG903_DDR_TMPR2_TREFI_POS 0 993: #define AG903_DDR_TMPR2_TREFI_MSK (0xffUL << AG903_DDR_TMPR2_TREFI_POS) 994: #define AG903_DDR_TMPR2_TXSR_POS 8 995: #define AG903_DDR_TMPR2_TXSR_MSK (0xffUL << AG903_DDR_TMPR2_TXSR_POS) 996: #define AG903_DDR_TMPR2_TRTW_POS 24 997: #define AG903_DDR_TMPR2_TRTW_MSK (0x3UL << AG903_DDR_TMPR2_TRTW_POS) 998: #define AG903_DDR_TMPR2_TRTR_POS 26 999: #define AG903_DDR_TMPR2_TRTR_MSK (0x3UL << AG903_DDR_TMPR2_TRTR_POS) 1000: #define AG903_DDR_TMPR2_TWTW_POS 28 1001: #define AG903_DDR_TMPR2_TWTW_MSK (0x3UL << AG903_DDR_TMPR2_TWTW_POS) 1002: #define AG903_DDR_TMPR2_TWTR_POS 30 1003: #define AG903_DDR_TMPR2_TWTR_MSK (0x3UL << AG903_DDR_TMPR2_TWTR_POS) 1004: 1005: #define AG903_DDR_PHYCR0_ODTMD_POS 0 1006: #define AG903_DDR_PHYCR0_ODTMD_MSK (0x7UL << AG903_DDR_PHYCR0_ODTMD_POS) 1007: #define AG903_DDR_PHYCR0_DQSB_POS 3 1008: #define AG903_DDR_PHYCR0_DQSB_MSK (0x1UL << AG903_DDR_PHYCR0_DQSB_POS) 1009: #define AG903_DDR_PHYCR0_ODTDM_POS 4 1010: #define AG903_DDR_PHYCR0_ODTDM_MSK (0x1UL << AG903_DDR_PHYCR0_ODTDM_POS) 1011: #define AG903_DDR_PHYCR0_DQSLF_POS 5 1012: #define AG903_DDR_PHYCR0_DQSLF_MSK (0x1UL << AG903_DDR_PHYCR0_DQSLF_POS) 1013: #define AG903_DDR_PHYCR0_IO18V_POS 6 1014: #define AG903_DDR_PHYCR0_IO18V_MSK (0x1UL << AG903_DDR_PHYCR0_IO18V_POS) 1015: #define AG903_DDR_PHYCR0_ACPD_POS 7 1016: #define AG903_DDR_PHYCR0_ACPD_MSK (0x1UL << AG903_DDR_PHYCR0_ACPD_POS) 1017: #define AG903_DDR_PHYCR0_ODTE_POS 8 1018: #define AG903_DDR_PHYCR0_ODTE_MSK (0x1UL << AG903_DDR_PHYCR0_ODTE_POS) 1019: #define AG903_DDR_PHYCR0_CMDE_POS 9 1020: #define AG903_DDR_PHYCR0_CMDE_MSK (0x1UL << AG903_DDR_PHYCR0_CMDE_POS) 1021: #define AG903_DDR_PHYCR0_CLKE_POS 10 1022: #define AG903_DDR_PHYCR0_CLKE_MSK (0x1UL << AG903_DDR_PHYCR0_CLKE_POS) 1023: #define AG903_DDR_PHYCR0_DQRE_POS 11 1024: #define AG903_DDR_PHYCR0_DQRE_MSK (0x1UL << AG903_DDR_PHYCR0_DQRE_POS) 1025: #define AG903_DDR_PHYCR0_CPHS_POS 12 1026: #define AG903_DDR_PHYCR0_CPHS_MSK (0x1UL << AG903_DDR_PHYCR0_CPHS_POS) 1027: #define AG903_DDR_PHYCR0_PCU_POS 13 1028: #define AG903_DDR_PHYCR0_PCU_MSK (0x1UL << AG903_DDR_PHYCR0_PCU_POS) 1029: #define AG903_DDR_PHYCR0_SBIAS_POS 14 1030: #define AG903_DDR_PHYCR0_SBIAS_MSK (0x1UL << AG903_DDR_PHYCR0_SBIAS_POS) 1031: #define AG903_DDR_PHYCR0_ADPD_POS 15 1032: #define AG903_DDR_PHYCR0_ADPD_MSK (0x1UL << AG903_DDR_PHYCR0_ADPD_POS) 1033: #define AG903_DDR_PHYCR0_FLDC_POS 16 1034: #define AG903_DDR_PHYCR0_FLDC_MSK (0x1UL << AG903_DDR_PHYCR0_FLDC_POS) 1035: #define AG903_DDR_PHYCR0_FLD0_POS 24 1036: #define AG903_DDR_PHYCR0_FLD0_MSK (0x1UL << AG903_DDR_PHYCR0_FLD0_POS) 1037: #define AG903_DDR_PHYCR0_FLD1_POS 25 1038: #define AG903_DDR_PHYCR0_FLD1_MSK (0x1UL << AG903_DDR_PHYCR0_FLD1_POS) 1039: #define AG903_DDR_PHYCR0_FLD2_POS 26 1040: #define AG903_DDR_PHYCR0_FLD2_MSK (0x1UL << AG903_DDR_PHYCR0_FLD2_POS) 1041: #define AG903_DDR_PHYCR0_FLD3_POS 27 1042: #define AG903_DDR_PHYCR0_FLD3_MSK (0x1UL << AG903_DDR_PHYCR0_FLD3_POS) 1043: #define AG903_DDR_PHYCR0_FLD4_POS 28 1044: #define AG903_DDR_PHYCR0_FLD4_MSK (0x1UL << AG903_DDR_PHYCR0_FLD4_POS) 1045: #define AG903_DDR_PHYCR0_FLD5_POS 29 1046: #define AG903_DDR_PHYCR0_FLD5_MSK (0x1UL << AG903_DDR_PHYCR0_FLD5_POS) 1047: #define AG903_DDR_PHYCR0_FLD6_POS 30 1048: #define AG903_DDR_PHYCR0_FLD6_MSK (0x1UL << AG903_DDR_PHYCR0_FLD6_POS) 1049: #define AG903_DDR_PHYCR0_FLD7_POS 31 1050: #define AG903_DDR_PHYCR0_FLD7_MSK (0x1UL << AG903_DDR_PHYCR0_FLD7_POS) 1051: 1052: #define AG903_DDR_PHYRDTR_DLLSEL0_POS 0 1053: #define AG903_DDR_PHYRDTR_DLLSEL0_MSK (0x7UL << AG903_DDR_PHYRDTR_DLLSEL0_POS) 1054: #define AG903_DDR_PHYRDTR_DLLSEL1_POS 4 1055: #define AG903_DDR_PHYRDTR_DLLSEL1_MSK (0x7UL << AG903_DDR_PHYRDTR_DLLSEL1_POS) 1056: #define AG903_DDR_PHYRDTR_DLLSEL2_POS 8 1057: #define AG903_DDR_PHYRDTR_DLLSEL2_MSK (0x7UL << AG903_DDR_PHYRDTR_DLLSEL2_POS) 1058: #define AG903_DDR_PHYRDTR_DLLSEL3_POS 12 1059: #define AG903_DDR_PHYRDTR_DLLSEL3_MSK (0x7UL << AG903_DDR_PHYRDTR_DLLSEL3_POS) 1060: #define AG903_DDR_PHYRDTR_DLLSEL4_POS 16 1061: #define AG903_DDR_PHYRDTR_DLLSEL4_MSK (0x7UL << AG903_DDR_PHYRDTR_DLLSEL4_POS) 1062: #define AG903_DDR_PHYRDTR_DLLSEL5_POS 20 1063: #define AG903_DDR_PHYRDTR_DLLSEL5_MSK (0x7UL << AG903_DDR_PHYRDTR_DLLSEL5_POS) 1064: #define AG903_DDR_PHYRDTR_DLLSEL6_POS 24 1065: #define AG903_DDR_PHYRDTR_DLLSEL6_MSK (0x7UL << AG903_DDR_PHYRDTR_DLLSEL6_POS) 1066: #define AG903_DDR_PHYRDTR_DLLSEL7_POS 28 1067: #define AG903_DDR_PHYRDTR_DLLSEL7_MSK (0x7UL << AG903_DDR_PHYRDTR_DLLSEL7_POS) 1068: 1069: #define AG903_DDR_COMPBLKCR_COMP_SEL_POS 0 1070: #define AG903_DDR_COMPBLKCR_COMP_SEL_MSK (0x1UL << AG903_DDR_COMPBLKCR_COMP_SEL_POS) 1071: #define AG903_DDR_COMPBLKCR_DIP_POS 1 1072: #define AG903_DDR_COMPBLKCR_DIP_MSK (0x3fUL << AG903_DDR_COMPBLKCR_DIP_POS) 1073: #define AG903_DDR_COMPBLKCR_DIN_POS 7 1074: #define AG903_DDR_COMPBLKCR_DIN_MSK (0x3fUL << AG903_DDR_COMPBLKCR_DIN_POS) 1075: #define AG903_DDR_COMPBLKCR_DOP_POS 13 1076: #define AG903_DDR_COMPBLKCR_DOP_MSK (0x3fUL << AG903_DDR_COMPBLKCR_DOP_POS) 1077: #define AG903_DDR_COMPBLKCR_DON_POS 19 1078: #define AG903_DDR_COMPBLKCR_DON_MSK (0x3fUL << AG903_DDR_COMPBLKCR_DON_POS) 1079: 1080: #define AG903_DDR_APDCR_PDNT_POS 0 1081: #define AG903_DDR_APDCR_PDNT_MSK (0xfffUL << AG903_DDR_APDCR_PDNT_POS) 1082: #define AG903_DDR_APDCR_PDNE_POS 12 1083: #define AG903_DDR_APDCR_PDNE_MSK (0x1UL << AG903_DDR_APDCR_PDNE_POS) 1084: #define AG903_DDR_APDCR_SREFT_POS 16 1085: #define AG903_DDR_APDCR_SREFT_MSK (0xfffUL << AG903_DDR_APDCR_SREFT_POS) 1086: #define AG903_DDR_APDCR_SREFE_POS 28 1087: #define AG903_DDR_APDCR_SREFE_MSK (0x1UL << AG903_DDR_APDCR_SREFE_POS) 1088: 1089: #define AG903_DDR_CHARBRA_HP_POS 0 1090: #define AG903_DDR_CHARBRA_HP_MSK (0xffUL << AG903_DDR_CHARBRA_HP_POS) 1091: #define AG903_DDR_CHARBRA_BOA_POS 8 1092: #define AG903_DDR_CHARBRA_BOA_MSK (0xffUL << AG903_DDR_CHARBRA_BOA_POS) 1093: #define AG903_DDR_CHARBRA_GGCNT_POS 24 1094: #define AG903_DDR_CHARBRA_GGCNT_MSK (0x1fUL << AG903_DDR_CHARBRA_GGCNT_POS) 1095: #define AG903_DDR_CHARBRA_IRWG_POS 30 1096: #define AG903_DDR_CHARBRA_IRWG_MSK (0x1UL << AG903_DDR_CHARBRA_IRWG_POS) 1097: #define AG903_DDR_CHARBRA_RWG_POS 31 1098: #define AG903_DDR_CHARBRA_RWG_MSK (0x1UL << AG903_DDR_CHARBRA_RWG_POS) 1099: 1100: #define AG903_DDR_CHGNTRA_ARB_CNT0_POS 0 1101: #define AG903_DDR_CHGNTRA_ARB_CNT0_MSK (0x1fUL << AG903_DDR_CHGNTRA_ARB_CNT0_POS) 1102: #define AG903_DDR_CHGNTRA_ARB_CNT1_POS 8 1103: #define AG903_DDR_CHGNTRA_ARB_CNT1_MSK (0x1fUL << AG903_DDR_CHGNTRA_ARB_CNT1_POS) 1104: #define AG903_DDR_CHGNTRA_ARB_CNT2_POS 16 1105: #define AG903_DDR_CHGNTRA_ARB_CNT2_MSK (0x1fUL << AG903_DDR_CHGNTRA_ARB_CNT2_POS) 1106: #define AG903_DDR_CHGNTRA_ARB_CNT3_POS 24 1107: #define AG903_DDR_CHGNTRA_ARB_CNT3_MSK (0x1fUL << AG903_DDR_CHGNTRA_ARB_CNT3_POS) 1108: 1109: #define AG903_DDR_CHGNTRB_ARB_CNT4_POS 0 1110: #define AG903_DDR_CHGNTRB_ARB_CNT4_MSK (0x1fUL << AG903_DDR_CHGNTRB_ARB_CNT4_POS) 1111: #define AG903_DDR_CHGNTRB_ARB_CNT5_POS 8 1112: #define AG903_DDR_CHGNTRB_ARB_CNT5_MSK (0x1fUL << AG903_DDR_CHGNTRB_ARB_CNT5_POS) 1113: #define AG903_DDR_CHGNTRB_ARB_CNT6_POS 16 1114: #define AG903_DDR_CHGNTRB_ARB_CNT6_MSK (0x1fUL << AG903_DDR_CHGNTRB_ARB_CNT6_POS) 1115: #define AG903_DDR_CHGNTRB_ARB_CNT7_POS 24 1116: #define AG903_DDR_CHGNTRB_ARB_CNT7_MSK (0x1fUL << AG903_DDR_CHGNTRB_ARB_CNT7_POS) 1117: 1118: #define AG903_DDR_PHYWRTMR_TWLAT_POS 0 1119: #define AG903_DDR_PHYWRTMR_TWLAT_MSK (0xfUL << AG903_DDR_PHYWRTMR_TWLAT_POS) 1120: #define AG903_DDR_PHYWRTMR_TWDEN_POS 4 1121: #define AG903_DDR_PHYWRTMR_TWDEN_MSK (0x3UL << AG903_DDR_PHYWRTMR_TWDEN_POS) 1122: #define AG903_DDR_PHYWRTMR_TRDEN_POS 16 1123: #define AG903_DDR_PHYWRTMR_TRDEN_MSK (0xfUL << AG903_DDR_PHYWRTMR_TRDEN_POS) 1124: #define AG903_DDR_PHYWRTMR_TRDLAT_POS 20 1125: #define AG903_DDR_PHYWRTMR_TRDLAT_MSK (0xfUL << AG903_DDR_PHYWRTMR_TRDLAT_POS) 1126: 1127: #define AG903_DDR_FLUSHCR_CMDFE_POS 0 1128: #define AG903_DDR_FLUSHCR_CMDFE_MSK (0xffUL << AG903_DDR_FLUSHCR_CMDFE_POS) 1129: #define AG903_DDR_FLUSHCR_FINTE_POS 8 1130: #define AG903_DDR_FLUSHCR_FINTE_MSK (0xffUL << AG903_DDR_FLUSHCR_FINTE_POS) 1131: #define AG903_DDR_FLUSHCR_DINTE_POS 16 1132: #define AG903_DDR_FLUSHCR_DINTE_MSK (0x1UL << AG903_DDR_FLUSHCR_DINTE_POS) 1133: 1134: #define AG903_DDR_FLUSHSR_FLUSH_DONE_POS 0 1135: #define AG903_DDR_FLUSHSR_FLUSH_DONE_MSK (0xffUL << AG903_DDR_FLUSHSR_FLUSH_DONE_POS) 1136: #define AG903_DDR_FLUSHSR_DBGHIT_POS 8 1137: #define AG903_DDR_FLUSHSR_DBGHIT_MSK (0x1UL << AG903_DDR_FLUSHSR_DBGHIT_POS) 1138: 1139: #define AG903_DDR_SPLITCR_SD0_POS 0 1140: #define AG903_DDR_SPLITCR_SD0_MSK (0x1UL << AG903_DDR_SPLITCR_SD0_POS) 1141: #define AG903_DDR_SPLITCR_SD1_POS 1 1142: #define AG903_DDR_SPLITCR_SD1_MSK (0x1UL << AG903_DDR_SPLITCR_SD1_POS) 1143: #define AG903_DDR_SPLITCR_SD2_POS 2 1144: #define AG903_DDR_SPLITCR_SD2_MSK (0x1UL << AG903_DDR_SPLITCR_SD2_POS) 1145: #define AG903_DDR_SPLITCR_SD3_POS 3 1146: #define AG903_DDR_SPLITCR_SD3_MSK (0x1UL << AG903_DDR_SPLITCR_SD3_POS) 1147: #define AG903_DDR_SPLITCR_SD4_POS 4 1148: #define AG903_DDR_SPLITCR_SD4_MSK (0x1UL << AG903_DDR_SPLITCR_SD4_POS) 1149: #define AG903_DDR_SPLITCR_SD5_POS 5 1150: #define AG903_DDR_SPLITCR_SD5_MSK (0x1UL << AG903_DDR_SPLITCR_SD5_POS) 1151: #define AG903_DDR_SPLITCR_SD6_POS 6 1152: #define AG903_DDR_SPLITCR_SD6_MSK (0x1UL << AG903_DDR_SPLITCR_SD6_POS) 1153: #define AG903_DDR_SPLITCR_SD7_POS 7 1154: #define AG903_DDR_SPLITCR_SD7_MSK (0x1UL << AG903_DDR_SPLITCR_SD7_POS) 1155: #define AG903_DDR_SPLITCR_HP0_POS 8 1156: #define AG903_DDR_SPLITCR_HP0_MSK (0x3UL << AG903_DDR_SPLITCR_HP0_POS) 1157: #define AG903_DDR_SPLITCR_HP1_POS 10 1158: #define AG903_DDR_SPLITCR_HP1_MSK (0x3UL << AG903_DDR_SPLITCR_HP1_POS) 1159: #define AG903_DDR_SPLITCR_HP2_POS 12 1160: #define AG903_DDR_SPLITCR_HP2_MSK (0x3UL << AG903_DDR_SPLITCR_HP2_POS) 1161: #define AG903_DDR_SPLITCR_HP3_POS 14 1162: #define AG903_DDR_SPLITCR_HP3_MSK (0x3UL << AG903_DDR_SPLITCR_HP3_POS) 1163: #define AG903_DDR_SPLITCR_HP4_POS 16 1164: #define AG903_DDR_SPLITCR_HP4_MSK (0x3UL << AG903_DDR_SPLITCR_HP4_POS) 1165: #define AG903_DDR_SPLITCR_HP5_POS 18 1166: #define AG903_DDR_SPLITCR_HP5_MSK (0x3UL << AG903_DDR_SPLITCR_HP5_POS) 1167: #define AG903_DDR_SPLITCR_HP6_POS 20 1168: #define AG903_DDR_SPLITCR_HP6_MSK (0x3UL << AG903_DDR_SPLITCR_HP6_POS) 1169: #define AG903_DDR_SPLITCR_HP7_POS 22 1170: #define AG903_DDR_SPLITCR_HP7_MSK (0x3UL << AG903_DDR_SPLITCR_HP7_POS) 1171: 1172: #define AG903_DDR_UPDCR_TDLLUP_POS 0 1173: #define AG903_DDR_UPDCR_TDLLUP_MSK (0xffUL << AG903_DDR_UPDCR_TDLLUP_POS) 1174: #define AG903_DDR_UPDCR_TWLVUP_POS 8 1175: #define AG903_DDR_UPDCR_TWLVUP_MSK (0xffUL << AG903_DDR_UPDCR_TWLVUP_POS) 1176: #define AG903_DDR_UPDCR_ZQUD_POS 16 1177: #define AG903_DDR_UPDCR_ZQUD_MSK (0x3UL << AG903_DDR_UPDCR_ZQUD_POS) 1178: 1179: #define AG903_DDR_REVR_REL_VER_POS 0 1180: #define AG903_DDR_REVR_REL_VER_MSK (0xffUL << AG903_DDR_REVR_REL_VER_POS) 1181: #define AG903_DDR_REVR_MINOR_VER_POS 8 1182: #define AG903_DDR_REVR_MINOR_VER_MSK (0xffUL << AG903_DDR_REVR_MINOR_VER_POS) 1183: #define AG903_DDR_REVR_MAJOR_VER_POS 16 1184: #define AG903_DDR_REVR_MAJOR_VER_MSK (0xffUL << AG903_DDR_REVR_MAJOR_VER_POS) 1185: 1186: #define AG903_DDR_FEATR1_CHCNT_POS 0 1187: #define AG903_DDR_FEATR1_CHCNT_MSK (0x7UL << AG903_DDR_FEATR1_CHCNT_POS) 1188: #define AG903_DDR_FEATR1_AMON_POS 3 1189: #define AG903_DDR_FEATR1_AMON_MSK (0x7UL << AG903_DDR_FEATR1_AMON_POS) 1190: #define AG903_DDR_FEATR1_MAXMW_POS 6 1191: #define AG903_DDR_FEATR1_MAXMW_MSK (0x3UL << AG903_DDR_FEATR1_MAXMW_POS) 1192: #define AG903_DDR_FEATR1_BT0_POS 8 1193: #define AG903_DDR_FEATR1_BT0_MSK (0x1UL << AG903_DDR_FEATR1_BT0_POS) 1194: #define AG903_DDR_FEATR1_BT1_POS 9 1195: #define AG903_DDR_FEATR1_BT1_MSK (0x1UL << AG903_DDR_FEATR1_BT1_POS) 1196: #define AG903_DDR_FEATR1_BT2_POS 10 1197: #define AG903_DDR_FEATR1_BT2_MSK (0x1UL << AG903_DDR_FEATR1_BT2_POS) 1198: #define AG903_DDR_FEATR1_BT3_POS 11 1199: #define AG903_DDR_FEATR1_BT3_MSK (0x1UL << AG903_DDR_FEATR1_BT3_POS) 1200: #define AG903_DDR_FEATR1_BT4_POS 12 1201: #define AG903_DDR_FEATR1_BT4_MSK (0x1UL << AG903_DDR_FEATR1_BT4_POS) 1202: #define AG903_DDR_FEATR1_BT5_POS 13 1203: #define AG903_DDR_FEATR1_BT5_MSK (0x1UL << AG903_DDR_FEATR1_BT5_POS) 1204: #define AG903_DDR_FEATR1_BT6_POS 14 1205: #define AG903_DDR_FEATR1_BT6_MSK (0x1UL << AG903_DDR_FEATR1_BT6_POS) 1206: #define AG903_DDR_FEATR1_BT7_POS 15 1207: #define AG903_DDR_FEATR1_BT7_MSK (0x1UL << AG903_DDR_FEATR1_BT7_POS) 1208: #define AG903_DDR_FEATR1_DW0_POS 16 1209: #define AG903_DDR_FEATR1_DW0_MSK (0x1UL << AG903_DDR_FEATR1_DW0_POS) 1210: #define AG903_DDR_FEATR1_DW1_POS 17 1211: #define AG903_DDR_FEATR1_DW1_MSK (0x1UL << AG903_DDR_FEATR1_DW1_POS) 1212: #define AG903_DDR_FEATR1_DW2_POS 18 1213: #define AG903_DDR_FEATR1_DW2_MSK (0x1UL << AG903_DDR_FEATR1_DW2_POS) 1214: #define AG903_DDR_FEATR1_DW3_POS 19 1215: #define AG903_DDR_FEATR1_DW3_MSK (0x1UL << AG903_DDR_FEATR1_DW3_POS) 1216: #define AG903_DDR_FEATR1_DW4_POS 20 1217: #define AG903_DDR_FEATR1_DW4_MSK (0x1UL << AG903_DDR_FEATR1_DW4_POS) 1218: #define AG903_DDR_FEATR1_DW5_POS 21 1219: #define AG903_DDR_FEATR1_DW5_MSK (0x1UL << AG903_DDR_FEATR1_DW5_POS) 1220: #define AG903_DDR_FEATR1_DW6_POS 22 1221: #define AG903_DDR_FEATR1_DW6_MSK (0x1UL << AG903_DDR_FEATR1_DW6_POS) 1222: #define AG903_DDR_FEATR1_DW7_POS 23 1223: #define AG903_DDR_FEATR1_DW7_MSK (0x1UL << AG903_DDR_FEATR1_DW7_POS) 1224: #define AG903_DDR_FEATR1_BNKNM_POS 24 1225: #define AG903_DDR_FEATR1_BNKNM_MSK (0x1UL << AG903_DDR_FEATR1_BNKNM_POS) 1226: #define AG903_DDR_FEATR1_BNKSW_POS 25 1227: #define AG903_DDR_FEATR1_BNKSW_MSK (0x1UL << AG903_DDR_FEATR1_BNKSW_POS) 1228: 1229: #define AG903_DDR_FEATR2_CM0_POS 0 1230: #define AG903_DDR_FEATR2_CM0_MSK (0x3UL << AG903_DDR_FEATR2_CM0_POS) 1231: #define AG903_DDR_FEATR2_SP0_POS 2 1232: #define AG903_DDR_FEATR2_SP0_MSK (0x1UL << AG903_DDR_FEATR2_SP0_POS) 1233: #define AG903_DDR_FEATR2_CB0_POS 3 1234: #define AG903_DDR_FEATR2_CB0_MSK (0x1UL << AG903_DDR_FEATR2_CB0_POS) 1235: #define AG903_DDR_FEATR2_CM1_POS 4 1236: #define AG903_DDR_FEATR2_CM1_MSK (0x3UL << AG903_DDR_FEATR2_CM1_POS) 1237: #define AG903_DDR_FEATR2_SP1_POS 6 1238: #define AG903_DDR_FEATR2_SP1_MSK (0x1UL << AG903_DDR_FEATR2_SP1_POS) 1239: #define AG903_DDR_FEATR2_CB1_POS 7 1240: #define AG903_DDR_FEATR2_CB1_MSK (0x1UL << AG903_DDR_FEATR2_CB1_POS) 1241: #define AG903_DDR_FEATR2_CM2_POS 8 1242: #define AG903_DDR_FEATR2_CM2_MSK (0x3UL << AG903_DDR_FEATR2_CM2_POS) 1243: #define AG903_DDR_FEATR2_SP2_POS 10 1244: #define AG903_DDR_FEATR2_SP2_MSK (0x1UL << AG903_DDR_FEATR2_SP2_POS) 1245: #define AG903_DDR_FEATR2_CB2_POS 11 1246: #define AG903_DDR_FEATR2_CB2_MSK (0x1UL << AG903_DDR_FEATR2_CB2_POS) 1247: #define AG903_DDR_FEATR2_CM3_POS 12 1248: #define AG903_DDR_FEATR2_CM3_MSK (0x3UL << AG903_DDR_FEATR2_CM3_POS) 1249: #define AG903_DDR_FEATR2_SP3_POS 14 1250: #define AG903_DDR_FEATR2_SP3_MSK (0x1UL << AG903_DDR_FEATR2_SP3_POS) 1251: #define AG903_DDR_FEATR2_CB3_POS 15 1252: #define AG903_DDR_FEATR2_CB3_MSK (0x1UL << AG903_DDR_FEATR2_CB3_POS) 1253: #define AG903_DDR_FEATR2_CM4_POS 16 1254: #define AG903_DDR_FEATR2_CM4_MSK (0x3UL << AG903_DDR_FEATR2_CM4_POS) 1255: #define AG903_DDR_FEATR2_SP4_POS 18 1256: #define AG903_DDR_FEATR2_SP4_MSK (0x1UL << AG903_DDR_FEATR2_SP4_POS) 1257: #define AG903_DDR_FEATR2_CB4_POS 19 1258: #define AG903_DDR_FEATR2_CB4_MSK (0x1UL << AG903_DDR_FEATR2_CB4_POS) 1259: #define AG903_DDR_FEATR2_CM5_POS 20 1260: #define AG903_DDR_FEATR2_CM5_MSK (0x3UL << AG903_DDR_FEATR2_CM5_POS) 1261: #define AG903_DDR_FEATR2_SP5_POS 22 1262: #define AG903_DDR_FEATR2_SP5_MSK (0x1UL << AG903_DDR_FEATR2_SP5_POS) 1263: #define AG903_DDR_FEATR2_CB5_POS 23 1264: #define AG903_DDR_FEATR2_CB5_MSK (0x1UL << AG903_DDR_FEATR2_CB5_POS) 1265: #define AG903_DDR_FEATR2_CM6_POS 24 1266: #define AG903_DDR_FEATR2_CM6_MSK (0x3UL << AG903_DDR_FEATR2_CM6_POS) 1267: #define AG903_DDR_FEATR2_SP6_POS 26 1268: #define AG903_DDR_FEATR2_SP6_MSK (0x1UL << AG903_DDR_FEATR2_SP6_POS) 1269: #define AG903_DDR_FEATR2_CB6_POS 27 1270: #define AG903_DDR_FEATR2_CB6_MSK (0x1UL << AG903_DDR_FEATR2_CB6_POS) 1271: #define AG903_DDR_FEATR2_CM7_POS 28 1272: #define AG903_DDR_FEATR2_CM7_MSK (0x3UL << AG903_DDR_FEATR2_CM7_POS) 1273: #define AG903_DDR_FEATR2_SP7_POS 30 1274: #define AG903_DDR_FEATR2_SP7_MSK (0x1UL << AG903_DDR_FEATR2_SP7_POS) 1275: #define AG903_DDR_FEATR2_CB7_POS 31 1276: #define AG903_DDR_FEATR2_CB7_MSK (0x1UL << AG903_DDR_FEATR2_CB7_POS) 1277: 1278: #define AG903_DDR_UDEFR_VALUE_POS 0 1279: #define AG903_DDR_UDEFR_VALUE_MSK (0xffffffffUL << AG903_DDR_UDEFR_VALUE_POS) 1280: 1281: #define AG903_DDR_WLEVELCR_TWL_POS 0 1282: #define AG903_DDR_WLEVELCR_TWL_MSK (0xffUL << AG903_DDR_WLEVELCR_TWL_POS) 1283: #define AG903_DDR_WLEVELCR_WHD0_POS 16 1284: #define AG903_DDR_WLEVELCR_WHD0_MSK (0x1UL << AG903_DDR_WLEVELCR_WHD0_POS) 1285: #define AG903_DDR_WLEVELCR_WHD1_POS 17 1286: #define AG903_DDR_WLEVELCR_WHD1_MSK (0x1UL << AG903_DDR_WLEVELCR_WHD1_POS) 1287: #define AG903_DDR_WLEVELCR_WHD2_POS 18 1288: #define AG903_DDR_WLEVELCR_WHD2_MSK (0x1UL << AG903_DDR_WLEVELCR_WHD2_POS) 1289: #define AG903_DDR_WLEVELCR_WHD3_POS 19 1290: #define AG903_DDR_WLEVELCR_WHD3_MSK (0x1UL << AG903_DDR_WLEVELCR_WHD3_POS) 1291: #define AG903_DDR_WLEVELCR_WHD4_POS 20 1292: #define AG903_DDR_WLEVELCR_WHD4_MSK (0x1UL << AG903_DDR_WLEVELCR_WHD4_POS) 1293: #define AG903_DDR_WLEVELCR_WHD5_POS 21 1294: #define AG903_DDR_WLEVELCR_WHD5_MSK (0x1UL << AG903_DDR_WLEVELCR_WHD5_POS) 1295: #define AG903_DDR_WLEVELCR_WHD6_POS 22 1296: #define AG903_DDR_WLEVELCR_WHD6_MSK (0x1UL << AG903_DDR_WLEVELCR_WHD6_POS) 1297: #define AG903_DDR_WLEVELCR_WHD7_POS 23 1298: #define AG903_DDR_WLEVELCR_WHD7_MSK (0x1UL << AG903_DDR_WLEVELCR_WHD7_POS) 1299: #define AG903_DDR_WLEVELCR_WLP0_POS 24 1300: #define AG903_DDR_WLEVELCR_WLP0_MSK (0x1UL << AG903_DDR_WLEVELCR_WLP0_POS) 1301: #define AG903_DDR_WLEVELCR_WLP1_POS 25 1302: #define AG903_DDR_WLEVELCR_WLP1_MSK (0x1UL << AG903_DDR_WLEVELCR_WLP1_POS) 1303: #define AG903_DDR_WLEVELCR_WLP2_POS 26 1304: #define AG903_DDR_WLEVELCR_WLP2_MSK (0x1UL << AG903_DDR_WLEVELCR_WLP2_POS) 1305: #define AG903_DDR_WLEVELCR_WLP3_POS 27 1306: #define AG903_DDR_WLEVELCR_WLP3_MSK (0x1UL << AG903_DDR_WLEVELCR_WLP3_POS) 1307: #define AG903_DDR_WLEVELCR_WLP4_POS 28 1308: #define AG903_DDR_WLEVELCR_WLP4_MSK (0x1UL << AG903_DDR_WLEVELCR_WLP4_POS) 1309: #define AG903_DDR_WLEVELCR_WLP5_POS 29 1310: #define AG903_DDR_WLEVELCR_WLP5_MSK (0x1UL << AG903_DDR_WLEVELCR_WLP5_POS) 1311: #define AG903_DDR_WLEVELCR_WLP6_POS 30 1312: #define AG903_DDR_WLEVELCR_WLP6_MSK (0x1UL << AG903_DDR_WLEVELCR_WLP6_POS) 1313: #define AG903_DDR_WLEVELCR_WLP7_POS 31 1314: #define AG903_DDR_WLEVELCR_WLP7_MSK (0x1UL << AG903_DDR_WLEVELCR_WLP7_POS) 1315: 1316: #define AG903_DDR_WLEVELBHR_DELAY4_POS 0 1317: #define AG903_DDR_WLEVELBHR_DELAY4_MSK (0x7fUL << AG903_DDR_WLEVELBHR_DELAY4_POS) 1318: #define AG903_DDR_WLEVELBHR_DELAY5_POS 8 1319: #define AG903_DDR_WLEVELBHR_DELAY5_MSK (0x7fUL << AG903_DDR_WLEVELBHR_DELAY5_POS) 1320: #define AG903_DDR_WLEVELBHR_DELAY6_POS 16 1321: #define AG903_DDR_WLEVELBHR_DELAY6_MSK (0x7fUL << AG903_DDR_WLEVELBHR_DELAY6_POS) 1322: #define AG903_DDR_WLEVELBHR_DELAY7_POS 24 1323: #define AG903_DDR_WLEVELBHR_DELAY7_MSK (0x7fUL << AG903_DDR_WLEVELBHR_DELAY7_POS) 1324: 1325: #define AG903_DDR_WLEVELBLR_DELAY0_POS 0 1326: #define AG903_DDR_WLEVELBLR_DELAY0_MSK (0x7fUL << AG903_DDR_WLEVELBLR_DELAY0_POS) 1327: #define AG903_DDR_WLEVELBLR_DELAY1_POS 8 1328: #define AG903_DDR_WLEVELBLR_DELAY1_MSK (0x7fUL << AG903_DDR_WLEVELBLR_DELAY1_POS) 1329: #define AG903_DDR_WLEVELBLR_DELAY2_POS 16 1330: #define AG903_DDR_WLEVELBLR_DELAY2_MSK (0x7fUL << AG903_DDR_WLEVELBLR_DELAY2_POS) 1331: #define AG903_DDR_WLEVELBLR_DELAY3_POS 24 1332: #define AG903_DDR_WLEVELBLR_DELAY3_MSK (0x7fUL << AG903_DDR_WLEVELBLR_DELAY3_POS) 1333: 1334: #define AG903_DDR_PHYMISCR1_RDQS0_POS 0 1335: #define AG903_DDR_PHYMISCR1_RDQS0_MSK (0x1UL << AG903_DDR_PHYMISCR1_RDQS0_POS) 1336: #define AG903_DDR_PHYMISCR1_WDQS0_POS 1 1337: #define AG903_DDR_PHYMISCR1_WDQS0_MSK (0x1UL << AG903_DDR_PHYMISCR1_WDQS0_POS) 1338: #define AG903_DDR_PHYMISCR1_RDQS1_POS 4 1339: #define AG903_DDR_PHYMISCR1_RDQS1_MSK (0x1UL << AG903_DDR_PHYMISCR1_RDQS1_POS) 1340: #define AG903_DDR_PHYMISCR1_WDQS1_POS 5 1341: #define AG903_DDR_PHYMISCR1_WDQS1_MSK (0x1UL << AG903_DDR_PHYMISCR1_WDQS1_POS) 1342: #define AG903_DDR_PHYMISCR1_RDQS2_POS 8 1343: #define AG903_DDR_PHYMISCR1_RDQS2_MSK (0x1UL << AG903_DDR_PHYMISCR1_RDQS2_POS) 1344: #define AG903_DDR_PHYMISCR1_WDQS2_POS 9 1345: #define AG903_DDR_PHYMISCR1_WDQS2_MSK (0x1UL << AG903_DDR_PHYMISCR1_WDQS2_POS) 1346: #define AG903_DDR_PHYMISCR1_RDQS3_POS 12 1347: #define AG903_DDR_PHYMISCR1_RDQS3_MSK (0x1UL << AG903_DDR_PHYMISCR1_RDQS3_POS) 1348: #define AG903_DDR_PHYMISCR1_WDQS3_POS 13 1349: #define AG903_DDR_PHYMISCR1_WDQS3_MSK (0x1UL << AG903_DDR_PHYMISCR1_WDQS3_POS) 1350: #define AG903_DDR_PHYMISCR1_RDQS4_POS 16 1351: #define AG903_DDR_PHYMISCR1_RDQS4_MSK (0x1UL << AG903_DDR_PHYMISCR1_RDQS4_POS) 1352: #define AG903_DDR_PHYMISCR1_WDQS4_POS 17 1353: #define AG903_DDR_PHYMISCR1_WDQS4_MSK (0x1UL << AG903_DDR_PHYMISCR1_WDQS4_POS) 1354: #define AG903_DDR_PHYMISCR1_RDQS5_POS 20 1355: #define AG903_DDR_PHYMISCR1_RDQS5_MSK (0x1UL << AG903_DDR_PHYMISCR1_RDQS5_POS) 1356: #define AG903_DDR_PHYMISCR1_WDQS5_POS 21 1357: #define AG903_DDR_PHYMISCR1_WDQS5_MSK (0x1UL << AG903_DDR_PHYMISCR1_WDQS5_POS) 1358: #define AG903_DDR_PHYMISCR1_RDQS6_POS 24 1359: #define AG903_DDR_PHYMISCR1_RDQS6_MSK (0x1UL << AG903_DDR_PHYMISCR1_RDQS6_POS) 1360: #define AG903_DDR_PHYMISCR1_WDQS6_POS 25 1361: #define AG903_DDR_PHYMISCR1_WDQS6_MSK (0x1UL << AG903_DDR_PHYMISCR1_WDQS6_POS) 1362: #define AG903_DDR_PHYMISCR1_RDQS7_POS 28 1363: #define AG903_DDR_PHYMISCR1_RDQS7_MSK (0x1UL << AG903_DDR_PHYMISCR1_RDQS7_POS) 1364: #define AG903_DDR_PHYMISCR1_WDQS7_POS 29 1365: #define AG903_DDR_PHYMISCR1_WDQS7_MSK (0x1UL << AG903_DDR_PHYMISCR1_WDQS7_POS) 1366: 1367: #define AG903_DDR_RLEVELCR_RHD0_POS 0 1368: #define AG903_DDR_RLEVELCR_RHD0_MSK (0x1UL << AG903_DDR_RLEVELCR_RHD0_POS) 1369: #define AG903_DDR_RLEVELCR_RHD1_POS 1 1370: #define AG903_DDR_RLEVELCR_RHD1_MSK (0x1UL << AG903_DDR_RLEVELCR_RHD1_POS) 1371: #define AG903_DDR_RLEVELCR_RHD2_POS 2 1372: #define AG903_DDR_RLEVELCR_RHD2_MSK (0x1UL << AG903_DDR_RLEVELCR_RHD2_POS) 1373: #define AG903_DDR_RLEVELCR_RHD3_POS 3 1374: #define AG903_DDR_RLEVELCR_RHD3_MSK (0x1UL << AG903_DDR_RLEVELCR_RHD3_POS) 1375: #define AG903_DDR_RLEVELCR_RHD4_POS 4 1376: #define AG903_DDR_RLEVELCR_RHD4_MSK (0x1UL << AG903_DDR_RLEVELCR_RHD4_POS) 1377: #define AG903_DDR_RLEVELCR_RHD5_POS 5 1378: #define AG903_DDR_RLEVELCR_RHD5_MSK (0x1UL << AG903_DDR_RLEVELCR_RHD5_POS) 1379: #define AG903_DDR_RLEVELCR_RHD6_POS 6 1380: #define AG903_DDR_RLEVELCR_RHD6_MSK (0x1UL << AG903_DDR_RLEVELCR_RHD6_POS) 1381: #define AG903_DDR_RLEVELCR_RHD7_POS 7 1382: #define AG903_DDR_RLEVELCR_RHD7_MSK (0x1UL << AG903_DDR_RLEVELCR_RHD7_POS) 1383: #define AG903_DDR_RLEVELCR_RLP0_POS 24 1384: #define AG903_DDR_RLEVELCR_RLP0_MSK (0x1UL << AG903_DDR_RLEVELCR_RLP0_POS) 1385: #define AG903_DDR_RLEVELCR_RLP1_POS 25 1386: #define AG903_DDR_RLEVELCR_RLP1_MSK (0x1UL << AG903_DDR_RLEVELCR_RLP1_POS) 1387: #define AG903_DDR_RLEVELCR_RLP2_POS 26 1388: #define AG903_DDR_RLEVELCR_RLP2_MSK (0x1UL << AG903_DDR_RLEVELCR_RLP2_POS) 1389: #define AG903_DDR_RLEVELCR_RLP3_POS 27 1390: #define AG903_DDR_RLEVELCR_RLP3_MSK (0x1UL << AG903_DDR_RLEVELCR_RLP3_POS) 1391: #define AG903_DDR_RLEVELCR_RLP4_POS 28 1392: #define AG903_DDR_RLEVELCR_RLP4_MSK (0x1UL << AG903_DDR_RLEVELCR_RLP4_POS) 1393: #define AG903_DDR_RLEVELCR_RLP5_POS 29 1394: #define AG903_DDR_RLEVELCR_RLP5_MSK (0x1UL << AG903_DDR_RLEVELCR_RLP5_POS) 1395: #define AG903_DDR_RLEVELCR_RLP6_POS 30 1396: #define AG903_DDR_RLEVELCR_RLP6_MSK (0x1UL << AG903_DDR_RLEVELCR_RLP6_POS) 1397: #define AG903_DDR_RLEVELCR_RLP7_POS 31 1398: #define AG903_DDR_RLEVELCR_RLP7_MSK (0x1UL << AG903_DDR_RLEVELCR_RLP7_POS) 1399: 1400: #define AG903_DDR_MSDLYCR_MSDLY0_POS 0 1401: #define AG903_DDR_MSDLYCR_MSDLY0_MSK (0xfUL << AG903_DDR_MSDLYCR_MSDLY0_POS) 1402: #define AG903_DDR_MSDLYCR_MSDLY1_POS 4 1403: #define AG903_DDR_MSDLYCR_MSDLY1_MSK (0xfUL << AG903_DDR_MSDLYCR_MSDLY1_POS) 1404: #define AG903_DDR_MSDLYCR_MSDLY2_POS 8 1405: #define AG903_DDR_MSDLYCR_MSDLY2_MSK (0xfUL << AG903_DDR_MSDLYCR_MSDLY2_POS) 1406: #define AG903_DDR_MSDLYCR_MSDLY3_POS 12 1407: #define AG903_DDR_MSDLYCR_MSDLY3_MSK (0xfUL << AG903_DDR_MSDLYCR_MSDLY3_POS) 1408: #define AG903_DDR_MSDLYCR_MSDLY4_POS 16 1409: #define AG903_DDR_MSDLYCR_MSDLY4_MSK (0xfUL << AG903_DDR_MSDLYCR_MSDLY4_POS) 1410: #define AG903_DDR_MSDLYCR_MSDLY5_POS 20 1411: #define AG903_DDR_MSDLYCR_MSDLY5_MSK (0xfUL << AG903_DDR_MSDLYCR_MSDLY5_POS) 1412: #define AG903_DDR_MSDLYCR_MSDLY6_POS 24 1413: #define AG903_DDR_MSDLYCR_MSDLY6_MSK (0xfUL << AG903_DDR_MSDLYCR_MSDLY6_POS) 1414: #define AG903_DDR_MSDLYCR_MSDLY7_POS 28 1415: #define AG903_DDR_MSDLYCR_MSDLY7_MSK (0xfUL << AG903_DDR_MSDLYCR_MSDLY7_POS) 1416: 1417: #define AG903_DDR_WRDLLCR_WRDLL0_POS 0 1418: #define AG903_DDR_WRDLLCR_WRDLL0_MSK (0x7UL << AG903_DDR_WRDLLCR_WRDLL0_POS) 1419: #define AG903_DDR_WRDLLCR_WRDLL1_POS 4 1420: #define AG903_DDR_WRDLLCR_WRDLL1_MSK (0x7UL << AG903_DDR_WRDLLCR_WRDLL1_POS) 1421: #define AG903_DDR_WRDLLCR_WRDLL2_POS 8 1422: #define AG903_DDR_WRDLLCR_WRDLL2_MSK (0x7UL << AG903_DDR_WRDLLCR_WRDLL2_POS) 1423: #define AG903_DDR_WRDLLCR_WRDLL3_POS 12 1424: #define AG903_DDR_WRDLLCR_WRDLL3_MSK (0x7UL << AG903_DDR_WRDLLCR_WRDLL3_POS) 1425: #define AG903_DDR_WRDLLCR_WRDLL4_POS 16 1426: #define AG903_DDR_WRDLLCR_WRDLL4_MSK (0x7UL << AG903_DDR_WRDLLCR_WRDLL4_POS) 1427: #define AG903_DDR_WRDLLCR_WRDLL5_POS 20 1428: #define AG903_DDR_WRDLLCR_WRDLL5_MSK (0x7UL << AG903_DDR_WRDLLCR_WRDLL5_POS) 1429: #define AG903_DDR_WRDLLCR_WRDLL6_POS 24 1430: #define AG903_DDR_WRDLLCR_WRDLL6_MSK (0x7UL << AG903_DDR_WRDLLCR_WRDLL6_POS) 1431: #define AG903_DDR_WRDLLCR_WRDLL7_POS 28 1432: #define AG903_DDR_WRDLLCR_WRDLL7_MSK (0x7UL << AG903_DDR_WRDLLCR_WRDLL7_POS) 1433: 1434: #define AG903_DDR_TRAFMR_TMCLKCYCLE_POS 0 1435: #define AG903_DDR_TRAFMR_TMCLKCYCLE_MSK (0xffffffffUL << AG903_DDR_TRAFMR_TMCLKCYCLE_POS) 1436: 1437: #define AG903_DDR_CMDCNTR0_CMDCNT0_POS 0 1438: #define AG903_DDR_CMDCNTR0_CMDCNT0_MSK (0xffffffffUL << AG903_DDR_CMDCNTR0_CMDCNT0_POS) 1439: 1440: #define AG903_DDR_CMDCNTR1_CMDCNT1_POS 0 1441: #define AG903_DDR_CMDCNTR1_CMDCNT1_MSK (0xffffffffUL << AG903_DDR_CMDCNTR1_CMDCNT1_POS) 1442: 1443: #define AG903_DDR_CMDCNTR2_CMDCNT2_POS 0 1444: #define AG903_DDR_CMDCNTR2_CMDCNT2_MSK (0xffffffffUL << AG903_DDR_CMDCNTR2_CMDCNT2_POS) 1445: 1446: #define AG903_DDR_CMDCNTR3_CMDCNT3_POS 0 1447: #define AG903_DDR_CMDCNTR3_CMDCNT3_MSK (0xffffffffUL << AG903_DDR_CMDCNTR3_CMDCNT3_POS) 1448: 1449: #define AG903_DDR_CMDCNTR4_CMDCNT4_POS 0 1450: #define AG903_DDR_CMDCNTR4_CMDCNT4_MSK (0xffffffffUL << AG903_DDR_CMDCNTR4_CMDCNT4_POS) 1451: 1452: #define AG903_DDR_CMDCNTR5_CMDCNT5_POS 0 1453: #define AG903_DDR_CMDCNTR5_CMDCNT5_MSK (0xffffffffUL << AG903_DDR_CMDCNTR5_CMDCNT5_POS) 1454: 1455: #define AG903_DDR_CMDCNTR6_CMDCNT6_POS 0 1456: #define AG903_DDR_CMDCNTR6_CMDCNT6_MSK (0xffffffffUL << AG903_DDR_CMDCNTR6_CMDCNT6_POS) 1457: 1458: #define AG903_DDR_CMDCNTR7_CMDCNT7_POS 0 1459: #define AG903_DDR_CMDCNTR7_CMDCNT7_MSK (0xffffffffUL << AG903_DDR_CMDCNTR7_CMDCNT7_POS) 1460: 1461: #define AG903_DDR_AHBRPRER1_PFV0_POS 0 1462: #define AG903_DDR_AHBRPRER1_PFV0_MSK (0xfUL << AG903_DDR_AHBRPRER1_PFV0_POS) 1463: #define AG903_DDR_AHBRPRER1_LPF0_POS 7 1464: #define AG903_DDR_AHBRPRER1_LPF0_MSK (0x1UL << AG903_DDR_AHBRPRER1_LPF0_POS) 1465: #define AG903_DDR_AHBRPRER1_PFV1_POS 8 1466: #define AG903_DDR_AHBRPRER1_PFV1_MSK (0x1fUL << AG903_DDR_AHBRPRER1_PFV1_POS) 1467: #define AG903_DDR_AHBRPRER1_LPF1_POS 15 1468: #define AG903_DDR_AHBRPRER1_LPF1_MSK (0x1UL << AG903_DDR_AHBRPRER1_LPF1_POS) 1469: #define AG903_DDR_AHBRPRER1_PFV2_POS 16 1470: #define AG903_DDR_AHBRPRER1_PFV2_MSK (0x1fUL << AG903_DDR_AHBRPRER1_PFV2_POS) 1471: #define AG903_DDR_AHBRPRER1_LPF2_POS 23 1472: #define AG903_DDR_AHBRPRER1_LPF2_MSK (0x1UL << AG903_DDR_AHBRPRER1_LPF2_POS) 1473: #define AG903_DDR_AHBRPRER1_PFV3_POS 24 1474: #define AG903_DDR_AHBRPRER1_PFV3_MSK (0x1fUL << AG903_DDR_AHBRPRER1_PFV3_POS) 1475: #define AG903_DDR_AHBRPRER1_LPF3_POS 31 1476: #define AG903_DDR_AHBRPRER1_LPF3_MSK (0x1UL << AG903_DDR_AHBRPRER1_LPF3_POS) 1477: 1478: #define AG903_DDR_AHBRPRER2_PFV4_POS 0 1479: #define AG903_DDR_AHBRPRER2_PFV4_MSK (0x1fUL << AG903_DDR_AHBRPRER2_PFV4_POS) 1480: #define AG903_DDR_AHBRPRER2_LPF4_POS 7 1481: #define AG903_DDR_AHBRPRER2_LPF4_MSK (0x1UL << AG903_DDR_AHBRPRER2_LPF4_POS) 1482: #define AG903_DDR_AHBRPRER2_PFV5_POS 8 1483: #define AG903_DDR_AHBRPRER2_PFV5_MSK (0x1fUL << AG903_DDR_AHBRPRER2_PFV5_POS) 1484: #define AG903_DDR_AHBRPRER2_LPF5_POS 15 1485: #define AG903_DDR_AHBRPRER2_LPF5_MSK (0x1UL << AG903_DDR_AHBRPRER2_LPF5_POS) 1486: #define AG903_DDR_AHBRPRER2_PFV6_POS 16 1487: #define AG903_DDR_AHBRPRER2_PFV6_MSK (0x1fUL << AG903_DDR_AHBRPRER2_PFV6_POS) 1488: #define AG903_DDR_AHBRPRER2_LPF6_POS 23 1489: #define AG903_DDR_AHBRPRER2_LPF6_MSK (0x1UL << AG903_DDR_AHBRPRER2_LPF6_POS) 1490: #define AG903_DDR_AHBRPRER2_PFV7_POS 24 1491: #define AG903_DDR_AHBRPRER2_PFV7_MSK (0x1fUL << AG903_DDR_AHBRPRER2_PFV7_POS) 1492: #define AG903_DDR_AHBRPRER2_LPF7_POS 31 1493: #define AG903_DDR_AHBRPRER2_LPF7_MSK (0x1UL << AG903_DDR_AHBRPRER2_LPF7_POS) 1494: 1495: #define AG903_DDR_INITWCR1_WC200US_POS 0 1496: #define AG903_DDR_INITWCR1_WC200US_MSK (0xfffffUL << AG903_DDR_INITWCR1_WC200US_POS) 1497: 1498: #define AG903_DDR_INITWCR2_WC500US_POS 0 1499: #define AG903_DDR_INITWCR2_WC500US_MSK (0xfffffUL << AG903_DDR_INITWCR2_WC500US_POS) 1500: 1501: #define AG903_DDR_QOSCR_EN_POS 0 1502: #define AG903_DDR_QOSCR_EN_MSK (0x1UL << AG903_DDR_QOSCR_EN_POS) 1503: #define AG903_DDR_QOSCR_PERI_POS 1 1504: #define AG903_DDR_QOSCR_PERI_MSK (0x3UL << AG903_DDR_QOSCR_PERI_POS) 1505: #define AG903_DDR_QOSCR_IDRW_POS 3 1506: #define AG903_DDR_QOSCR_IDRW_MSK (0x1UL << AG903_DDR_QOSCR_IDRW_POS) 1507: 1508: #define AG903_DDR_QOSCNTRA_CMDCNT0_POS 0 1509: #define AG903_DDR_QOSCNTRA_CMDCNT0_MSK (0xffUL << AG903_DDR_QOSCNTRA_CMDCNT0_POS) 1510: #define AG903_DDR_QOSCNTRA_CMDCNT1_POS 8 1511: #define AG903_DDR_QOSCNTRA_CMDCNT1_MSK (0xffUL << AG903_DDR_QOSCNTRA_CMDCNT1_POS) 1512: #define AG903_DDR_QOSCNTRA_CMDCNT2_POS 16 1513: #define AG903_DDR_QOSCNTRA_CMDCNT2_MSK (0xffUL << AG903_DDR_QOSCNTRA_CMDCNT2_POS) 1514: #define AG903_DDR_QOSCNTRA_CMDCNT3_POS 24 1515: #define AG903_DDR_QOSCNTRA_CMDCNT3_MSK (0xffUL << AG903_DDR_QOSCNTRA_CMDCNT3_POS) 1516: 1517: #define AG903_DDR_QOSCNTRB_CMDCNT4_POS 0 1518: #define AG903_DDR_QOSCNTRB_CMDCNT4_MSK (0xffUL << AG903_DDR_QOSCNTRB_CMDCNT4_POS) 1519: #define AG903_DDR_QOSCNTRB_CMDCNT5_POS 8 1520: #define AG903_DDR_QOSCNTRB_CMDCNT5_MSK (0xffUL << AG903_DDR_QOSCNTRB_CMDCNT5_POS) 1521: #define AG903_DDR_QOSCNTRB_CMDCNT6_POS 16 1522: #define AG903_DDR_QOSCNTRB_CMDCNT6_MSK (0xffUL << AG903_DDR_QOSCNTRB_CMDCNT6_POS) 1523: #define AG903_DDR_QOSCNTRB_CMDCNT7_POS 24 1524: #define AG903_DDR_QOSCNTRB_CMDCNT7_MSK (0xffUL << AG903_DDR_QOSCNTRB_CMDCNT7_POS) 1525: 1526: #define AG903_DDR_QOSCNTRC_WCMDCNT0_POS 0 1527: #define AG903_DDR_QOSCNTRC_WCMDCNT0_MSK (0xffUL << AG903_DDR_QOSCNTRC_WCMDCNT0_POS) 1528: #define AG903_DDR_QOSCNTRC_WCMDCNT1_POS 8 1529: #define AG903_DDR_QOSCNTRC_WCMDCNT1_MSK (0xffUL << AG903_DDR_QOSCNTRC_WCMDCNT1_POS) 1530: #define AG903_DDR_QOSCNTRC_WCMDCNT2_POS 16 1531: #define AG903_DDR_QOSCNTRC_WCMDCNT2_MSK (0xffUL << AG903_DDR_QOSCNTRC_WCMDCNT2_POS) 1532: #define AG903_DDR_QOSCNTRC_WCMDCNT3_POS 24 1533: #define AG903_DDR_QOSCNTRC_WCMDCNT3_MSK (0xffUL << AG903_DDR_QOSCNTRC_WCMDCNT3_POS) 1534: 1535: #define AG903_DDR_QOSCNTRD_WCMDCNT4_POS 0 1536: #define AG903_DDR_QOSCNTRD_WCMDCNT4_MSK (0xffUL << AG903_DDR_QOSCNTRD_WCMDCNT4_POS) 1537: #define AG903_DDR_QOSCNTRD_WCMDCNT5_POS 8 1538: #define AG903_DDR_QOSCNTRD_WCMDCNT5_MSK (0xffUL << AG903_DDR_QOSCNTRD_WCMDCNT5_POS) 1539: #define AG903_DDR_QOSCNTRD_WCMDCNT6_POS 16 1540: #define AG903_DDR_QOSCNTRD_WCMDCNT6_MSK (0xffUL << AG903_DDR_QOSCNTRD_WCMDCNT6_POS) 1541: #define AG903_DDR_QOSCNTRD_WCMDCNT7_POS 24 1542: #define AG903_DDR_QOSCNTRD_WCMDCNT7_MSK (0xffUL << AG903_DDR_QOSCNTRD_WCMDCNT7_POS) 1543: 1544: #define AG903_DDR_CHARBRB_WHIPRI_POS 0 1545: #define AG903_DDR_CHARBRB_WHIPRI_MSK (0xffUL << AG903_DDR_CHARBRB_WHIPRI_POS) 1546: #define AG903_DDR_CHARBRB_WBSTORTARB_POS 8 1547: #define AG903_DDR_CHARBRB_WBSTORTARB_MSK (0xffUL << AG903_DDR_CHARBRB_WBSTORTARB_POS) 1548: #define AG903_DDR_CHARBRB_WGGRTCNT_POS 24 1549: #define AG903_DDR_CHARBRB_WGGRTCNT_MSK (0x1fUL << AG903_DDR_CHARBRB_WGGRTCNT_POS) 1550: 1551: #define AG903_DDR_CHGNTRC_WARBCNT0_POS 0 1552: #define AG903_DDR_CHGNTRC_WARBCNT0_MSK (0x1fUL << AG903_DDR_CHGNTRC_WARBCNT0_POS) 1553: #define AG903_DDR_CHGNTRC_WARBCNT1_POS 8 1554: #define AG903_DDR_CHGNTRC_WARBCNT1_MSK (0x1fUL << AG903_DDR_CHGNTRC_WARBCNT1_POS) 1555: #define AG903_DDR_CHGNTRC_WARBCNT2_POS 16 1556: #define AG903_DDR_CHGNTRC_WARBCNT2_MSK (0x1fUL << AG903_DDR_CHGNTRC_WARBCNT2_POS) 1557: #define AG903_DDR_CHGNTRC_WARBCNT3_POS 24 1558: #define AG903_DDR_CHGNTRC_WARBCNT3_MSK (0x1fUL << AG903_DDR_CHGNTRC_WARBCNT3_POS) 1559: 1560: #define AG903_DDR_CHGNTRD_WARBCNT4_POS 0 1561: #define AG903_DDR_CHGNTRD_WARBCNT4_MSK (0x1fUL << AG903_DDR_CHGNTRD_WARBCNT4_POS) 1562: #define AG903_DDR_CHGNTRD_WARBCNT5_POS 8 1563: #define AG903_DDR_CHGNTRD_WARBCNT5_MSK (0x1fUL << AG903_DDR_CHGNTRD_WARBCNT5_POS) 1564: #define AG903_DDR_CHGNTRD_WARBCNT6_POS 16 1565: #define AG903_DDR_CHGNTRD_WARBCNT6_MSK (0x1fUL << AG903_DDR_CHGNTRD_WARBCNT6_POS) 1566: #define AG903_DDR_CHGNTRD_WARBCNT7_POS 24 1567: #define AG903_DDR_CHGNTRD_WARBCNT7_MSK (0x1fUL << AG903_DDR_CHGNTRD_WARBCNT7_POS) 1568: 1569: #define AG903_DDR_DBGADR_BASEADDR_POS 0 1570: #define AG903_DDR_DBGADR_BASEADDR_MSK (0xffffffffUL << AG903_DDR_DBGADR_BASEADDR_POS) 1571: 1572: #define AG903_DDR_DBGADMR_ADDRMASK_POS 0 1573: #define AG903_DDR_DBGADMR_ADDRMASK_MSK (0xffffffffUL << AG903_DDR_DBGADMR_ADDRMASK_POS) 1574: 1575: #define AG903_DDR_DBGWDR_WRITEDATA_POS 0 1576: #define AG903_DDR_DBGWDR_WRITEDATA_MSK (0xffffffffUL << AG903_DDR_DBGWDR_WRITEDATA_POS) 1577: 1578: #define AG903_DDR_DBGWDMR_DATAMASK_POS 0 1579: #define AG903_DDR_DBGWDMR_DATAMASK_MSK (0xffffffffUL << AG903_DDR_DBGWDMR_DATAMASK_POS) 1580: 1581: #define AG903_DDR_DBGMSTR_ID_POS 0 1582: #define AG903_DDR_DBGMSTR_ID_MSK (0xffffUL << AG903_DDR_DBGMSTR_ID_POS) 1583: #define AG903_DDR_DBGMSTR_CH_POS 16 1584: #define AG903_DDR_DBGMSTR_CH_MSK (0x7UL << AG903_DDR_DBGMSTR_CH_POS) 1585: #define AG903_DDR_DBGMSTR_EX_POS 19 1586: #define AG903_DDR_DBGMSTR_EX_MSK (0x1UL << AG903_DDR_DBGMSTR_EX_POS) 1587: 1588: #define AG903_DDR_DBGACCR_RWS_POS 0 1589: #define AG903_DDR_DBGACCR_RWS_MSK (0x1UL << AG903_DDR_DBGACCR_RWS_POS) 1590: #define AG903_DDR_DBGACCR_LSW_POS 1 1591: #define AG903_DDR_DBGACCR_LSW_MSK (0x1UL << AG903_DDR_DBGACCR_LSW_POS) 1592: 1593: #define AG903_DDR_DBGPCR_ADR_POS 0 1594: #define AG903_DDR_DBGPCR_ADR_MSK (0x1UL << AG903_DDR_DBGPCR_ADR_POS) 1595: #define AG903_DDR_DBGPCR_WD_POS 1 1596: #define AG903_DDR_DBGPCR_WD_MSK (0x1UL << AG903_DDR_DBGPCR_WD_POS) 1597: #define AG903_DDR_DBGPCR_ID_POS 2 1598: #define AG903_DDR_DBGPCR_ID_MSK (0x1UL << AG903_DDR_DBGPCR_ID_POS) 1599: #define AG903_DDR_DBGPCR_CH_POS 3 1600: #define AG903_DDR_DBGPCR_CH_MSK (0x1UL << AG903_DDR_DBGPCR_CH_POS) 1601: #define AG903_DDR_DBGPCR_RW_POS 4 1602: #define AG903_DDR_DBGPCR_RW_MSK (0x1UL << AG903_DDR_DBGPCR_RW_POS) 1603: 1604: #define AG903_DDR_DBGENR_EN_POS 0 1605: #define AG903_DDR_DBGENR_EN_MSK (0x1UL << AG903_DDR_DBGENR_EN_POS) 1606: 1607: #define AG903_DDR_DBGADSR_ADDRSTATUS_POS 0 1608: #define AG903_DDR_DBGADSR_ADDRSTATUS_MSK (0xffffffffUL << AG903_DDR_DBGADSR_ADDRSTATUS_POS) 1609: 1610: #define AG903_DDR_DBGWDSR_DATASTATUS_POS 0 1611: #define AG903_DDR_DBGWDSR_DATASTATUS_MSK (0xffffffffUL << AG903_DDR_DBGWDSR_DATASTATUS_POS) 1612: 1613: #define AG903_DDR_DBGMSTSR_IDSTATUS_POS 0 1614: #define AG903_DDR_DBGMSTSR_IDSTATUS_MSK (0xffffUL << AG903_DDR_DBGMSTSR_IDSTATUS_POS) 1615: #define AG903_DDR_DBGMSTSR_CHSTATUS_POS 16 1616: #define AG903_DDR_DBGMSTSR_CHSTATUS_MSK (0x7UL << AG903_DDR_DBGMSTSR_CHSTATUS_POS) 1617: 1618: #define AG903_DDR_DBGACCSR_ST_POS 0 1619: #define AG903_DDR_DBGACCSR_ST_MSK (0x1UL << AG903_DDR_DBGACCSR_ST_POS) 1620: 1621: #define AG903_DDR_PHYRDTFR_RD0_POS 0 1622: #define AG903_DDR_PHYRDTFR_RD0_MSK (0x7UL << AG903_DDR_PHYRDTFR_RD0_POS) 1623: #define AG903_DDR_PHYRDTFR_RD1_POS 4 1624: #define AG903_DDR_PHYRDTFR_RD1_MSK (0x7UL << AG903_DDR_PHYRDTFR_RD1_POS) 1625: #define AG903_DDR_PHYRDTFR_RD2_POS 8 1626: #define AG903_DDR_PHYRDTFR_RD2_MSK (0x7UL << AG903_DDR_PHYRDTFR_RD2_POS) 1627: #define AG903_DDR_PHYRDTFR_RD3_POS 12 1628: #define AG903_DDR_PHYRDTFR_RD3_MSK (0x7UL << AG903_DDR_PHYRDTFR_RD3_POS) 1629: #define AG903_DDR_PHYRDTFR_RD4_POS 16 1630: #define AG903_DDR_PHYRDTFR_RD4_MSK (0x7UL << AG903_DDR_PHYRDTFR_RD4_POS) 1631: #define AG903_DDR_PHYRDTFR_RD5_POS 20 1632: #define AG903_DDR_PHYRDTFR_RD5_MSK (0x7UL << AG903_DDR_PHYRDTFR_RD5_POS) 1633: #define AG903_DDR_PHYRDTFR_RD6_POS 24 1634: #define AG903_DDR_PHYRDTFR_RD6_MSK (0x7UL << AG903_DDR_PHYRDTFR_RD6_POS) 1635: #define AG903_DDR_PHYRDTFR_RD7_POS 28 1636: #define AG903_DDR_PHYRDTFR_RD7_MSK (0x7UL << AG903_DDR_PHYRDTFR_RD7_POS) 1637: 1638: #define AG903_DDR_PHYMISCR2_RDCA_POS 0 1639: #define AG903_DDR_PHYMISCR2_RDCA_MSK (0x7UL << AG903_DDR_PHYMISCR2_RDCA_POS) 1640: #define AG903_DDR_PHYMISCR2_RDDT_POS 4 1641: #define AG903_DDR_PHYMISCR2_RDDT_MSK (0x7UL << AG903_DDR_PHYMISCR2_RDDT_POS) 1642: #define AG903_DDR_PHYMISCR2_VREF_POS 8 1643: #define AG903_DDR_PHYMISCR2_VREF_MSK (0x7UL << AG903_DDR_PHYMISCR2_VREF_POS) 1644: #define AG903_DDR_PHYMISCR2_RLEEN_POS 12 1645: #define AG903_DDR_PHYMISCR2_RLEEN_MSK (0x1UL << AG903_DDR_PHYMISCR2_RLEEN_POS) 1646: #define AG903_DDR_PHYMISCR2_RLGEN_POS 13 1647: #define AG903_DDR_PHYMISCR2_RLGEN_MSK (0x1UL << AG903_DDR_PHYMISCR2_RLGEN_POS) 1648: #define AG903_DDR_PHYMISCR2_IO15V_POS 14 1649: #define AG903_DDR_PHYMISCR2_IO15V_MSK (0x1UL << AG903_DDR_PHYMISCR2_IO15V_POS) 1650: 1651: #endif 1652:
名前 
説明 
DDR Base Address 
DDRAHBRPRER1 LPF0-bit mask 
DDRAHBRPRER1 LPF0-bit position 
DDRAHBRPRER1 LPF1-bit mask 
DDRAHBRPRER1 LPF1-bit position 
DDRAHBRPRER1 LPF2-bit mask 
DDRAHBRPRER1 LPF2-bit position 
DDRAHBRPRER1 LPF3-bit mask 
DDRAHBRPRER1 LPF3-bit position 
DDRAHBRPRER1 PFV0-bit mask 
DDRAHBRPRER1 PFV0-bit position 
DDRAHBRPRER1 PFV1-bit mask 
DDRAHBRPRER1 PFV1-bit position 
DDRAHBRPRER1 PFV2-bit mask 
DDRAHBRPRER1 PFV2-bit position 
DDRAHBRPRER1 PFV3-bit mask 
DDRAHBRPRER1 PFV3-bit position 
DDRAHBRPRER2 LPF4-bit mask 
DDRAHBRPRER2 LPF4-bit position 
DDRAHBRPRER2 LPF5-bit mask 
DDRAHBRPRER2 LPF5-bit position 
DDRAHBRPRER2 LPF6-bit mask 
DDRAHBRPRER2 LPF6-bit position 
DDRAHBRPRER2 LPF7-bit mask 
DDRAHBRPRER2 LPF7-bit position 
DDRAHBRPRER2 PFV4-bit mask 
DDRAHBRPRER2 PFV4-bit position 
DDRAHBRPRER2 PFV5-bit mask 
DDRAHBRPRER2 PFV5-bit position 
DDRAHBRPRER2 PFV6-bit mask 
DDRAHBRPRER2 PFV6-bit position 
DDRAHBRPRER2 PFV7-bit mask 
DDRAHBRPRER2 PFV7-bit position 
DDRAPDCR PDNE-bit mask 
DDRAPDCR PDNE-bit position 
DDRAPDCR PDNT-bit mask 
DDRAPDCR PDNT-bit position 
DDRAPDCR SREFE-bit mask 
DDRAPDCR SREFE-bit position 
DDRAPDCR SREFT-bit mask 
DDRAPDCR SREFT-bit position 
DDRCHARBRA BOA-bit mask 
DDRCHARBRA BOA-bit position 
DDRCHARBRA GGCNT-bit mask 
DDRCHARBRA GGCNT-bit position 
DDRCHARBRA HP-bit mask 
DDRCHARBRA HP-bit position 
DDRCHARBRA IRWG-bit mask 
DDRCHARBRA IRWG-bit position 
DDRCHARBRA RWG-bit mask 
DDRCHARBRA RWG-bit position 
DDRCHARBRB WBSTORTARB-bit mask 
DDRCHARBRB WBSTORTARB-bit position 
DDRCHARBRB WGGRTCNT-bit mask 
DDRCHARBRB WGGRTCNT-bit position 
DDRCHARBRB WHIPRI-bit mask 
DDRCHARBRB WHIPRI-bit position 
DDRCHGNTRA ARB_CNT0-bit mask 
DDRCHGNTRA ARB_CNT0-bit position 
DDRCHGNTRA ARB_CNT1-bit mask 
DDRCHGNTRA ARB_CNT1-bit position 
DDRCHGNTRA ARB_CNT2-bit mask 
DDRCHGNTRA ARB_CNT2-bit position 
DDRCHGNTRA ARB_CNT3-bit mask 
DDRCHGNTRA ARB_CNT3-bit position 
DDRCHGNTRB ARB_CNT4-bit mask 
DDRCHGNTRB ARB_CNT4-bit position 
DDRCHGNTRB ARB_CNT5-bit mask 
DDRCHGNTRB ARB_CNT5-bit position 
DDRCHGNTRB ARB_CNT6-bit mask 
DDRCHGNTRB ARB_CNT6-bit position 
DDRCHGNTRB ARB_CNT7-bit mask 
DDRCHGNTRB ARB_CNT7-bit position 
DDRCHGNTRC WARBCNT0-bit mask 
DDRCHGNTRC WARBCNT0-bit position 
DDRCHGNTRC WARBCNT1-bit mask 
DDRCHGNTRC WARBCNT1-bit position 
DDRCHGNTRC WARBCNT2-bit mask 
DDRCHGNTRC WARBCNT2-bit position 
DDRCHGNTRC WARBCNT3-bit mask 
DDRCHGNTRC WARBCNT3-bit position 
DDRCHGNTRD WARBCNT4-bit mask 
DDRCHGNTRD WARBCNT4-bit position 
DDRCHGNTRD WARBCNT5-bit mask 
DDRCHGNTRD WARBCNT5-bit position 
DDRCHGNTRD WARBCNT6-bit mask 
DDRCHGNTRD WARBCNT6-bit position 
DDRCHGNTRD WARBCNT7-bit mask 
DDRCHGNTRD WARBCNT7-bit position 
DDRCMDCNTR0 CMDCNT0-bit mask 
DDRCMDCNTR0 CMDCNT0-bit position 
DDRCMDCNTR1 CMDCNT1-bit mask 
DDRCMDCNTR1 CMDCNT1-bit position 
DDRCMDCNTR2 CMDCNT2-bit mask 
DDRCMDCNTR2 CMDCNT2-bit position 
DDRCMDCNTR3 CMDCNT3-bit mask 
DDRCMDCNTR3 CMDCNT3-bit position 
DDRCMDCNTR4 CMDCNT4-bit mask 
DDRCMDCNTR4 CMDCNT4-bit position 
DDRCMDCNTR5 CMDCNT5-bit mask 
DDRCMDCNTR5 CMDCNT5-bit position 
DDRCMDCNTR6 CMDCNT6-bit mask 
DDRCMDCNTR6 CMDCNT6-bit position 
DDRCMDCNTR7 CMDCNT7-bit mask 
DDRCMDCNTR7 CMDCNT7-bit position 
DDRCOMPBLKCR COMP_SEL-bit mask 
DDRCOMPBLKCR COMP_SEL-bit position 
DDRCOMPBLKCR DIN-bit mask 
DDRCOMPBLKCR DIN-bit position 
DDRCOMPBLKCR DIP-bit mask 
DDRCOMPBLKCR DIP-bit position 
DDRCOMPBLKCR DON-bit mask 
DDRCOMPBLKCR DON-bit position 
DDRCOMPBLKCR DOP-bit mask 
DDRCOMPBLKCR DOP-bit position 
DDRDBGACCR LSW-bit mask 
DDRDBGACCR LSW-bit position 
DDRDBGACCR RWS-bit mask 
DDRDBGACCR RWS-bit position 
DDRDBGACCSR ST-bit mask 
DDRDBGACCSR ST-bit position 
DDRDBGADMR ADDRMASK-bit mask 
DDRDBGADMR ADDRMASK-bit position 
DDRDBGADR BASEADDR-bit mask 
DDRDBGADR BASEADDR-bit position 
DDRDBGADSR ADDRSTATUS-bit mask 
DDRDBGADSR ADDRSTATUS-bit position 
DDRDBGENR EN-bit mask 
DDRDBGENR EN-bit position 
DDRDBGMSTR CH-bit mask 
DDRDBGMSTR CH-bit position 
DDRDBGMSTR EX-bit mask 
DDRDBGMSTR EX-bit position 
DDRDBGMSTR ID-bit mask 
DDRDBGMSTR ID-bit position 
DDRDBGMSTSR CHSTATUS-bit mask 
DDRDBGMSTSR CHSTATUS-bit position 
DDRDBGMSTSR IDSTATUS-bit mask 
DDRDBGMSTSR IDSTATUS-bit position 
DDRDBGPCR ADR-bit mask 
DDRDBGPCR ADR-bit position 
DDRDBGPCR CH-bit mask 
DDRDBGPCR CH-bit position 
DDRDBGPCR ID-bit mask 
DDRDBGPCR ID-bit position 
DDRDBGPCR RW-bit mask 
DDRDBGPCR RW-bit position 
DDRDBGPCR WD-bit mask 
DDRDBGPCR WD-bit position 
DDRDBGWDMR DATAMASK-bit mask 
DDRDBGWDMR DATAMASK-bit position 
DDRDBGWDR WRITEDATA-bit mask 
DDRDBGWDR WRITEDATA-bit position 
DDRDBGWDSR DATASTATUS-bit mask 
DDRDBGWDSR DATASTATUS-bit position 
DDREXRANKR RNK0_BASE-bit mask 
DDREXRANKR RNK0_BASE-bit position 
DDREXRANKR RNK0_SIZE-bit mask 
DDREXRANKR RNK0_SIZE-bit position 
DDREXRANKR RNK0_TYPE-bit mask 
DDREXRANKR RNK0_TYPE-bit position 
DDREXRANKR RNK1_EN-bit mask 
DDREXRANKR RNK1_EN-bit position 
DDREXRANKR RNK1_SIZE-bit mask 
DDREXRANKR RNK1_SIZE-bit position 
DDREXRANKR RNK1_TYPE-bit mask 
DDREXRANKR RNK1_TYPE-bit position 
DDRFEATR1 AMON-bit mask 
DDRFEATR1 AMON-bit position 
DDRFEATR1 BNKNM-bit mask 
DDRFEATR1 BNKNM-bit position 
DDRFEATR1 BNKSW-bit mask 
DDRFEATR1 BNKSW-bit position 
DDRFEATR1 BT0-bit mask 
DDRFEATR1 BT0-bit position 
DDRFEATR1 BT1-bit mask 
DDRFEATR1 BT1-bit position 
DDRFEATR1 BT2-bit mask 
DDRFEATR1 BT2-bit position 
DDRFEATR1 BT3-bit mask 
DDRFEATR1 BT3-bit position 
DDRFEATR1 BT4-bit mask 
DDRFEATR1 BT4-bit position 
DDRFEATR1 BT5-bit mask 
DDRFEATR1 BT5-bit position 
DDRFEATR1 BT6-bit mask 
DDRFEATR1 BT6-bit position 
DDRFEATR1 BT7-bit mask 
DDRFEATR1 BT7-bit position 
DDRFEATR1 CHCNT-bit mask 
DDRFEATR1 CHCNT-bit position 
DDRFEATR1 DW0-bit mask 
DDRFEATR1 DW0-bit position 
DDRFEATR1 DW1-bit mask 
DDRFEATR1 DW1-bit position 
DDRFEATR1 DW2-bit mask 
DDRFEATR1 DW2-bit position 
DDRFEATR1 DW3-bit mask 
DDRFEATR1 DW3-bit position 
DDRFEATR1 DW4-bit mask 
DDRFEATR1 DW4-bit position 
DDRFEATR1 DW5-bit mask 
DDRFEATR1 DW5-bit position 
DDRFEATR1 DW6-bit mask 
DDRFEATR1 DW6-bit position 
DDRFEATR1 DW7-bit mask 
DDRFEATR1 DW7-bit position 
DDRFEATR1 MAXMW-bit mask 
DDRFEATR1 MAXMW-bit position 
DDRFEATR2 CB0-bit mask 
DDRFEATR2 CB0-bit position 
DDRFEATR2 CB1-bit mask 
DDRFEATR2 CB1-bit position 
DDRFEATR2 CB2-bit mask 
DDRFEATR2 CB2-bit position 
DDRFEATR2 CB3-bit mask 
DDRFEATR2 CB3-bit position 
DDRFEATR2 CB4-bit mask 
DDRFEATR2 CB4-bit position 
DDRFEATR2 CB5-bit mask 
DDRFEATR2 CB5-bit position 
DDRFEATR2 CB6-bit mask 
DDRFEATR2 CB6-bit position 
DDRFEATR2 CB7-bit mask 
DDRFEATR2 CB7-bit position 
DDRFEATR2 CM0-bit mask 
DDRFEATR2 CM0-bit position 
DDRFEATR2 CM1-bit mask 
DDRFEATR2 CM1-bit position 
DDRFEATR2 CM2-bit mask 
DDRFEATR2 CM2-bit position 
DDRFEATR2 CM3-bit mask 
DDRFEATR2 CM3-bit position 
DDRFEATR2 CM4-bit mask 
DDRFEATR2 CM4-bit position 
DDRFEATR2 CM5-bit mask 
DDRFEATR2 CM5-bit position 
DDRFEATR2 CM6-bit mask 
DDRFEATR2 CM6-bit position 
DDRFEATR2 CM7-bit mask 
DDRFEATR2 CM7-bit position 
DDRFEATR2 SP0-bit mask 
DDRFEATR2 SP0-bit position 
DDRFEATR2 SP1-bit mask 
DDRFEATR2 SP1-bit position 
DDRFEATR2 SP2-bit mask 
DDRFEATR2 SP2-bit position 
DDRFEATR2 SP3-bit mask 
DDRFEATR2 SP3-bit position 
DDRFEATR2 SP4-bit mask 
DDRFEATR2 SP4-bit position 
DDRFEATR2 SP5-bit mask 
DDRFEATR2 SP5-bit position 
DDRFEATR2 SP6-bit mask 
DDRFEATR2 SP6-bit position 
DDRFEATR2 SP7-bit mask 
DDRFEATR2 SP7-bit position 
DDRFLUSHCR CMDFE-bit mask 
DDRFLUSHCR CMDFE-bit position 
DDRFLUSHCR DINTE-bit mask 
DDRFLUSHCR DINTE-bit position 
DDRFLUSHCR FINTE-bit mask 
DDRFLUSHCR FINTE-bit position 
DDRFLUSHSR DBGHIT-bit mask 
DDRFLUSHSR DBGHIT-bit position 
DDRFLUSHSR FLUSH_DONE-bit mask 
DDRFLUSHSR FLUSH_DONE-bit position 
DDRINITWCR1 WC200US-bit mask 
DDRINITWCR1 WC200US-bit position 
DDRINITWCR2 WC500US-bit mask 
DDRINITWCR2 WC500US-bit position 
DDRMCCR AMTSEL-bit mask 
DDRMCCR AMTSEL-bit position 
DDRMCCR ARCI-bit mask 
DDRMCCR ARCI-bit position 
DDRMCCR CCL-bit mask 
DDRMCCR CCL-bit position 
DDRMCCR DBER-bit mask 
DDRMCCR DBER-bit position 
DDRMCCR DDR-bit mask 
DDRMCCR DDR-bit position 
DDRMCCR DREO-bit mask 
DDRMCCR DREO-bit position 
DDRMCCR FE-bit mask 
DDRMCCR FE-bit position 
DDRMCCR GDS-bit mask 
DDRMCCR GDS-bit position 
DDRMCCR LPDDR-bit mask 
DDRMCCR LPDDR-bit position 
DDRMCCR MREF-bit mask 
DDRMCCR MREF-bit position 
DDRMCCR MW-bit mask 
DDRMCCR MW-bit position 
DDRMCCR PRCC-bit mask 
DDRMCCR PRCC-bit position 
DDRMCCR WCYC-bit mask 
DDRMCCR WCYC-bit position 
DDRMCSR APDS-bit mask 
DDRMCSR APDS-bit position 
DDRMCSR BCQE-bit mask 
DDRMCSR BCQE-bit position 
DDRMCSR ESRC-bit mask 
DDRMCSR ESRC-bit position 
DDRMCSR INIC-bit mask 
DDRMCSR INIC-bit position 
DDRMCSR INIOK-bit mask 
DDRMCSR INIOK-bit position 
DDRMCSR INIS-bit mask 
DDRMCSR INIS-bit position 
DDRMCSR MCQE-bit mask 
DDRMCSR MCQE-bit position 
DDRMCSR MCSR-bit mask 
DDRMCSR MCSR-bit position 
DDRMCSR MRSC-bit mask 
DDRMCSR MRSC-bit position 
DDRMCSR REGM-bit mask 
DDRMCSR REGM-bit position 
DDRMCSR RLF-bit mask 
DDRMCSR RLF-bit position 
DDRMCSR SREF-bit mask 
DDRMCSR SREF-bit position 
DDRMCSR SRST-bit mask 
DDRMCSR SRST-bit position 
DDRMCSR WLF-bit mask 
DDRMCSR WLF-bit position 
DDRMCSR WSTA-bit mask 
DDRMCSR WSTA-bit position 
DDRMCSR ZQCL-bit mask 
DDRMCSR ZQCL-bit position 
DDRMCSR ZQCLS-bit mask 
DDRMCSR ZQCLS-bit position 
DDRMCSR ZQCS-bit mask 
DDRMCSR ZQCS-bit position 
DDRMCSR ZQCSS-bit mask 
DDRMCSR ZQCSS-bit position 
DDRMRSVR0 EXTMR-bit mask 
DDRMRSVR0 EXTMR-bit position 
DDRMRSVR0 MR-bit mask 
DDRMRSVR0 MR-bit position 
DDRMRSVR1 EMR2-bit mask 
DDRMRSVR1 EMR2-bit position 
DDRMRSVR1 EMR3-bit mask 
DDRMRSVR1 EMR3-bit position 
DDRMSDLYCR MSDLY0-bit mask 
DDRMSDLYCR MSDLY0-bit position 
DDRMSDLYCR MSDLY1-bit mask 
DDRMSDLYCR MSDLY1-bit position 
DDRMSDLYCR MSDLY2-bit mask 
DDRMSDLYCR MSDLY2-bit position 
DDRMSDLYCR MSDLY3-bit mask 
DDRMSDLYCR MSDLY3-bit position 
DDRMSDLYCR MSDLY4-bit mask 
DDRMSDLYCR MSDLY4-bit position 
DDRMSDLYCR MSDLY5-bit mask 
DDRMSDLYCR MSDLY5-bit position 
DDRMSDLYCR MSDLY6-bit mask 
DDRMSDLYCR MSDLY6-bit position 
DDRMSDLYCR MSDLY7-bit mask 
DDRMSDLYCR MSDLY7-bit position 
DDRPHYCR0 ACPD-bit mask 
DDRPHYCR0 ACPD-bit position 
DDRPHYCR0 ADPD-bit mask 
DDRPHYCR0 ADPD-bit position 
DDRPHYCR0 CLKE-bit mask 
DDRPHYCR0 CLKE-bit position 
DDRPHYCR0 CMDE-bit mask 
DDRPHYCR0 CMDE-bit position 
DDRPHYCR0 CPHS-bit mask 
DDRPHYCR0 CPHS-bit position 
DDRPHYCR0 DQRE-bit mask 
DDRPHYCR0 DQRE-bit position 
DDRPHYCR0 DQSB-bit mask 
DDRPHYCR0 DQSB-bit position 
DDRPHYCR0 DQSLF-bit mask 
DDRPHYCR0 DQSLF-bit position 
DDRPHYCR0 FLD0-bit mask 
DDRPHYCR0 FLD0-bit position 
DDRPHYCR0 FLD1-bit mask 
DDRPHYCR0 FLD1-bit position 
DDRPHYCR0 FLD2-bit mask 
DDRPHYCR0 FLD2-bit position 
DDRPHYCR0 FLD3-bit mask 
DDRPHYCR0 FLD3-bit position 
DDRPHYCR0 FLD4-bit mask 
DDRPHYCR0 FLD4-bit position 
DDRPHYCR0 FLD5-bit mask 
DDRPHYCR0 FLD5-bit position 
DDRPHYCR0 FLD6-bit mask 
DDRPHYCR0 FLD6-bit position 
DDRPHYCR0 FLD7-bit mask 
DDRPHYCR0 FLD7-bit position 
DDRPHYCR0 FLDC-bit mask 
DDRPHYCR0 FLDC-bit position 
DDRPHYCR0 IO18V-bit mask 
DDRPHYCR0 IO18V-bit position 
DDRPHYCR0 ODTDM-bit mask 
DDRPHYCR0 ODTDM-bit position 
DDRPHYCR0 ODTE-bit mask 
DDRPHYCR0 ODTE-bit position 
DDRPHYCR0 ODTMD-bit mask 
DDRPHYCR0 ODTMD-bit position 
DDRPHYCR0 PCU-bit mask 
DDRPHYCR0 PCU-bit position 
DDRPHYCR0 SBIAS-bit mask 
DDRPHYCR0 SBIAS-bit position 
DDRPHYMISCR1 RDQS0-bit mask 
DDRPHYMISCR1 RDQS0-bit position 
DDRPHYMISCR1 RDQS1-bit mask 
DDRPHYMISCR1 RDQS1-bit position 
DDRPHYMISCR1 RDQS2-bit mask 
DDRPHYMISCR1 RDQS2-bit position 
DDRPHYMISCR1 RDQS3-bit mask 
DDRPHYMISCR1 RDQS3-bit position 
DDRPHYMISCR1 RDQS4-bit mask 
DDRPHYMISCR1 RDQS4-bit position 
DDRPHYMISCR1 RDQS5-bit mask 
DDRPHYMISCR1 RDQS5-bit position 
DDRPHYMISCR1 RDQS6-bit mask 
DDRPHYMISCR1 RDQS6-bit position 
DDRPHYMISCR1 RDQS7-bit mask 
DDRPHYMISCR1 RDQS7-bit position 
DDRPHYMISCR1 WDQS0-bit mask 
DDRPHYMISCR1 WDQS0-bit position 
DDRPHYMISCR1 WDQS1-bit mask 
DDRPHYMISCR1 WDQS1-bit position 
DDRPHYMISCR1 WDQS2-bit mask 
DDRPHYMISCR1 WDQS2-bit position 
DDRPHYMISCR1 WDQS3-bit mask 
DDRPHYMISCR1 WDQS3-bit position 
DDRPHYMISCR1 WDQS4-bit mask 
DDRPHYMISCR1 WDQS4-bit position 
DDRPHYMISCR1 WDQS5-bit mask 
DDRPHYMISCR1 WDQS5-bit position 
DDRPHYMISCR1 WDQS6-bit mask 
DDRPHYMISCR1 WDQS6-bit position 
DDRPHYMISCR1 WDQS7-bit mask 
DDRPHYMISCR1 WDQS7-bit position 
DDRPHYMISCR2 IO15V-bit mask 
DDRPHYMISCR2 IO15V-bit position 
DDRPHYMISCR2 RDCA-bit mask 
DDRPHYMISCR2 RDCA-bit position 
DDRPHYMISCR2 RDDT-bit mask 
DDRPHYMISCR2 RDDT-bit position 
DDRPHYMISCR2 RLEEN-bit mask 
DDRPHYMISCR2 RLEEN-bit position 
DDRPHYMISCR2 RLGEN-bit mask 
DDRPHYMISCR2 RLGEN-bit position 
DDRPHYMISCR2 VREF-bit mask 
DDRPHYMISCR2 VREF-bit position 
DDRPHYRDTFR RD0-bit mask 
DDRPHYRDTFR RD0-bit position 
DDRPHYRDTFR RD1-bit mask 
DDRPHYRDTFR RD1-bit position 
DDRPHYRDTFR RD2-bit mask 
DDRPHYRDTFR RD2-bit position 
DDRPHYRDTFR RD3-bit mask 
DDRPHYRDTFR RD3-bit position 
DDRPHYRDTFR RD4-bit mask 
DDRPHYRDTFR RD4-bit position 
DDRPHYRDTFR RD5-bit mask 
DDRPHYRDTFR RD5-bit position 
DDRPHYRDTFR RD6-bit mask 
DDRPHYRDTFR RD6-bit position 
DDRPHYRDTFR RD7-bit mask 
DDRPHYRDTFR RD7-bit position 
DDRPHYRDTR DLLSEL0-bit mask 
DDRPHYRDTR DLLSEL0-bit position 
DDRPHYRDTR DLLSEL1-bit mask 
DDRPHYRDTR DLLSEL1-bit position 
DDRPHYRDTR DLLSEL2-bit mask 
DDRPHYRDTR DLLSEL2-bit position 
DDRPHYRDTR DLLSEL3-bit mask 
DDRPHYRDTR DLLSEL3-bit position 
DDRPHYRDTR DLLSEL4-bit mask 
DDRPHYRDTR DLLSEL4-bit position 
DDRPHYRDTR DLLSEL5-bit mask 
DDRPHYRDTR DLLSEL5-bit position 
DDRPHYRDTR DLLSEL6-bit mask 
DDRPHYRDTR DLLSEL6-bit position 
DDRPHYRDTR DLLSEL7-bit mask 
DDRPHYRDTR DLLSEL7-bit position 
DDRPHYWRTMR TRDEN-bit mask 
DDRPHYWRTMR TRDEN-bit position 
DDRPHYWRTMR TRDLAT-bit mask 
DDRPHYWRTMR TRDLAT-bit position 
DDRPHYWRTMR TWDEN-bit mask 
DDRPHYWRTMR TWDEN-bit position 
DDRPHYWRTMR TWLAT-bit mask 
DDRPHYWRTMR TWLAT-bit position 
DDRQOSCNTRA CMDCNT0-bit mask 
DDRQOSCNTRA CMDCNT0-bit position 
DDRQOSCNTRA CMDCNT1-bit mask 
DDRQOSCNTRA CMDCNT1-bit position 
DDRQOSCNTRA CMDCNT2-bit mask 
DDRQOSCNTRA CMDCNT2-bit position 
DDRQOSCNTRA CMDCNT3-bit mask 
DDRQOSCNTRA CMDCNT3-bit position 
DDRQOSCNTRB CMDCNT4-bit mask 
DDRQOSCNTRB CMDCNT4-bit position 
DDRQOSCNTRB CMDCNT5-bit mask 
DDRQOSCNTRB CMDCNT5-bit position 
DDRQOSCNTRB CMDCNT6-bit mask 
DDRQOSCNTRB CMDCNT6-bit position 
DDRQOSCNTRB CMDCNT7-bit mask 
DDRQOSCNTRB CMDCNT7-bit position 
DDRQOSCNTRC WCMDCNT0-bit mask 
DDRQOSCNTRC WCMDCNT0-bit position 
DDRQOSCNTRC WCMDCNT1-bit mask 
DDRQOSCNTRC WCMDCNT1-bit position 
DDRQOSCNTRC WCMDCNT2-bit mask 
DDRQOSCNTRC WCMDCNT2-bit position 
DDRQOSCNTRC WCMDCNT3-bit mask 
DDRQOSCNTRC WCMDCNT3-bit position 
DDRQOSCNTRD WCMDCNT4-bit mask 
DDRQOSCNTRD WCMDCNT4-bit position 
DDRQOSCNTRD WCMDCNT5-bit mask 
DDRQOSCNTRD WCMDCNT5-bit position 
DDRQOSCNTRD WCMDCNT6-bit mask 
DDRQOSCNTRD WCMDCNT6-bit position 
DDRQOSCNTRD WCMDCNT7-bit mask 
DDRQOSCNTRD WCMDCNT7-bit position 
DDRQOSCR EN-bit mask 
DDRQOSCR EN-bit position 
DDRQOSCR IDRW-bit mask 
DDRQOSCR IDRW-bit position 
DDRQOSCR PERI-bit mask 
DDRQOSCR PERI-bit position 
DDRREVR MAJOR_VER-bit mask 
DDRREVR MAJOR_VER-bit position 
DDRREVR MINOR_VER-bit mask 
DDRREVR MINOR_VER-bit position 
DDRREVR REL_VER-bit mask 
DDRREVR REL_VER-bit position 
DDRRLEVELCR RHD0-bit mask 
DDRRLEVELCR RHD0-bit position 
DDRRLEVELCR RHD1-bit mask 
DDRRLEVELCR RHD1-bit position 
DDRRLEVELCR RHD2-bit mask 
DDRRLEVELCR RHD2-bit position 
DDRRLEVELCR RHD3-bit mask 
DDRRLEVELCR RHD3-bit position 
DDRRLEVELCR RHD4-bit mask 
DDRRLEVELCR RHD4-bit position 
DDRRLEVELCR RHD5-bit mask 
DDRRLEVELCR RHD5-bit position 
DDRRLEVELCR RHD6-bit mask 
DDRRLEVELCR RHD6-bit position 
DDRRLEVELCR RHD7-bit mask 
DDRRLEVELCR RHD7-bit position 
DDRRLEVELCR RLP0-bit mask 
DDRRLEVELCR RLP0-bit position 
DDRRLEVELCR RLP1-bit mask 
DDRRLEVELCR RLP1-bit position 
DDRRLEVELCR RLP2-bit mask 
DDRRLEVELCR RLP2-bit position 
DDRRLEVELCR RLP3-bit mask 
DDRRLEVELCR RLP3-bit position 
DDRRLEVELCR RLP4-bit mask 
DDRRLEVELCR RLP4-bit position 
DDRRLEVELCR RLP5-bit mask 
DDRRLEVELCR RLP5-bit position 
DDRRLEVELCR RLP6-bit mask 
DDRRLEVELCR RLP6-bit position 
DDRRLEVELCR RLP7-bit mask 
DDRRLEVELCR RLP7-bit position 
DDRSPLITCR HP0-bit mask 
DDRSPLITCR HP0-bit position 
DDRSPLITCR HP1-bit mask 
DDRSPLITCR HP1-bit position 
DDRSPLITCR HP2-bit mask 
DDRSPLITCR HP2-bit position 
DDRSPLITCR HP3-bit mask 
DDRSPLITCR HP3-bit position 
DDRSPLITCR HP4-bit mask 
DDRSPLITCR HP4-bit position 
DDRSPLITCR HP5-bit mask 
DDRSPLITCR HP5-bit position 
DDRSPLITCR HP6-bit mask 
DDRSPLITCR HP6-bit position 
DDRSPLITCR HP7-bit mask 
DDRSPLITCR HP7-bit position 
DDRSPLITCR SD0-bit mask 
DDRSPLITCR SD0-bit position 
DDRSPLITCR SD1-bit mask 
DDRSPLITCR SD1-bit position 
DDRSPLITCR SD2-bit mask 
DDRSPLITCR SD2-bit position 
DDRSPLITCR SD3-bit mask 
DDRSPLITCR SD3-bit position 
DDRSPLITCR SD4-bit mask 
DDRSPLITCR SD4-bit position 
DDRSPLITCR SD5-bit mask 
DDRSPLITCR SD5-bit position 
DDRSPLITCR SD6-bit mask 
DDRSPLITCR SD6-bit position 
DDRSPLITCR SD7-bit mask 
DDRSPLITCR SD7-bit position 
DDRTMPR0 TFAW-bit mask 
DDRTMPR0 TFAW-bit position 
DDRTMPR0 TRAS-bit mask 
DDRTMPR0 TRAS-bit position 
DDRTMPR0 TRC-bit mask 
DDRTMPR0 TRC-bit position 
DDRTMPR0 TRFC-bit mask 
DDRTMPR0 TRFC-bit position 
DDRTMPR1 TMOD-bit mask 
DDRTMPR1 TMOD-bit position 
DDRTMPR1 TMRD-bit mask 
DDRTMPR1 TMRD-bit position 
DDRTMPR1 TRCD-bit mask 
DDRTMPR1 TRCD-bit position 
DDRTMPR1 TRP-bit mask 
DDRTMPR1 TRP-bit position 
DDRTMPR1 TRRD-bit mask 
DDRTMPR1 TRRD-bit position 
DDRTMPR1 TRTP-bit mask 
DDRTMPR1 TRTP-bit position 
DDRTMPR1 TWR-bit mask 
DDRTMPR1 TWR-bit position 
DDRTMPR1 TWTR-bit mask 
DDRTMPR1 TWTR-bit position 
DDRTMPR2 TREFI-bit mask 
DDRTMPR2 TREFI-bit position 
DDRTMPR2 TRTR-bit mask 
DDRTMPR2 TRTR-bit position 
DDRTMPR2 TRTW-bit mask 
DDRTMPR2 TRTW-bit position 
DDRTMPR2 TWTR-bit mask 
DDRTMPR2 TWTR-bit position 
DDRTMPR2 TWTW-bit mask 
DDRTMPR2 TWTW-bit position 
DDRTMPR2 TXSR-bit mask 
DDRTMPR2 TXSR-bit position 
DDRTRAFMR TMCLKCYCLE-bit mask 
DDRTRAFMR TMCLKCYCLE-bit position 
DDRUDEFR VALUE-bit mask 
DDRUDEFR VALUE-bit position 
DDRUPDCR TDLLUP-bit mask 
DDRUPDCR TDLLUP-bit position 
DDRUPDCR TWLVUP-bit mask 
DDRUPDCR TWLVUP-bit position 
DDRUPDCR ZQUD-bit mask 
DDRUPDCR ZQUD-bit position 
DDRWLEVELBHR DELAY4-bit mask 
DDRWLEVELBHR DELAY4-bit position 
DDRWLEVELBHR DELAY5-bit mask 
DDRWLEVELBHR DELAY5-bit position 
DDRWLEVELBHR DELAY6-bit mask 
DDRWLEVELBHR DELAY6-bit position 
DDRWLEVELBHR DELAY7-bit mask 
DDRWLEVELBHR DELAY7-bit position 
DDRWLEVELBLR DELAY0-bit mask 
DDRWLEVELBLR DELAY0-bit position 
DDRWLEVELBLR DELAY1-bit mask 
DDRWLEVELBLR DELAY1-bit position 
DDRWLEVELBLR DELAY2-bit mask 
DDRWLEVELBLR DELAY2-bit position 
DDRWLEVELBLR DELAY3-bit mask 
DDRWLEVELBLR DELAY3-bit position 
DDRWLEVELCR TWL-bit mask 
DDRWLEVELCR TWL-bit position 
DDRWLEVELCR WHD0-bit mask 
DDRWLEVELCR WHD0-bit position 
DDRWLEVELCR WHD1-bit mask 
DDRWLEVELCR WHD1-bit position 
DDRWLEVELCR WHD2-bit mask 
DDRWLEVELCR WHD2-bit position 
DDRWLEVELCR WHD3-bit mask 
DDRWLEVELCR WHD3-bit position 
DDRWLEVELCR WHD4-bit mask 
DDRWLEVELCR WHD4-bit position 
DDRWLEVELCR WHD5-bit mask 
DDRWLEVELCR WHD5-bit position 
DDRWLEVELCR WHD6-bit mask 
DDRWLEVELCR WHD6-bit position 
DDRWLEVELCR WHD7-bit mask 
DDRWLEVELCR WHD7-bit position 
DDRWLEVELCR WLP0-bit mask 
DDRWLEVELCR WLP0-bit position 
DDRWLEVELCR WLP1-bit mask 
DDRWLEVELCR WLP1-bit position 
DDRWLEVELCR WLP2-bit mask 
DDRWLEVELCR WLP2-bit position 
DDRWLEVELCR WLP3-bit mask 
DDRWLEVELCR WLP3-bit position 
DDRWLEVELCR WLP4-bit mask 
DDRWLEVELCR WLP4-bit position 
DDRWLEVELCR WLP5-bit mask 
DDRWLEVELCR WLP5-bit position 
DDRWLEVELCR WLP6-bit mask 
DDRWLEVELCR WLP6-bit position 
DDRWLEVELCR WLP7-bit mask 
DDRWLEVELCR WLP7-bit position 
DDRWRDLLCR WRDLL0-bit mask 
DDRWRDLLCR WRDLL0-bit position 
DDRWRDLLCR WRDLL1-bit mask 
DDRWRDLLCR WRDLL1-bit position 
DDRWRDLLCR WRDLL2-bit mask 
DDRWRDLLCR WRDLL2-bit position 
DDRWRDLLCR WRDLL3-bit mask 
DDRWRDLLCR WRDLL3-bit position 
DDRWRDLLCR WRDLL4-bit mask 
DDRWRDLLCR WRDLL4-bit position 
DDRWRDLLCR WRDLL5-bit mask 
DDRWRDLLCR WRDLL5-bit position 
DDRWRDLLCR WRDLL6-bit mask 
DDRWRDLLCR WRDLL6-bit position 
DDRWRDLLCR WRDLL7-bit mask 
DDRWRDLLCR WRDLL7-bit position 
名前 
説明 
DDR Type 
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