AG903ライブラリリファレンス
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AG903_pbdreg.h
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1: 8: 9: 13: 14:
#ifndef
_AG903_PBD_REGMAP_H_ 15:
#define
_AG903_PBD_REGMAP_H_ 16: 17: 18:
#include
"AG903_regmap.h" 19: 20:
#ifndef
__I
21: 22:
#define
__I
volatile
const
23:
#endif
24:
#ifndef
__O
25: 26:
#define
__O
volatile
27:
#endif
28:
#ifndef
__IO
29: 30:
#define
__IO
volatile
31:
#endif
32: 33: 34:
typedef
struct
{ 35: 36:
union
{ 37:
__IO
uint32_t CONFIG; 38: 39:
struct
{ 40:
__IO
uint32_t W32_L : 1; 41:
__IO
uint32_t BED_L : 1; 42: uint32_t : 6; 43:
__IO
uint32_t RW0_L : 1; 44:
__IO
uint32_t RW1_L : 1; 45: uint32_t : 6; 46:
__IO
uint32_t W32_U : 1; 47:
__IO
uint32_t BED_U : 1; 48: uint32_t : 6; 49:
__IO
uint32_t RW0_U : 1; 50:
__IO
uint32_t RW1_U : 1; 51: } CONFIG_bits; 52: }; 53: 54:
union
{ 55:
__IO
uint32_t WAITDLY; 56: 57:
struct
{ 58:
__IO
uint32_t DLY : 3; 59: } WAITDLY_bits; 60: }; 61: 62:
union
{ 63:
__IO
uint32_t MAPCS0; 64: }; 65: 66:
union
{ 67:
__IO
uint32_t MAPCS1; 68: }; 69: 70:
union
{ 71:
__IO
uint32_t WAITCTRL; 72: 73:
struct
{ 74:
__IO
uint32_t EN : 1; 75:
__IO
uint32_t OD : 1; 76:
__IO
uint32_t POL : 1; 77: } WAITCTRL_bits; 78: }; 79: 80:
union
{ 81:
__IO
uint32_t DMACTRL; 82: 83:
struct
{ 84:
__IO
uint32_t EN : 1; 85:
__IO
uint32_t DCK : 1; 86:
__IO
uint32_t DRQ : 1; 87: } DMACTRL_bits; 88: }; 89: 90:
union
{ 91:
__IO
uint32_t INTMSK; 92: 93:
struct
{ 94:
__IO
uint32_t INT0 : 1; 95:
__IO
uint32_t INT1 : 1; 96: } INTMSK_bits; 97: }; 98: 99:
union
{ 100:
__IO
uint32_t INTPOL; 101: 102:
struct
{ 103:
__IO
uint32_t INT0 : 1; 104:
__IO
uint32_t INT1 : 1; 105: } INTPOL_bits; 106: }; 107: 108:
union
{ 109:
__I
uint32_t IRQMON0; 110: 111:
struct
{ 112:
__I
uint32_t IRQ0 : 2; 113:
__I
uint32_t IRQ1 : 2; 114:
__I
uint32_t IRQ2 : 2; 115:
__I
uint32_t IRQ3 : 2; 116:
__I
uint32_t IRQ4 : 2; 117:
__I
uint32_t IRQ5 : 2; 118:
__I
uint32_t IRQ6 : 2; 119:
__I
uint32_t IRQ7 : 2; 120:
__I
uint32_t IRQ8 : 2; 121:
__I
uint32_t IRQ9 : 2; 122:
__I
uint32_t IRQ10 : 2; 123:
__I
uint32_t IRQ11 : 2; 124:
__I
uint32_t IRQ12 : 2; 125:
__I
uint32_t IRQ13 : 2; 126:
__I
uint32_t IRQ14 : 2; 127:
__I
uint32_t IRQ15 : 2; 128: } IRQMON0_bits; 129: }; 130: 131:
union
{ 132:
__I
uint32_t IRQMON1; 133: 134:
struct
{ 135:
__I
uint32_t IRQ16 : 2; 136:
__I
uint32_t IRQ17 : 2; 137:
__I
uint32_t IRQ18 : 2; 138:
__I
uint32_t IRQ19 : 2; 139:
__I
uint32_t IRQ20 : 2; 140:
__I
uint32_t IRQ21 : 2; 141:
__I
uint32_t IRQ22 : 2; 142:
__I
uint32_t IRQ23 : 2; 143:
__I
uint32_t IRQ24 : 2; 144:
__I
uint32_t IRQ25 : 2; 145:
__I
uint32_t IRQ26 : 2; 146:
__I
uint32_t IRQ27 : 2; 147:
__I
uint32_t IRQ28 : 2; 148:
__I
uint32_t IRQ29 : 2; 149:
__I
uint32_t IRQ30 : 2; 150:
__I
uint32_t IRQ31 : 2; 151: } IRQMON1_bits; 152: }; 153: 154:
union
{ 155:
__I
uint32_t IRQMON2; 156: 157:
struct
{ 158:
__I
uint32_t IRQ32 : 2; 159:
__I
uint32_t IRQ33 : 2; 160:
__I
uint32_t IRQ34 : 2; 161:
__I
uint32_t IRQ35 : 2; 162:
__I
uint32_t IRQ36 : 2; 163:
__I
uint32_t IRQ37 : 2; 164:
__I
uint32_t IRQ38 : 2; 165:
__I
uint32_t IRQ39 : 2; 166:
__I
uint32_t IRQ40 : 2; 167:
__I
uint32_t IRQ41 : 2; 168:
__I
uint32_t IRQ42 : 2; 169:
__I
uint32_t IRQ43 : 2; 170:
__I
uint32_t IRQ44 : 2; 171:
__I
uint32_t IRQ45 : 2; 172:
__I
uint32_t IRQ46 : 2; 173:
__I
uint32_t IRQ47 : 2; 174: } IRQMON2_bits; 175: }; 176: 177:
union
{ 178:
__I
uint32_t IRQMON3; 179: 180:
struct
{ 181:
__I
uint32_t IRQ48 : 2; 182:
__I
uint32_t IRQ49 : 2; 183:
__I
uint32_t IRQ50 : 2; 184:
__I
uint32_t IRQ51 : 2; 185:
__I
uint32_t IRQ52 : 2; 186:
__I
uint32_t IRQ53 : 2; 187:
__I
uint32_t IRQ54 : 2; 188:
__I
uint32_t IRQ55 : 2; 189:
__I
uint32_t IRQ56 : 2; 190:
__I
uint32_t IRQ57 : 2; 191:
__I
uint32_t IRQ58 : 2; 192:
__I
uint32_t IRQ59 : 2; 193:
__I
uint32_t IRQ60 : 2; 194:
__I
uint32_t IRQ61 : 2; 195:
__I
uint32_t IRQ62 : 2; 196:
__I
uint32_t IRQ63 : 2; 197: } IRQMON3_bits; 198: }; 199: 200:
union
{ 201:
__IO
uint32_t IRQSEL0; 202: 203:
struct
{ 204:
__IO
uint32_t IRQ0 : 2; 205:
__IO
uint32_t IRQ1 : 2; 206:
__IO
uint32_t IRQ2 : 2; 207:
__IO
uint32_t IRQ3 : 2; 208:
__IO
uint32_t IRQ4 : 2; 209:
__IO
uint32_t IRQ5 : 2; 210:
__IO
uint32_t IRQ6 : 2; 211:
__IO
uint32_t IRQ7 : 2; 212:
__IO
uint32_t IRQ8 : 2; 213:
__IO
uint32_t IRQ9 : 2; 214:
__IO
uint32_t IRQ10 : 2; 215:
__IO
uint32_t IRQ11 : 2; 216:
__IO
uint32_t IRQ12 : 2; 217:
__IO
uint32_t IRQ13 : 2; 218:
__IO
uint32_t IRQ14 : 2; 219:
__IO
uint32_t IRQ15 : 2; 220: } IRQSEL0_bits; 221: }; 222: 223:
union
{ 224:
__IO
uint32_t IRQSEL1; 225: 226:
struct
{ 227:
__IO
uint32_t IRQ16 : 2; 228:
__IO
uint32_t IRQ17 : 2; 229:
__IO
uint32_t IRQ18 : 2; 230:
__IO
uint32_t IRQ19 : 2; 231:
__IO
uint32_t IRQ20 : 2; 232:
__IO
uint32_t IRQ21 : 2; 233:
__IO
uint32_t IRQ22 : 2; 234:
__IO
uint32_t IRQ23 : 2; 235:
__IO
uint32_t IRQ24 : 2; 236:
__IO
uint32_t IRQ25 : 2; 237:
__IO
uint32_t IRQ26 : 2; 238:
__IO
uint32_t IRQ27 : 2; 239:
__IO
uint32_t IRQ28 : 2; 240:
__IO
uint32_t IRQ29 : 2; 241:
__IO
uint32_t IRQ30 : 2; 242:
__IO
uint32_t IRQ31 : 2; 243: } IRQSEL1_bits; 244: }; 245: 246:
union
{ 247:
__IO
uint32_t IRQSEL2; 248: 249:
struct
{ 250:
__IO
uint32_t IRQ32 : 2; 251:
__IO
uint32_t IRQ33 : 2; 252:
__IO
uint32_t IRQ34 : 2; 253:
__IO
uint32_t IRQ35 : 2; 254:
__IO
uint32_t IRQ36 : 2; 255:
__IO
uint32_t IRQ37 : 2; 256:
__IO
uint32_t IRQ38 : 2; 257:
__IO
uint32_t IRQ39 : 2; 258:
__IO
uint32_t IRQ40 : 2; 259:
__IO
uint32_t IRQ41 : 2; 260:
__IO
uint32_t IRQ42 : 2; 261:
__IO
uint32_t IRQ43 : 2; 262:
__IO
uint32_t IRQ44 : 2; 263:
__IO
uint32_t IRQ45 : 2; 264:
__IO
uint32_t IRQ46 : 2; 265:
__IO
uint32_t IRQ47 : 2; 266: } IRQSEL2_bits; 267: }; 268: 269:
union
{ 270:
__IO
uint32_t IRQSEL3; 271: 272:
struct
{ 273:
__IO
uint32_t IRQ48 : 2; 274:
__IO
uint32_t IRQ49 : 2; 275:
__IO
uint32_t IRQ50 : 2; 276:
__IO
uint32_t IRQ51 : 2; 277:
__IO
uint32_t IRQ52 : 2; 278:
__IO
uint32_t IRQ53 : 2; 279:
__IO
uint32_t IRQ54 : 2; 280:
__IO
uint32_t IRQ55 : 2; 281:
__IO
uint32_t IRQ56 : 2; 282:
__IO
uint32_t IRQ57 : 2; 283:
__IO
uint32_t IRQ58 : 2; 284:
__IO
uint32_t IRQ59 : 2; 285:
__IO
uint32_t IRQ60 : 2; 286:
__IO
uint32_t IRQ61 : 2; 287:
__IO
uint32_t IRQ62 : 2; 288:
__IO
uint32_t IRQ63 : 2; 289: } IRQSEL3_bits; 290: }; 291: 292:
union
{ 293:
__IO
uint32_t MAPMODE; 294: 295:
struct
{ 296:
__IO
uint32_t MODE : 1; 297: } MAPMODE_bits; 298: }; 299: 300:
union
{ 301:
__IO
uint32_t TIMEOUTCONFIG; 302: 303:
struct
{ 304:
__IO
uint32_t TIMEOUT : 16; 305: } TIMEOUTCONFIG_bits; 306: }; 307: 308:
union
{ 309:
__IO
uint32_t TIMEOUTDEFVAL; 310: }; 311: 312:
union
{ 313:
__IO
uint32_t TIMEOUTSTATUS; 314: 315:
struct
{ 316:
__IO
uint32_t TS : 1; 317: uint32_t : 3; 318:
__I
uint32_t RB : 1; 319:
__I
uint32_t WB : 1; 320: } TIMEOUTSTATUS_bits; 321: }; 322: 323:
union
{ 324:
__I
uint32_t TIMEOUTADR; 325: }; 326: 327: 328: }
AG903_PBD_Type
; 329: 330:
#define
AG903_PBD
((
volatile
AG903_PBD_Type
*)
AG903_PBD_BASE
) 331: 332: 333:
#define
AG903_PBD_CONFIG_W32_L_POS
0 334:
#define
AG903_PBD_CONFIG_W32_L_MSK
(0x1UL <<
AG903_PBD_CONFIG_W32_L_POS
) 335:
#define
AG903_PBD_CONFIG_BED_L_POS
1 336:
#define
AG903_PBD_CONFIG_BED_L_MSK
(0x1UL <<
AG903_PBD_CONFIG_BED_L_POS
) 337:
#define
AG903_PBD_CONFIG_RW0_L_POS
8 338:
#define
AG903_PBD_CONFIG_RW0_L_MSK
(0x1UL <<
AG903_PBD_CONFIG_RW0_L_POS
) 339:
#define
AG903_PBD_CONFIG_RW1_L_POS
9 340:
#define
AG903_PBD_CONFIG_RW1_L_MSK
(0x1UL <<
AG903_PBD_CONFIG_RW1_L_POS
) 341:
#define
AG903_PBD_CONFIG_W32_U_POS
16 342:
#define
AG903_PBD_CONFIG_W32_U_MSK
(0x1UL <<
AG903_PBD_CONFIG_W32_U_POS
) 343:
#define
AG903_PBD_CONFIG_BED_U_POS
17 344:
#define
AG903_PBD_CONFIG_BED_U_MSK
(0x1UL <<
AG903_PBD_CONFIG_BED_U_POS
) 345:
#define
AG903_PBD_CONFIG_RW0_U_POS
24 346:
#define
AG903_PBD_CONFIG_RW0_U_MSK
(0x1UL <<
AG903_PBD_CONFIG_RW0_U_POS
) 347:
#define
AG903_PBD_CONFIG_RW1_U_POS
25 348:
#define
AG903_PBD_CONFIG_RW1_U_MSK
(0x1UL <<
AG903_PBD_CONFIG_RW1_U_POS
) 349: 350:
#define
AG903_PBD_WAITDLY_DLY_POS
0 351:
#define
AG903_PBD_WAITDLY_DLY_MSK
(0x7UL <<
AG903_PBD_WAITDLY_DLY_POS
) 352: 353:
#define
AG903_PBD_MAPCS0_BASE_POS
0 354:
#define
AG903_PBD_MAPCS0_BASE_MSK
(0xffffffffUL <<
AG903_PBD_MAPCS0_BASE_POS
) 355: 356:
#define
AG903_PBD_MAPCS1_BASE_POS
0 357:
#define
AG903_PBD_MAPCS1_BASE_MSK
(0xffffffffUL <<
AG903_PBD_MAPCS1_BASE_POS
) 358: 359:
#define
AG903_PBD_WAITCTRL_EN_POS
0 360:
#define
AG903_PBD_WAITCTRL_EN_MSK
(0x1UL <<
AG903_PBD_WAITCTRL_EN_POS
) 361:
#define
AG903_PBD_WAITCTRL_OD_POS
1 362:
#define
AG903_PBD_WAITCTRL_OD_MSK
(0x1UL <<
AG903_PBD_WAITCTRL_OD_POS
) 363:
#define
AG903_PBD_WAITCTRL_POL_POS
2 364:
#define
AG903_PBD_WAITCTRL_POL_MSK
(0x1UL <<
AG903_PBD_WAITCTRL_POL_POS
) 365: 366:
#define
AG903_PBD_DMACTRL_EN_POS
0 367:
#define
AG903_PBD_DMACTRL_EN_MSK
(0x1UL <<
AG903_PBD_DMACTRL_EN_POS
) 368:
#define
AG903_PBD_DMACTRL_DCK_POS
1 369:
#define
AG903_PBD_DMACTRL_DCK_MSK
(0x1UL <<
AG903_PBD_DMACTRL_DCK_POS
) 370:
#define
AG903_PBD_DMACTRL_DRQ_POS
2 371:
#define
AG903_PBD_DMACTRL_DRQ_MSK
(0x1UL <<
AG903_PBD_DMACTRL_DRQ_POS
) 372: 373:
#define
AG903_PBD_INTMSK_INT0_POS
0 374:
#define
AG903_PBD_INTMSK_INT0_MSK
(0x1UL <<
AG903_PBD_INTMSK_INT0_POS
) 375:
#define
AG903_PBD_INTMSK_INT1_POS
1 376:
#define
AG903_PBD_INTMSK_INT1_MSK
(0x1UL <<
AG903_PBD_INTMSK_INT1_POS
) 377: 378:
#define
AG903_PBD_INTPOL_INT0_POS
0 379:
#define
AG903_PBD_INTPOL_INT0_MSK
(0x1UL <<
AG903_PBD_INTPOL_INT0_POS
) 380:
#define
AG903_PBD_INTPOL_INT1_POS
1 381:
#define
AG903_PBD_INTPOL_INT1_MSK
(0x1UL <<
AG903_PBD_INTPOL_INT1_POS
) 382: 383:
#define
AG903_PBD_IRQMON0_IRQ0_POS
0 384:
#define
AG903_PBD_IRQMON0_IRQ0_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ0_POS
) 385:
#define
AG903_PBD_IRQMON0_IRQ1_POS
2 386:
#define
AG903_PBD_IRQMON0_IRQ1_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ1_POS
) 387:
#define
AG903_PBD_IRQMON0_IRQ2_POS
4 388:
#define
AG903_PBD_IRQMON0_IRQ2_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ2_POS
) 389:
#define
AG903_PBD_IRQMON0_IRQ3_POS
6 390:
#define
AG903_PBD_IRQMON0_IRQ3_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ3_POS
) 391:
#define
AG903_PBD_IRQMON0_IRQ4_POS
8 392:
#define
AG903_PBD_IRQMON0_IRQ4_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ4_POS
) 393:
#define
AG903_PBD_IRQMON0_IRQ5_POS
10 394:
#define
AG903_PBD_IRQMON0_IRQ5_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ5_POS
) 395:
#define
AG903_PBD_IRQMON0_IRQ6_POS
12 396:
#define
AG903_PBD_IRQMON0_IRQ6_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ6_POS
) 397:
#define
AG903_PBD_IRQMON0_IRQ7_POS
14 398:
#define
AG903_PBD_IRQMON0_IRQ7_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ7_POS
) 399:
#define
AG903_PBD_IRQMON0_IRQ8_POS
16 400:
#define
AG903_PBD_IRQMON0_IRQ8_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ8_POS
) 401:
#define
AG903_PBD_IRQMON0_IRQ9_POS
18 402:
#define
AG903_PBD_IRQMON0_IRQ9_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ9_POS
) 403:
#define
AG903_PBD_IRQMON0_IRQ10_POS
20 404:
#define
AG903_PBD_IRQMON0_IRQ10_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ10_POS
) 405:
#define
AG903_PBD_IRQMON0_IRQ11_POS
22 406:
#define
AG903_PBD_IRQMON0_IRQ11_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ11_POS
) 407:
#define
AG903_PBD_IRQMON0_IRQ12_POS
24 408:
#define
AG903_PBD_IRQMON0_IRQ12_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ12_POS
) 409:
#define
AG903_PBD_IRQMON0_IRQ13_POS
26 410:
#define
AG903_PBD_IRQMON0_IRQ13_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ13_POS
) 411:
#define
AG903_PBD_IRQMON0_IRQ14_POS
28 412:
#define
AG903_PBD_IRQMON0_IRQ14_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ14_POS
) 413:
#define
AG903_PBD_IRQMON0_IRQ15_POS
30 414:
#define
AG903_PBD_IRQMON0_IRQ15_MSK
(0x3UL <<
AG903_PBD_IRQMON0_IRQ15_POS
) 415: 416:
#define
AG903_PBD_IRQMON1_IRQ16_POS
0 417:
#define
AG903_PBD_IRQMON1_IRQ16_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ16_POS
) 418:
#define
AG903_PBD_IRQMON1_IRQ17_POS
2 419:
#define
AG903_PBD_IRQMON1_IRQ17_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ17_POS
) 420:
#define
AG903_PBD_IRQMON1_IRQ18_POS
4 421:
#define
AG903_PBD_IRQMON1_IRQ18_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ18_POS
) 422:
#define
AG903_PBD_IRQMON1_IRQ19_POS
6 423:
#define
AG903_PBD_IRQMON1_IRQ19_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ19_POS
) 424:
#define
AG903_PBD_IRQMON1_IRQ20_POS
8 425:
#define
AG903_PBD_IRQMON1_IRQ20_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ20_POS
) 426:
#define
AG903_PBD_IRQMON1_IRQ21_POS
10 427:
#define
AG903_PBD_IRQMON1_IRQ21_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ21_POS
) 428:
#define
AG903_PBD_IRQMON1_IRQ22_POS
12 429:
#define
AG903_PBD_IRQMON1_IRQ22_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ22_POS
) 430:
#define
AG903_PBD_IRQMON1_IRQ23_POS
14 431:
#define
AG903_PBD_IRQMON1_IRQ23_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ23_POS
) 432:
#define
AG903_PBD_IRQMON1_IRQ24_POS
16 433:
#define
AG903_PBD_IRQMON1_IRQ24_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ24_POS
) 434:
#define
AG903_PBD_IRQMON1_IRQ25_POS
18 435:
#define
AG903_PBD_IRQMON1_IRQ25_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ25_POS
) 436:
#define
AG903_PBD_IRQMON1_IRQ26_POS
20 437:
#define
AG903_PBD_IRQMON1_IRQ26_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ26_POS
) 438:
#define
AG903_PBD_IRQMON1_IRQ27_POS
22 439:
#define
AG903_PBD_IRQMON1_IRQ27_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ27_POS
) 440:
#define
AG903_PBD_IRQMON1_IRQ28_POS
24 441:
#define
AG903_PBD_IRQMON1_IRQ28_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ28_POS
) 442:
#define
AG903_PBD_IRQMON1_IRQ29_POS
26 443:
#define
AG903_PBD_IRQMON1_IRQ29_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ29_POS
) 444:
#define
AG903_PBD_IRQMON1_IRQ30_POS
28 445:
#define
AG903_PBD_IRQMON1_IRQ30_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ30_POS
) 446:
#define
AG903_PBD_IRQMON1_IRQ31_POS
30 447:
#define
AG903_PBD_IRQMON1_IRQ31_MSK
(0x3UL <<
AG903_PBD_IRQMON1_IRQ31_POS
) 448: 449:
#define
AG903_PBD_IRQMON2_IRQ32_POS
0 450:
#define
AG903_PBD_IRQMON2_IRQ32_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ32_POS
) 451:
#define
AG903_PBD_IRQMON2_IRQ33_POS
2 452:
#define
AG903_PBD_IRQMON2_IRQ33_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ33_POS
) 453:
#define
AG903_PBD_IRQMON2_IRQ34_POS
4 454:
#define
AG903_PBD_IRQMON2_IRQ34_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ34_POS
) 455:
#define
AG903_PBD_IRQMON2_IRQ35_POS
6 456:
#define
AG903_PBD_IRQMON2_IRQ35_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ35_POS
) 457:
#define
AG903_PBD_IRQMON2_IRQ36_POS
8 458:
#define
AG903_PBD_IRQMON2_IRQ36_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ36_POS
) 459:
#define
AG903_PBD_IRQMON2_IRQ37_POS
10 460:
#define
AG903_PBD_IRQMON2_IRQ37_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ37_POS
) 461:
#define
AG903_PBD_IRQMON2_IRQ38_POS
12 462:
#define
AG903_PBD_IRQMON2_IRQ38_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ38_POS
) 463:
#define
AG903_PBD_IRQMON2_IRQ39_POS
14 464:
#define
AG903_PBD_IRQMON2_IRQ39_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ39_POS
) 465:
#define
AG903_PBD_IRQMON2_IRQ40_POS
16 466:
#define
AG903_PBD_IRQMON2_IRQ40_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ40_POS
) 467:
#define
AG903_PBD_IRQMON2_IRQ41_POS
18 468:
#define
AG903_PBD_IRQMON2_IRQ41_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ41_POS
) 469:
#define
AG903_PBD_IRQMON2_IRQ42_POS
20 470:
#define
AG903_PBD_IRQMON2_IRQ42_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ42_POS
) 471:
#define
AG903_PBD_IRQMON2_IRQ43_POS
22 472:
#define
AG903_PBD_IRQMON2_IRQ43_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ43_POS
) 473:
#define
AG903_PBD_IRQMON2_IRQ44_POS
24 474:
#define
AG903_PBD_IRQMON2_IRQ44_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ44_POS
) 475:
#define
AG903_PBD_IRQMON2_IRQ45_POS
26 476:
#define
AG903_PBD_IRQMON2_IRQ45_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ45_POS
) 477:
#define
AG903_PBD_IRQMON2_IRQ46_POS
28 478:
#define
AG903_PBD_IRQMON2_IRQ46_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ46_POS
) 479:
#define
AG903_PBD_IRQMON2_IRQ47_POS
30 480:
#define
AG903_PBD_IRQMON2_IRQ47_MSK
(0x3UL <<
AG903_PBD_IRQMON2_IRQ47_POS
) 481: 482:
#define
AG903_PBD_IRQMON3_IRQ48_POS
0 483:
#define
AG903_PBD_IRQMON3_IRQ48_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ48_POS
) 484:
#define
AG903_PBD_IRQMON3_IRQ49_POS
2 485:
#define
AG903_PBD_IRQMON3_IRQ49_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ49_POS
) 486:
#define
AG903_PBD_IRQMON3_IRQ50_POS
4 487:
#define
AG903_PBD_IRQMON3_IRQ50_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ50_POS
) 488:
#define
AG903_PBD_IRQMON3_IRQ51_POS
6 489:
#define
AG903_PBD_IRQMON3_IRQ51_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ51_POS
) 490:
#define
AG903_PBD_IRQMON3_IRQ52_POS
8 491:
#define
AG903_PBD_IRQMON3_IRQ52_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ52_POS
) 492:
#define
AG903_PBD_IRQMON3_IRQ53_POS
10 493:
#define
AG903_PBD_IRQMON3_IRQ53_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ53_POS
) 494:
#define
AG903_PBD_IRQMON3_IRQ54_POS
12 495:
#define
AG903_PBD_IRQMON3_IRQ54_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ54_POS
) 496:
#define
AG903_PBD_IRQMON3_IRQ55_POS
14 497:
#define
AG903_PBD_IRQMON3_IRQ55_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ55_POS
) 498:
#define
AG903_PBD_IRQMON3_IRQ56_POS
16 499:
#define
AG903_PBD_IRQMON3_IRQ56_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ56_POS
) 500:
#define
AG903_PBD_IRQMON3_IRQ57_POS
18 501:
#define
AG903_PBD_IRQMON3_IRQ57_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ57_POS
) 502:
#define
AG903_PBD_IRQMON3_IRQ58_POS
20 503:
#define
AG903_PBD_IRQMON3_IRQ58_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ58_POS
) 504:
#define
AG903_PBD_IRQMON3_IRQ59_POS
22 505:
#define
AG903_PBD_IRQMON3_IRQ59_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ59_POS
) 506:
#define
AG903_PBD_IRQMON3_IRQ60_POS
24 507:
#define
AG903_PBD_IRQMON3_IRQ60_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ60_POS
) 508:
#define
AG903_PBD_IRQMON3_IRQ61_POS
26 509:
#define
AG903_PBD_IRQMON3_IRQ61_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ61_POS
) 510:
#define
AG903_PBD_IRQMON3_IRQ62_POS
28 511:
#define
AG903_PBD_IRQMON3_IRQ62_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ62_POS
) 512:
#define
AG903_PBD_IRQMON3_IRQ63_POS
30 513:
#define
AG903_PBD_IRQMON3_IRQ63_MSK
(0x3UL <<
AG903_PBD_IRQMON3_IRQ63_POS
) 514: 515:
#define
AG903_PBD_IRQSEL0_IRQ0_POS
0 516:
#define
AG903_PBD_IRQSEL0_IRQ0_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ0_POS
) 517:
#define
AG903_PBD_IRQSEL0_IRQ1_POS
2 518:
#define
AG903_PBD_IRQSEL0_IRQ1_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ1_POS
) 519:
#define
AG903_PBD_IRQSEL0_IRQ2_POS
4 520:
#define
AG903_PBD_IRQSEL0_IRQ2_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ2_POS
) 521:
#define
AG903_PBD_IRQSEL0_IRQ3_POS
6 522:
#define
AG903_PBD_IRQSEL0_IRQ3_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ3_POS
) 523:
#define
AG903_PBD_IRQSEL0_IRQ4_POS
8 524:
#define
AG903_PBD_IRQSEL0_IRQ4_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ4_POS
) 525:
#define
AG903_PBD_IRQSEL0_IRQ5_POS
10 526:
#define
AG903_PBD_IRQSEL0_IRQ5_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ5_POS
) 527:
#define
AG903_PBD_IRQSEL0_IRQ6_POS
12 528:
#define
AG903_PBD_IRQSEL0_IRQ6_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ6_POS
) 529:
#define
AG903_PBD_IRQSEL0_IRQ7_POS
14 530:
#define
AG903_PBD_IRQSEL0_IRQ7_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ7_POS
) 531:
#define
AG903_PBD_IRQSEL0_IRQ8_POS
16 532:
#define
AG903_PBD_IRQSEL0_IRQ8_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ8_POS
) 533:
#define
AG903_PBD_IRQSEL0_IRQ9_POS
18 534:
#define
AG903_PBD_IRQSEL0_IRQ9_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ9_POS
) 535:
#define
AG903_PBD_IRQSEL0_IRQ10_POS
20 536:
#define
AG903_PBD_IRQSEL0_IRQ10_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ10_POS
) 537:
#define
AG903_PBD_IRQSEL0_IRQ11_POS
22 538:
#define
AG903_PBD_IRQSEL0_IRQ11_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ11_POS
) 539:
#define
AG903_PBD_IRQSEL0_IRQ12_POS
24 540:
#define
AG903_PBD_IRQSEL0_IRQ12_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ12_POS
) 541:
#define
AG903_PBD_IRQSEL0_IRQ13_POS
26 542:
#define
AG903_PBD_IRQSEL0_IRQ13_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ13_POS
) 543:
#define
AG903_PBD_IRQSEL0_IRQ14_POS
28 544:
#define
AG903_PBD_IRQSEL0_IRQ14_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ14_POS
) 545:
#define
AG903_PBD_IRQSEL0_IRQ15_POS
30 546:
#define
AG903_PBD_IRQSEL0_IRQ15_MSK
(0x3UL <<
AG903_PBD_IRQSEL0_IRQ15_POS
) 547: 548:
#define
AG903_PBD_IRQSEL1_IRQ16_POS
0 549:
#define
AG903_PBD_IRQSEL1_IRQ16_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ16_POS
) 550:
#define
AG903_PBD_IRQSEL1_IRQ17_POS
2 551:
#define
AG903_PBD_IRQSEL1_IRQ17_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ17_POS
) 552:
#define
AG903_PBD_IRQSEL1_IRQ18_POS
4 553:
#define
AG903_PBD_IRQSEL1_IRQ18_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ18_POS
) 554:
#define
AG903_PBD_IRQSEL1_IRQ19_POS
6 555:
#define
AG903_PBD_IRQSEL1_IRQ19_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ19_POS
) 556:
#define
AG903_PBD_IRQSEL1_IRQ20_POS
8 557:
#define
AG903_PBD_IRQSEL1_IRQ20_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ20_POS
) 558:
#define
AG903_PBD_IRQSEL1_IRQ21_POS
10 559:
#define
AG903_PBD_IRQSEL1_IRQ21_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ21_POS
) 560:
#define
AG903_PBD_IRQSEL1_IRQ22_POS
12 561:
#define
AG903_PBD_IRQSEL1_IRQ22_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ22_POS
) 562:
#define
AG903_PBD_IRQSEL1_IRQ23_POS
14 563:
#define
AG903_PBD_IRQSEL1_IRQ23_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ23_POS
) 564:
#define
AG903_PBD_IRQSEL1_IRQ24_POS
16 565:
#define
AG903_PBD_IRQSEL1_IRQ24_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ24_POS
) 566:
#define
AG903_PBD_IRQSEL1_IRQ25_POS
18 567:
#define
AG903_PBD_IRQSEL1_IRQ25_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ25_POS
) 568:
#define
AG903_PBD_IRQSEL1_IRQ26_POS
20 569:
#define
AG903_PBD_IRQSEL1_IRQ26_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ26_POS
) 570:
#define
AG903_PBD_IRQSEL1_IRQ27_POS
22 571:
#define
AG903_PBD_IRQSEL1_IRQ27_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ27_POS
) 572:
#define
AG903_PBD_IRQSEL1_IRQ28_POS
24 573:
#define
AG903_PBD_IRQSEL1_IRQ28_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ28_POS
) 574:
#define
AG903_PBD_IRQSEL1_IRQ29_POS
26 575:
#define
AG903_PBD_IRQSEL1_IRQ29_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ29_POS
) 576:
#define
AG903_PBD_IRQSEL1_IRQ30_POS
28 577:
#define
AG903_PBD_IRQSEL1_IRQ30_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ30_POS
) 578:
#define
AG903_PBD_IRQSEL1_IRQ31_POS
30 579:
#define
AG903_PBD_IRQSEL1_IRQ31_MSK
(0x3UL <<
AG903_PBD_IRQSEL1_IRQ31_POS
) 580: 581:
#define
AG903_PBD_IRQSEL2_IRQ32_POS
0 582:
#define
AG903_PBD_IRQSEL2_IRQ32_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ32_POS
) 583:
#define
AG903_PBD_IRQSEL2_IRQ33_POS
2 584:
#define
AG903_PBD_IRQSEL2_IRQ33_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ33_POS
) 585:
#define
AG903_PBD_IRQSEL2_IRQ34_POS
4 586:
#define
AG903_PBD_IRQSEL2_IRQ34_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ34_POS
) 587:
#define
AG903_PBD_IRQSEL2_IRQ35_POS
6 588:
#define
AG903_PBD_IRQSEL2_IRQ35_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ35_POS
) 589:
#define
AG903_PBD_IRQSEL2_IRQ36_POS
8 590:
#define
AG903_PBD_IRQSEL2_IRQ36_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ36_POS
) 591:
#define
AG903_PBD_IRQSEL2_IRQ37_POS
10 592:
#define
AG903_PBD_IRQSEL2_IRQ37_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ37_POS
) 593:
#define
AG903_PBD_IRQSEL2_IRQ38_POS
12 594:
#define
AG903_PBD_IRQSEL2_IRQ38_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ38_POS
) 595:
#define
AG903_PBD_IRQSEL2_IRQ39_POS
14 596:
#define
AG903_PBD_IRQSEL2_IRQ39_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ39_POS
) 597:
#define
AG903_PBD_IRQSEL2_IRQ40_POS
16 598:
#define
AG903_PBD_IRQSEL2_IRQ40_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ40_POS
) 599:
#define
AG903_PBD_IRQSEL2_IRQ41_POS
18 600:
#define
AG903_PBD_IRQSEL2_IRQ41_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ41_POS
) 601:
#define
AG903_PBD_IRQSEL2_IRQ42_POS
20 602:
#define
AG903_PBD_IRQSEL2_IRQ42_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ42_POS
) 603:
#define
AG903_PBD_IRQSEL2_IRQ43_POS
22 604:
#define
AG903_PBD_IRQSEL2_IRQ43_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ43_POS
) 605:
#define
AG903_PBD_IRQSEL2_IRQ44_POS
24 606:
#define
AG903_PBD_IRQSEL2_IRQ44_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ44_POS
) 607:
#define
AG903_PBD_IRQSEL2_IRQ45_POS
26 608:
#define
AG903_PBD_IRQSEL2_IRQ45_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ45_POS
) 609:
#define
AG903_PBD_IRQSEL2_IRQ46_POS
28 610:
#define
AG903_PBD_IRQSEL2_IRQ46_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ46_POS
) 611:
#define
AG903_PBD_IRQSEL2_IRQ47_POS
30 612:
#define
AG903_PBD_IRQSEL2_IRQ47_MSK
(0x3UL <<
AG903_PBD_IRQSEL2_IRQ47_POS
) 613: 614:
#define
AG903_PBD_IRQSEL3_IRQ48_POS
0 615:
#define
AG903_PBD_IRQSEL3_IRQ48_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ48_POS
) 616:
#define
AG903_PBD_IRQSEL3_IRQ49_POS
2 617:
#define
AG903_PBD_IRQSEL3_IRQ49_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ49_POS
) 618:
#define
AG903_PBD_IRQSEL3_IRQ50_POS
4 619:
#define
AG903_PBD_IRQSEL3_IRQ50_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ50_POS
) 620:
#define
AG903_PBD_IRQSEL3_IRQ51_POS
6 621:
#define
AG903_PBD_IRQSEL3_IRQ51_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ51_POS
) 622:
#define
AG903_PBD_IRQSEL3_IRQ52_POS
8 623:
#define
AG903_PBD_IRQSEL3_IRQ52_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ52_POS
) 624:
#define
AG903_PBD_IRQSEL3_IRQ53_POS
10 625:
#define
AG903_PBD_IRQSEL3_IRQ53_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ53_POS
) 626:
#define
AG903_PBD_IRQSEL3_IRQ54_POS
12 627:
#define
AG903_PBD_IRQSEL3_IRQ54_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ54_POS
) 628:
#define
AG903_PBD_IRQSEL3_IRQ55_POS
14 629:
#define
AG903_PBD_IRQSEL3_IRQ55_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ55_POS
) 630:
#define
AG903_PBD_IRQSEL3_IRQ56_POS
16 631:
#define
AG903_PBD_IRQSEL3_IRQ56_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ56_POS
) 632:
#define
AG903_PBD_IRQSEL3_IRQ57_POS
18 633:
#define
AG903_PBD_IRQSEL3_IRQ57_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ57_POS
) 634:
#define
AG903_PBD_IRQSEL3_IRQ58_POS
20 635:
#define
AG903_PBD_IRQSEL3_IRQ58_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ58_POS
) 636:
#define
AG903_PBD_IRQSEL3_IRQ59_POS
22 637:
#define
AG903_PBD_IRQSEL3_IRQ59_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ59_POS
) 638:
#define
AG903_PBD_IRQSEL3_IRQ60_POS
24 639:
#define
AG903_PBD_IRQSEL3_IRQ60_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ60_POS
) 640:
#define
AG903_PBD_IRQSEL3_IRQ61_POS
26 641:
#define
AG903_PBD_IRQSEL3_IRQ61_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ61_POS
) 642:
#define
AG903_PBD_IRQSEL3_IRQ62_POS
28 643:
#define
AG903_PBD_IRQSEL3_IRQ62_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ62_POS
) 644:
#define
AG903_PBD_IRQSEL3_IRQ63_POS
30 645:
#define
AG903_PBD_IRQSEL3_IRQ63_MSK
(0x3UL <<
AG903_PBD_IRQSEL3_IRQ63_POS
) 646: 647:
#define
AG903_PBD_MAPMODE_MODE_POS
0 648:
#define
AG903_PBD_MAPMODE_MODE_MSK
(0x1UL <<
AG903_PBD_MAPMODE_MODE_POS
) 649: 650:
#define
AG903_PBD_TIMEOUTCONFIG_TIMEOUT_POS
0 651:
#define
AG903_PBD_TIMEOUTCONFIG_TIMEOUT_MSK
(0xffffUL <<
AG903_PBD_TIMEOUTCONFIG_TIMEOUT_POS
) 652: 653:
#define
AG903_PBD_TIMEOUTDEFVAL_DEFVAL_POS
0 654:
#define
AG903_PBD_TIMEOUTDEFVAL_DEFVAL_MSK
(0xffffffffUL <<
AG903_PBD_TIMEOUTDEFVAL_DEFVAL_POS
) 655: 656:
#define
AG903_PBD_TIMEOUTSTATUS_TS_POS
0 657:
#define
AG903_PBD_TIMEOUTSTATUS_TS_MSK
(0x1UL <<
AG903_PBD_TIMEOUTSTATUS_TS_POS
) 658:
#define
AG903_PBD_TIMEOUTSTATUS_RB_POS
4 659:
#define
AG903_PBD_TIMEOUTSTATUS_RB_MSK
(0x1UL <<
AG903_PBD_TIMEOUTSTATUS_RB_POS
) 660:
#define
AG903_PBD_TIMEOUTSTATUS_WB_POS
5 661:
#define
AG903_PBD_TIMEOUTSTATUS_WB_MSK
(0x1UL <<
AG903_PBD_TIMEOUTSTATUS_WB_POS
) 662: 663:
#define
AG903_PBD_TIMEOUTADR_ADR_POS
0 664:
#define
AG903_PBD_TIMEOUTADR_ADR_MSK
(0xffffffffUL <<
AG903_PBD_TIMEOUTADR_ADR_POS
) 665: 666: 667:
#endif
668:
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