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AG903_sspreg.h

SSP Register Definition

SSP Register Definition

none

AXELL CORPORATION

2017_10_20 Auto-generated.

1: 8: 9: 13: 14: #ifndef _AG903_SSP_REGMAP_H_ 15: #define _AG903_SSP_REGMAP_H_ 16: 17: 18: #include "AG903_regmap.h" 19: 20: #ifndef __I 21: 22: #define __I volatile const 23: #endif 24: #ifndef __O 25: 26: #define __O volatile 27: #endif 28: #ifndef __IO 29: 30: #define __IO volatile 31: #endif 32: 33: 34: typedef struct { 35: 36: union { 37: __IO uint32_t SSPCR0; 38: 39: struct { 40: __IO uint32_t SCLKPH : 1; 41: __IO uint32_t SCLKPO : 1; 42: __IO uint32_t OPM : 2; 43: __IO uint32_t FSJSTFY : 1; 44: __IO uint32_t FSPO : 1; 45: __IO uint32_t LSB : 1; 46: __IO uint32_t LBM : 1; 47: __IO uint32_t FSDIST : 2; 48: __IO uint32_t Validity : 1; 49: __IO uint32_t FLASH : 1; 50: __IO uint32_t FFMT : 3; 51: __IO uint32_t SPIFSPO : 1; 52: __IO uint32_t SCLKFDBK : 1; 53: __IO uint32_t FSFDBK : 1; 54: } SSPCR0_bits; 55: }; 56: 57: union { 58: __IO uint32_t SSPCR1; 59: 60: struct { 61: __IO uint32_t SCLKDIV : 16; 62: __IO uint32_t SDL : 7; 63: uint32_t : 1; 64: __IO uint32_t PDL : 8; 65: } SSPCR1_bits; 66: }; 67: 68: union { 69: __IO uint32_t SSPCR2; 70: 71: struct { 72: __IO uint32_t SSPEN : 1; 73: __IO uint32_t TXDOE : 1; 74: __IO uint32_t RXFCLR : 1; 75: __IO uint32_t TXFCLR : 1; 76: uint32_t : 2; 77: __IO uint32_t SSPRST : 1; 78: __IO uint32_t RXEN : 1; 79: __IO uint32_t TXEN : 1; 80: __IO uint32_t FS : 1; 81: __IO uint32_t FSOS : 2; 82: } SSPCR2_bits; 83: }; 84: 85: union { 86: __I uint32_t SSPStatus; 87: 88: struct { 89: __I uint32_t RFF : 1; 90: __I uint32_t TFNF : 1; 91: __I uint32_t BUSY : 1; 92: uint32_t : 1; 93: __I uint32_t RFVE : 6; 94: uint32_t : 2; 95: __I uint32_t TFVE : 6; 96: } SSPStatus_bits; 97: }; 98: 99: union { 100: __IO uint32_t IntrCR; 101: 102: struct { 103: __IO uint32_t RFORIEN : 1; 104: __IO uint32_t TFURIEN : 1; 105: __IO uint32_t RFTHIEN : 1; 106: __IO uint32_t TFTHIEN : 1; 107: __IO uint32_t RFDMAEN : 1; 108: __IO uint32_t TFDMAEN : 1; 109: uint32_t : 1; 110: __IO uint32_t RFTHOD : 5; 111: __IO uint32_t TFTHOD : 5; 112: } IntrCR_bits; 113: }; 114: 115: union { 116: __I uint32_t IntrStatus; 117: 118: struct { 119: __I uint32_t RFORI : 1; 120: __I uint32_t TFURI : 1; 121: __I uint32_t RFTHI : 1; 122: __I uint32_t TFTHI : 1; 123: } IntrStatus_bits; 124: }; 125: 126: union { 127: __IO uint32_t TxRxDR; 128: }; 129: 130: __I uint32_t RESERVED1[2]; 131: 132: union { 133: __IO uint32_t SPDIFStatus0; 134: 135: struct { 136: __IO uint32_t STUS0 : 8; 137: __IO uint32_t STUS1 : 8; 138: __IO uint32_t STUS2 : 8; 139: __IO uint32_t STUS3 : 8; 140: } SPDIFStatus0_bits; 141: }; 142: 143: union { 144: __IO uint32_t SPDIFStatus1; 145: 146: struct { 147: __IO uint32_t STUS4 : 8; 148: } SPDIFStatus1_bits; 149: }; 150: 151: union { 152: __IO uint32_t SPDIFUser0; 153: }; 154: 155: union { 156: __IO uint32_t SPDIFUser1; 157: }; 158: 159: union { 160: __IO uint32_t SPDIFUser2; 161: }; 162: 163: union { 164: __IO uint32_t SPDIFUser3; 165: }; 166: 167: union { 168: __IO uint32_t SPDIFUser4; 169: }; 170: 171: union { 172: __IO uint32_t SPDIFUser5; 173: }; 174: 175: union { 176: __IO uint32_t SPDIFUser6; 177: }; 178: 179: union { 180: __IO uint32_t SPDIFUser7; 181: }; 182: 183: union { 184: __IO uint32_t SPDIFUser8; 185: }; 186: 187: union { 188: __IO uint32_t SPDIFUser9; 189: }; 190: 191: union { 192: __IO uint32_t SPDIFUser10; 193: }; 194: 195: union { 196: __IO uint32_t SPDIFUser11; 197: }; 198: 199: __I uint32_t RESERVED2[1]; 200: 201: union { 202: __I uint32_t SSPRevision; 203: 204: struct { 205: __I uint32_t REL_REV : 8; 206: __I uint32_t MINOR_REV : 8; 207: __I uint32_t MAJOR_REV : 8; 208: } SSPRevision_bits; 209: }; 210: 211: union { 212: __I uint32_t SSPFeature; 213: 214: struct { 215: __I uint32_t FIFO_WIDTH : 8; 216: __I uint32_t RXFIFO_DEPTH : 8; 217: __I uint32_t TXFIFO_DEPTH : 8; 218: uint32_t : 1; 219: __I uint32_t I2S_FCFG : 1; 220: __I uint32_t SPIMWR_FCFG : 1; 221: __I uint32_t SSP_FCFG : 1; 222: __I uint32_t SPDIF_FCFG : 1; 223: __I uint32_t EXT_FSNUM : 2; 224: } SSPFeature_bits; 225: }; 226: 227: 228: }AG903_SSPn_Type; 229: 230: #define AG903_SSPn(ch) ((volatile AG903_SSPn_Type *)(AG903_SSP0_BASE + 0x100000 * ch)) 231: #define AG903_SSPn_SSPCR0(ch) AG903_SSPn(ch)->SSPCR0 232: #define AG903_SSPn_SSPCR1(ch) AG903_SSPn(ch)->SSPCR1 233: #define AG903_SSPn_SSPCR2(ch) AG903_SSPn(ch)->SSPCR2 234: #define AG903_SSPn_SSPStatus(ch) AG903_SSPn(ch)->SSPStatus 235: #define AG903_SSPn_IntrCR(ch) AG903_SSPn(ch)->IntrCR 236: #define AG903_SSPn_IntrStatus(ch) AG903_SSPn(ch)->IntrStatus 237: #define AG903_SSPn_TxRxDR(ch) AG903_SSPn(ch)->TxRxDR 238: #define AG903_SSPn_SPDIFStatus0(ch) AG903_SSPn(ch)->SPDIFStatus0 239: #define AG903_SSPn_SPDIFStatus1(ch) AG903_SSPn(ch)->SPDIFStatus1 240: #define AG903_SSPn_SPDIFUser0(ch) AG903_SSPn(ch)->SPDIFUser0 241: #define AG903_SSPn_SPDIFUser1(ch) AG903_SSPn(ch)->SPDIFUser1 242: #define AG903_SSPn_SPDIFUser2(ch) AG903_SSPn(ch)->SPDIFUser2 243: #define AG903_SSPn_SPDIFUser3(ch) AG903_SSPn(ch)->SPDIFUser3 244: #define AG903_SSPn_SPDIFUser4(ch) AG903_SSPn(ch)->SPDIFUser4 245: #define AG903_SSPn_SPDIFUser5(ch) AG903_SSPn(ch)->SPDIFUser5 246: #define AG903_SSPn_SPDIFUser6(ch) AG903_SSPn(ch)->SPDIFUser6 247: #define AG903_SSPn_SPDIFUser7(ch) AG903_SSPn(ch)->SPDIFUser7 248: #define AG903_SSPn_SPDIFUser8(ch) AG903_SSPn(ch)->SPDIFUser8 249: #define AG903_SSPn_SPDIFUser9(ch) AG903_SSPn(ch)->SPDIFUser9 250: #define AG903_SSPn_SPDIFUser10(ch) AG903_SSPn(ch)->SPDIFUser10 251: #define AG903_SSPn_SPDIFUser11(ch) AG903_SSPn(ch)->SPDIFUser11 252: #define AG903_SSPn_SSPRevision(ch) AG903_SSPn(ch)->SSPRevision 253: #define AG903_SSPn_SSPFeature(ch) AG903_SSPn(ch)->SSPFeature 254: 255: #define AG903_SSP0 ((volatile AG903_SSPn_Type *) AG903_SSP0_BASE) 256: #define AG903_SSP1 ((volatile AG903_SSPn_Type *) AG903_SSP1_BASE) 257: #define AG903_SSP2 ((volatile AG903_SSPn_Type *) AG903_SSP2_BASE) 258: #define AG903_SSP3 ((volatile AG903_SSPn_Type *) AG903_SSP3_BASE) 259: 260: 261: #define AG903_SSPn_SSPCR0_SCLKPH_POS 0 262: #define AG903_SSPn_SSPCR0_SCLKPH_MSK (0x1UL << AG903_SSPn_SSPCR0_SCLKPH_POS) 263: #define AG903_SSPn_SSPCR0_SCLKPO_POS 1 264: #define AG903_SSPn_SSPCR0_SCLKPO_MSK (0x1UL << AG903_SSPn_SSPCR0_SCLKPO_POS) 265: #define AG903_SSPn_SSPCR0_OPM_POS 2 266: #define AG903_SSPn_SSPCR0_OPM_MSK (0x3UL << AG903_SSPn_SSPCR0_OPM_POS) 267: #define AG903_SSPn_SSPCR0_FSJSTFY_POS 4 268: #define AG903_SSPn_SSPCR0_FSJSTFY_MSK (0x1UL << AG903_SSPn_SSPCR0_FSJSTFY_POS) 269: #define AG903_SSPn_SSPCR0_FSPO_POS 5 270: #define AG903_SSPn_SSPCR0_FSPO_MSK (0x1UL << AG903_SSPn_SSPCR0_FSPO_POS) 271: #define AG903_SSPn_SSPCR0_LSB_POS 6 272: #define AG903_SSPn_SSPCR0_LSB_MSK (0x1UL << AG903_SSPn_SSPCR0_LSB_POS) 273: #define AG903_SSPn_SSPCR0_LBM_POS 7 274: #define AG903_SSPn_SSPCR0_LBM_MSK (0x1UL << AG903_SSPn_SSPCR0_LBM_POS) 275: #define AG903_SSPn_SSPCR0_FSDIST_POS 8 276: #define AG903_SSPn_SSPCR0_FSDIST_MSK (0x3UL << AG903_SSPn_SSPCR0_FSDIST_POS) 277: #define AG903_SSPn_SSPCR0_Validity_POS 10 278: #define AG903_SSPn_SSPCR0_Validity_MSK (0x1UL << AG903_SSPn_SSPCR0_Validity_POS) 279: #define AG903_SSPn_SSPCR0_FLASH_POS 11 280: #define AG903_SSPn_SSPCR0_FLASH_MSK (0x1UL << AG903_SSPn_SSPCR0_FLASH_POS) 281: #define AG903_SSPn_SSPCR0_FFMT_POS 12 282: #define AG903_SSPn_SSPCR0_FFMT_MSK (0x7UL << AG903_SSPn_SSPCR0_FFMT_POS) 283: #define AG903_SSPn_SSPCR0_SPIFSPO_POS 15 284: #define AG903_SSPn_SSPCR0_SPIFSPO_MSK (0x1UL << AG903_SSPn_SSPCR0_SPIFSPO_POS) 285: #define AG903_SSPn_SSPCR0_SCLKFDBK_POS 16 286: #define AG903_SSPn_SSPCR0_SCLKFDBK_MSK (0x1UL << AG903_SSPn_SSPCR0_SCLKFDBK_POS) 287: #define AG903_SSPn_SSPCR0_FSFDBK_POS 17 288: #define AG903_SSPn_SSPCR0_FSFDBK_MSK (0x1UL << AG903_SSPn_SSPCR0_FSFDBK_POS) 289: 290: #define AG903_SSPn_SSPCR1_SCLKDIV_POS 0 291: #define AG903_SSPn_SSPCR1_SCLKDIV_MSK (0xffffUL << AG903_SSPn_SSPCR1_SCLKDIV_POS) 292: #define AG903_SSPn_SSPCR1_SDL_POS 16 293: #define AG903_SSPn_SSPCR1_SDL_MSK (0x7fUL << AG903_SSPn_SSPCR1_SDL_POS) 294: #define AG903_SSPn_SSPCR1_PDL_POS 24 295: #define AG903_SSPn_SSPCR1_PDL_MSK (0xffUL << AG903_SSPn_SSPCR1_PDL_POS) 296: 297: #define AG903_SSPn_SSPCR2_SSPEN_POS 0 298: #define AG903_SSPn_SSPCR2_SSPEN_MSK (0x1UL << AG903_SSPn_SSPCR2_SSPEN_POS) 299: #define AG903_SSPn_SSPCR2_TXDOE_POS 1 300: #define AG903_SSPn_SSPCR2_TXDOE_MSK (0x1UL << AG903_SSPn_SSPCR2_TXDOE_POS) 301: #define AG903_SSPn_SSPCR2_RXFCLR_POS 2 302: #define AG903_SSPn_SSPCR2_RXFCLR_MSK (0x1UL << AG903_SSPn_SSPCR2_RXFCLR_POS) 303: #define AG903_SSPn_SSPCR2_TXFCLR_POS 3 304: #define AG903_SSPn_SSPCR2_TXFCLR_MSK (0x1UL << AG903_SSPn_SSPCR2_TXFCLR_POS) 305: #define AG903_SSPn_SSPCR2_SSPRST_POS 6 306: #define AG903_SSPn_SSPCR2_SSPRST_MSK (0x1UL << AG903_SSPn_SSPCR2_SSPRST_POS) 307: #define AG903_SSPn_SSPCR2_RXEN_POS 7 308: #define AG903_SSPn_SSPCR2_RXEN_MSK (0x1UL << AG903_SSPn_SSPCR2_RXEN_POS) 309: #define AG903_SSPn_SSPCR2_TXEN_POS 8 310: #define AG903_SSPn_SSPCR2_TXEN_MSK (0x1UL << AG903_SSPn_SSPCR2_TXEN_POS) 311: #define AG903_SSPn_SSPCR2_FS_POS 9 312: #define AG903_SSPn_SSPCR2_FS_MSK (0x1UL << AG903_SSPn_SSPCR2_FS_POS) 313: #define AG903_SSPn_SSPCR2_FSOS_POS 10 314: #define AG903_SSPn_SSPCR2_FSOS_MSK (0x3UL << AG903_SSPn_SSPCR2_FSOS_POS) 315: 316: #define AG903_SSPn_SSPStatus_RFF_POS 0 317: #define AG903_SSPn_SSPStatus_RFF_MSK (0x1UL << AG903_SSPn_SSPStatus_RFF_POS) 318: #define AG903_SSPn_SSPStatus_TFNF_POS 1 319: #define AG903_SSPn_SSPStatus_TFNF_MSK (0x1UL << AG903_SSPn_SSPStatus_TFNF_POS) 320: #define AG903_SSPn_SSPStatus_BUSY_POS 2 321: #define AG903_SSPn_SSPStatus_BUSY_MSK (0x1UL << AG903_SSPn_SSPStatus_BUSY_POS) 322: #define AG903_SSPn_SSPStatus_RFVE_POS 4 323: #define AG903_SSPn_SSPStatus_RFVE_MSK (0x3fUL << AG903_SSPn_SSPStatus_RFVE_POS) 324: #define AG903_SSPn_SSPStatus_TFVE_POS 12 325: #define AG903_SSPn_SSPStatus_TFVE_MSK (0x3fUL << AG903_SSPn_SSPStatus_TFVE_POS) 326: 327: #define AG903_SSPn_IntrCR_RFORIEN_POS 0 328: #define AG903_SSPn_IntrCR_RFORIEN_MSK (0x1UL << AG903_SSPn_IntrCR_RFORIEN_POS) 329: #define AG903_SSPn_IntrCR_TFURIEN_POS 1 330: #define AG903_SSPn_IntrCR_TFURIEN_MSK (0x1UL << AG903_SSPn_IntrCR_TFURIEN_POS) 331: #define AG903_SSPn_IntrCR_RFTHIEN_POS 2 332: #define AG903_SSPn_IntrCR_RFTHIEN_MSK (0x1UL << AG903_SSPn_IntrCR_RFTHIEN_POS) 333: #define AG903_SSPn_IntrCR_TFTHIEN_POS 3 334: #define AG903_SSPn_IntrCR_TFTHIEN_MSK (0x1UL << AG903_SSPn_IntrCR_TFTHIEN_POS) 335: #define AG903_SSPn_IntrCR_RFDMAEN_POS 4 336: #define AG903_SSPn_IntrCR_RFDMAEN_MSK (0x1UL << AG903_SSPn_IntrCR_RFDMAEN_POS) 337: #define AG903_SSPn_IntrCR_TFDMAEN_POS 5 338: #define AG903_SSPn_IntrCR_TFDMAEN_MSK (0x1UL << AG903_SSPn_IntrCR_TFDMAEN_POS) 339: #define AG903_SSPn_IntrCR_RFTHOD_POS 7 340: #define AG903_SSPn_IntrCR_RFTHOD_MSK (0x1fUL << AG903_SSPn_IntrCR_RFTHOD_POS) 341: #define AG903_SSPn_IntrCR_TFTHOD_POS 12 342: #define AG903_SSPn_IntrCR_TFTHOD_MSK (0x1fUL << AG903_SSPn_IntrCR_TFTHOD_POS) 343: 344: #define AG903_SSPn_IntrStatus_RFORI_POS 0 345: #define AG903_SSPn_IntrStatus_RFORI_MSK (0x1UL << AG903_SSPn_IntrStatus_RFORI_POS) 346: #define AG903_SSPn_IntrStatus_TFURI_POS 1 347: #define AG903_SSPn_IntrStatus_TFURI_MSK (0x1UL << AG903_SSPn_IntrStatus_TFURI_POS) 348: #define AG903_SSPn_IntrStatus_RFTHI_POS 2 349: #define AG903_SSPn_IntrStatus_RFTHI_MSK (0x1UL << AG903_SSPn_IntrStatus_RFTHI_POS) 350: #define AG903_SSPn_IntrStatus_TFTHI_POS 3 351: #define AG903_SSPn_IntrStatus_TFTHI_MSK (0x1UL << AG903_SSPn_IntrStatus_TFTHI_POS) 352: 353: #define AG903_SSPn_TxRxDR_DATA_POS 0 354: #define AG903_SSPn_TxRxDR_DATA_MSK (0xffffffffUL << AG903_SSPn_TxRxDR_DATA_POS) 355: 356: #define AG903_SSPn_SPDIFStatus0_STUS0_POS 0 357: #define AG903_SSPn_SPDIFStatus0_STUS0_MSK (0xffUL << AG903_SSPn_SPDIFStatus0_STUS0_POS) 358: #define AG903_SSPn_SPDIFStatus0_STUS1_POS 8 359: #define AG903_SSPn_SPDIFStatus0_STUS1_MSK (0xffUL << AG903_SSPn_SPDIFStatus0_STUS1_POS) 360: #define AG903_SSPn_SPDIFStatus0_STUS2_POS 16 361: #define AG903_SSPn_SPDIFStatus0_STUS2_MSK (0xffUL << AG903_SSPn_SPDIFStatus0_STUS2_POS) 362: #define AG903_SSPn_SPDIFStatus0_STUS3_POS 24 363: #define AG903_SSPn_SPDIFStatus0_STUS3_MSK (0xffUL << AG903_SSPn_SPDIFStatus0_STUS3_POS) 364: 365: #define AG903_SSPn_SPDIFStatus1_STUS4_POS 0 366: #define AG903_SSPn_SPDIFStatus1_STUS4_MSK (0xffUL << AG903_SSPn_SPDIFStatus1_STUS4_POS) 367: 368: #define AG903_SSPn_SPDIFUser0_USER0_POS 0 369: #define AG903_SSPn_SPDIFUser0_USER0_MSK (0xffffffffUL << AG903_SSPn_SPDIFUser0_USER0_POS) 370: 371: #define AG903_SSPn_SPDIFUser1_USER1_POS 0 372: #define AG903_SSPn_SPDIFUser1_USER1_MSK (0xffffffffUL << AG903_SSPn_SPDIFUser1_USER1_POS) 373: 374: #define AG903_SSPn_SPDIFUser2_USER2_POS 0 375: #define AG903_SSPn_SPDIFUser2_USER2_MSK (0xffffffffUL << AG903_SSPn_SPDIFUser2_USER2_POS) 376: 377: #define AG903_SSPn_SPDIFUser3_USER3_POS 0 378: #define AG903_SSPn_SPDIFUser3_USER3_MSK (0xffffffffUL << AG903_SSPn_SPDIFUser3_USER3_POS) 379: 380: #define AG903_SSPn_SPDIFUser4_USER4_POS 0 381: #define AG903_SSPn_SPDIFUser4_USER4_MSK (0xffffffffUL << AG903_SSPn_SPDIFUser4_USER4_POS) 382: 383: #define AG903_SSPn_SPDIFUser5_USER5_POS 0 384: #define AG903_SSPn_SPDIFUser5_USER5_MSK (0xffffffffUL << AG903_SSPn_SPDIFUser5_USER5_POS) 385: 386: #define AG903_SSPn_SPDIFUser6_USER6_POS 0 387: #define AG903_SSPn_SPDIFUser6_USER6_MSK (0xffffffffUL << AG903_SSPn_SPDIFUser6_USER6_POS) 388: 389: #define AG903_SSPn_SPDIFUser7_USER7_POS 0 390: #define AG903_SSPn_SPDIFUser7_USER7_MSK (0xffffffffUL << AG903_SSPn_SPDIFUser7_USER7_POS) 391: 392: #define AG903_SSPn_SPDIFUser8_USER8_POS 0 393: #define AG903_SSPn_SPDIFUser8_USER8_MSK (0xffffffffUL << AG903_SSPn_SPDIFUser8_USER8_POS) 394: 395: #define AG903_SSPn_SPDIFUser9_USER9_POS 0 396: #define AG903_SSPn_SPDIFUser9_USER9_MSK (0xffffffffUL << AG903_SSPn_SPDIFUser9_USER9_POS) 397: 398: #define AG903_SSPn_SPDIFUser10_USER10_POS 0 399: #define AG903_SSPn_SPDIFUser10_USER10_MSK (0xffffffffUL << AG903_SSPn_SPDIFUser10_USER10_POS) 400: 401: #define AG903_SSPn_SPDIFUser11_USER11_POS 0 402: #define AG903_SSPn_SPDIFUser11_USER11_MSK (0xffffffffUL << AG903_SSPn_SPDIFUser11_USER11_POS) 403: 404: #define AG903_SSPn_SSPRevision_REL_REV_POS 0 405: #define AG903_SSPn_SSPRevision_REL_REV_MSK (0xffUL << AG903_SSPn_SSPRevision_REL_REV_POS) 406: #define AG903_SSPn_SSPRevision_MINOR_REV_POS 8 407: #define AG903_SSPn_SSPRevision_MINOR_REV_MSK (0xffUL << AG903_SSPn_SSPRevision_MINOR_REV_POS) 408: #define AG903_SSPn_SSPRevision_MAJOR_REV_POS 16 409: #define AG903_SSPn_SSPRevision_MAJOR_REV_MSK (0xffUL << AG903_SSPn_SSPRevision_MAJOR_REV_POS) 410: 411: #define AG903_SSPn_SSPFeature_FIFO_WIDTH_POS 0 412: #define AG903_SSPn_SSPFeature_FIFO_WIDTH_MSK (0xffUL << AG903_SSPn_SSPFeature_FIFO_WIDTH_POS) 413: #define AG903_SSPn_SSPFeature_RXFIFO_DEPTH_POS 8 414: #define AG903_SSPn_SSPFeature_RXFIFO_DEPTH_MSK (0xffUL << AG903_SSPn_SSPFeature_RXFIFO_DEPTH_POS) 415: #define AG903_SSPn_SSPFeature_TXFIFO_DEPTH_POS 16 416: #define AG903_SSPn_SSPFeature_TXFIFO_DEPTH_MSK (0xffUL << AG903_SSPn_SSPFeature_TXFIFO_DEPTH_POS) 417: #define AG903_SSPn_SSPFeature_I2S_FCFG_POS 25 418: #define AG903_SSPn_SSPFeature_I2S_FCFG_MSK (0x1UL << AG903_SSPn_SSPFeature_I2S_FCFG_POS) 419: #define AG903_SSPn_SSPFeature_SPIMWR_FCFG_POS 26 420: #define AG903_SSPn_SSPFeature_SPIMWR_FCFG_MSK (0x1UL << AG903_SSPn_SSPFeature_SPIMWR_FCFG_POS) 421: #define AG903_SSPn_SSPFeature_SSP_FCFG_POS 27 422: #define AG903_SSPn_SSPFeature_SSP_FCFG_MSK (0x1UL << AG903_SSPn_SSPFeature_SSP_FCFG_POS) 423: #define AG903_SSPn_SSPFeature_SPDIF_FCFG_POS 28 424: #define AG903_SSPn_SSPFeature_SPDIF_FCFG_MSK (0x1UL << AG903_SSPn_SSPFeature_SPDIF_FCFG_POS) 425: #define AG903_SSPn_SSPFeature_EXT_FSNUM_POS 29 426: #define AG903_SSPn_SSPFeature_EXT_FSNUM_MSK (0x3UL << AG903_SSPn_SSPFeature_EXT_FSNUM_POS) 427: 428: #endif 429:
名前 
説明 
SSPn Base Address 
SSPn Base Address 
SSPn Base Address 
SSPn Base Address 
SSPn Base Address (n=0..3) 
SSPnIntrCR Address (n=0..3) 
SSPnIntrCR RFDMAEN-bit mask 
SSPnIntrCR RFDMAEN-bit position 
SSPnIntrCR RFORIEN-bit mask 
SSPnIntrCR RFORIEN-bit position 
SSPnIntrCR RFTHIEN-bit mask 
SSPnIntrCR RFTHIEN-bit position 
SSPnIntrCR RFTHOD-bit mask 
SSPnIntrCR RFTHOD-bit position 
SSPnIntrCR TFDMAEN-bit mask 
SSPnIntrCR TFDMAEN-bit position 
SSPnIntrCR TFTHIEN-bit mask 
SSPnIntrCR TFTHIEN-bit position 
SSPnIntrCR TFTHOD-bit mask 
SSPnIntrCR TFTHOD-bit position 
SSPnIntrCR TFURIEN-bit mask 
SSPnIntrCR TFURIEN-bit position 
SSPnIntrStatus Address (n=0..3) 
SSPnIntrStatus RFORI-bit mask 
SSPnIntrStatus RFORI-bit position 
SSPnIntrStatus RFTHI-bit mask 
SSPnIntrStatus RFTHI-bit position 
SSPnIntrStatus TFTHI-bit mask 
SSPnIntrStatus TFTHI-bit position 
SSPnIntrStatus TFURI-bit mask 
SSPnIntrStatus TFURI-bit position 
SSPnSPDIFStatus0 Address (n=0..3) 
SSPnSPDIFStatus0 STUS0-bit mask 
SSPnSPDIFStatus0 STUS0-bit position 
SSPnSPDIFStatus0 STUS1-bit mask 
SSPnSPDIFStatus0 STUS1-bit position 
SSPnSPDIFStatus0 STUS2-bit mask 
SSPnSPDIFStatus0 STUS2-bit position 
SSPnSPDIFStatus0 STUS3-bit mask 
SSPnSPDIFStatus0 STUS3-bit position 
SSPnSPDIFStatus1 Address (n=0..3) 
SSPnSPDIFStatus1 STUS4-bit mask 
SSPnSPDIFStatus1 STUS4-bit position 
SSPnSPDIFUser0 Address (n=0..3) 
SSPnSPDIFUser0 USER0-bit mask 
SSPnSPDIFUser0 USER0-bit position 
SSPnSPDIFUser1 Address (n=0..3) 
SSPnSPDIFUser1 USER1-bit mask 
SSPnSPDIFUser1 USER1-bit position 
SSPnSPDIFUser10 Address (n=0..3) 
SSPnSPDIFUser10 USER10-bit mask 
SSPnSPDIFUser10 USER10-bit position 
SSPnSPDIFUser11 Address (n=0..3) 
SSPnSPDIFUser11 USER11-bit mask 
SSPnSPDIFUser11 USER11-bit position 
SSPnSPDIFUser2 Address (n=0..3) 
SSPnSPDIFUser2 USER2-bit mask 
SSPnSPDIFUser2 USER2-bit position 
SSPnSPDIFUser3 Address (n=0..3) 
SSPnSPDIFUser3 USER3-bit mask 
SSPnSPDIFUser3 USER3-bit position 
SSPnSPDIFUser4 Address (n=0..3) 
SSPnSPDIFUser4 USER4-bit mask 
SSPnSPDIFUser4 USER4-bit position 
SSPnSPDIFUser5 Address (n=0..3) 
SSPnSPDIFUser5 USER5-bit mask 
SSPnSPDIFUser5 USER5-bit position 
SSPnSPDIFUser6 Address (n=0..3) 
SSPnSPDIFUser6 USER6-bit mask 
SSPnSPDIFUser6 USER6-bit position 
SSPnSPDIFUser7 Address (n=0..3) 
SSPnSPDIFUser7 USER7-bit mask 
SSPnSPDIFUser7 USER7-bit position 
SSPnSPDIFUser8 Address (n=0..3) 
SSPnSPDIFUser8 USER8-bit mask 
SSPnSPDIFUser8 USER8-bit position 
SSPnSPDIFUser9 Address (n=0..3) 
SSPnSPDIFUser9 USER9-bit mask 
SSPnSPDIFUser9 USER9-bit position 
SSPnSSPCR0 Address (n=0..3) 
SSPnSSPCR0 FFMT-bit mask 
SSPnSSPCR0 FFMT-bit position 
SSPnSSPCR0 FLASH-bit mask 
SSPnSSPCR0 FLASH-bit position 
SSPnSSPCR0 FSDIST-bit mask 
SSPnSSPCR0 FSDIST-bit position 
SSPnSSPCR0 FSFDBK-bit mask 
SSPnSSPCR0 FSFDBK-bit position 
SSPnSSPCR0 FSJSTFY-bit mask 
SSPnSSPCR0 FSJSTFY-bit position 
SSPnSSPCR0 FSPO-bit mask 
SSPnSSPCR0 FSPO-bit position 
SSPnSSPCR0 LBM-bit mask 
SSPnSSPCR0 LBM-bit position 
SSPnSSPCR0 LSB-bit mask 
SSPnSSPCR0 LSB-bit position 
SSPnSSPCR0 OPM-bit mask 
SSPnSSPCR0 OPM-bit position 
SSPnSSPCR0 SCLKFDBK-bit mask 
SSPnSSPCR0 SCLKFDBK-bit position 
SSPnSSPCR0 SCLKPH-bit mask 
SSPnSSPCR0 SCLKPH-bit position 
SSPnSSPCR0 SCLKPO-bit mask 
SSPnSSPCR0 SCLKPO-bit position 
SSPnSSPCR0 SPIFSPO-bit mask 
SSPnSSPCR0 SPIFSPO-bit position 
SSPnSSPCR0 Validity-bit mask 
SSPnSSPCR0 Validity-bit position 
SSPnSSPCR1 Address (n=0..3) 
SSPnSSPCR1 PDL-bit mask 
SSPnSSPCR1 PDL-bit position 
SSPnSSPCR1 SCLKDIV-bit mask 
SSPnSSPCR1 SCLKDIV-bit position 
SSPnSSPCR1 SDL-bit mask 
SSPnSSPCR1 SDL-bit position 
SSPnSSPCR2 Address (n=0..3) 
SSPnSSPCR2 FS-bit mask 
SSPnSSPCR2 FS-bit position 
SSPnSSPCR2 FSOS-bit mask 
SSPnSSPCR2 FSOS-bit position 
SSPnSSPCR2 RXEN-bit mask 
SSPnSSPCR2 RXEN-bit position 
SSPnSSPCR2 RXFCLR-bit mask 
SSPnSSPCR2 RXFCLR-bit position 
SSPnSSPCR2 SSPEN-bit mask 
SSPnSSPCR2 SSPEN-bit position 
SSPnSSPCR2 SSPRST-bit mask 
SSPnSSPCR2 SSPRST-bit position 
SSPnSSPCR2 TXDOE-bit mask 
SSPnSSPCR2 TXDOE-bit position 
SSPnSSPCR2 TXEN-bit mask 
SSPnSSPCR2 TXEN-bit position 
SSPnSSPCR2 TXFCLR-bit mask 
SSPnSSPCR2 TXFCLR-bit position 
SSPnSSPFeature Address (n=0..3) 
SSPnSSPFeature EXT_FSNUM-bit mask 
SSPnSSPFeature EXT_FSNUM-bit position 
SSPnSSPFeature FIFO_WIDTH-bit mask 
SSPnSSPFeature FIFO_WIDTH-bit position 
SSPnSSPFeature I2S_FCFG-bit mask 
SSPnSSPFeature I2S_FCFG-bit position 
SSPnSSPFeature RXFIFO_DEPTH-bit mask 
SSPnSSPFeature RXFIFO_DEPTH-bit position 
SSPnSSPFeature SPDIF_FCFG-bit mask 
SSPnSSPFeature SPDIF_FCFG-bit position 
SSPnSSPFeature SPIMWR_FCFG-bit mask 
SSPnSSPFeature SPIMWR_FCFG-bit position 
SSPnSSPFeature SSP_FCFG-bit mask 
SSPnSSPFeature SSP_FCFG-bit position 
SSPnSSPFeature TXFIFO_DEPTH-bit mask 
SSPnSSPFeature TXFIFO_DEPTH-bit position 
SSPnSSPRevision Address (n=0..3) 
SSPnSSPRevision MAJOR_REV-bit mask 
SSPnSSPRevision MAJOR_REV-bit position 
SSPnSSPRevision MINOR_REV-bit mask 
SSPnSSPRevision MINOR_REV-bit position 
SSPnSSPRevision REL_REV-bit mask 
SSPnSSPRevision REL_REV-bit position 
SSPnSSPStatus Address (n=0..3) 
SSPnSSPStatus BUSY-bit mask 
SSPnSSPStatus BUSY-bit position 
SSPnSSPStatus RFF-bit mask 
SSPnSSPStatus RFF-bit position 
SSPnSSPStatus RFVE-bit mask 
SSPnSSPStatus RFVE-bit position 
SSPnSSPStatus TFNF-bit mask 
SSPnSSPStatus TFNF-bit position 
SSPnSSPStatus TFVE-bit mask 
SSPnSSPStatus TFVE-bit position 
SSPnTxRxDR Address (n=0..3) 
SSPnTxRxDR DATA-bit mask 
SSPnTxRxDR DATA-bit position 
名前 
説明 
SSPn Type 
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