AG903ライブラリリファレンス
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AG903_dmacreg.h
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1: 8: 9: 13: 14:
#ifndef
_AG903_DMAC_REGMAP_H_ 15:
#define
_AG903_DMAC_REGMAP_H_ 16: 17: 18:
#include
"AG903_regmap.h" 19: 20:
#ifndef
__I
21: 22:
#define
__I
volatile
const
23:
#endif
24:
#ifndef
__O
25: 26:
#define
__O
volatile
27:
#endif
28:
#ifndef
__IO
29: 30:
#define
__IO
volatile
31:
#endif
32: 33: 34:
typedef
struct
{ 35: 36:
union
{ 37:
__I
uint32_t
INT
; 38: 39:
struct
{ 40:
__I
uint32_t Intr : 8; 41: } INT_bits; 42: }; 43: 44:
union
{ 45:
__I
uint32_t TIMECOUNT_INT; 46: 47:
struct
{ 48:
__I
uint32_t TCIntr : 8; 49: } TIMECOUNT_INT_bits; 50: }; 51: 52:
union
{ 53:
__O
uint32_t TIMECOUNT_INT_CLEAR; 54: 55:
struct
{ 56:
__O
uint32_t TCIntrClr : 8; 57: } TIMECOUNT_INT_CLEAR_bits; 58: }; 59: 60:
union
{ 61:
__I
uint32_t ERR_ABORT_INT; 62: 63:
struct
{ 64:
__I
uint32_t ErrIntr : 8; 65:
__I
uint32_t WdtIntr : 8; 66:
__I
uint32_t AbtIntr : 8; 67: } ERR_ABORT_INT_bits; 68: }; 69: 70:
union
{ 71:
__O
uint32_t ERR_ABORT_INT_CLEAR; 72: 73:
struct
{ 74:
__O
uint32_t ErrIntrClr : 8; 75:
__O
uint32_t WdtIntrClr : 8; 76:
__O
uint32_t AbtIntrClr : 8; 77: } ERR_ABORT_INT_CLEAR_bits; 78: }; 79: 80:
union
{ 81:
__I
uint32_t TIMECOUNT_STATUS; 82: 83:
struct
{ 84:
__I
uint32_t TCStatus : 8; 85: } TIMECOUNT_STATUS_bits; 86: }; 87: 88:
union
{ 89:
__I
uint32_t ERR_ABORT_STATUS; 90: 91:
struct
{ 92:
__I
uint32_t ErrStatus : 8; 93:
__I
uint32_t WdtStatus : 8; 94:
__I
uint32_t AbtStatus : 8; 95: } ERR_ABORT_STATUS_bits; 96: }; 97: 98:
union
{ 99:
__IO
uint32_t CHANNEL_ENABLE; 100: 101:
struct
{ 102:
__IO
uint32_t ChEnable : 8; 103: } CHANNEL_ENABLE_bits; 104: }; 105: 106:
union
{ 107:
__IO
uint32_t SYNC_PERI_IF; 108: 109:
struct
{ 110:
__IO
uint32_t SyncDmaReq : 16; 111: } SYNC_PERI_IF_bits; 112: }; 113: 114:
union
{ 115:
__IO
uint32_t LOCAL_DESC_MEM_BASE; 116: 117:
struct
{ 118: uint32_t : 20; 119:
__IO
uint32_t LDMBase : 12; 120: } LOCAL_DESC_MEM_BASE_bits; 121: }; 122: 123:
union
{ 124:
__IO
uint32_t WATCHDOG_TIMER; 125: 126:
struct
{ 127:
__IO
uint32_t WDTimer : 16; 128: } WATCHDOG_TIMER_bits; 129: }; 130: 131:
union
{ 132:
__IO
uint32_t GLOBAL_EVENT; 133: 134:
struct
{ 135:
__I
uint32_t GlbEvent : 8; 136:
__O
uint32_t GlbEventSet : 8; 137:
__O
uint32_t GlbEventClr : 8; 138: } GLOBAL_EVENT_bits; 139: }; 140: 141:
union
{ 142:
__IO
uint32_t PSLVERR_ENABLE; 143: 144:
struct
{ 145:
__IO
uint32_t PSlvErrEn : 1; 146: } PSLVERR_ENABLE_bits; 147: }; 148: 149:
union
{ 150:
__I
uint32_t REVISION_NUMBER; 151: }; 152: 153:
union
{ 154:
__I
uint32_t HW_FEATURE; 155: 156:
struct
{ 157:
__I
uint32_t ChNum : 3; 158:
__I
uint32_t UnalignMode : 1; 159:
__I
uint32_t DWidth : 2; 160:
__I
uint32_t SLVDWidth : 2; 161:
__I
uint32_t DFDepth : 3; 162: uint32_t : 1; 163:
__I
uint32_t PriOn : 1; 164: uint32_t : 3; 165:
__I
uint32_t PriNum : 4; 166:
__I
uint32_t LdmOn : 1; 167: uint32_t : 3; 168:
__I
uint32_t LdmDepth : 2; 169: uint32_t : 2; 170:
__I
uint32_t CmdDepth : 2; 171: } HW_FEATURE_bits; 172: }; 173: 174:
union
{ 175:
__IO
uint32_t LOCAL_DESC_MEM_FREE_FLAG_SET_0; 176: }; 177: 178:
union
{ 179:
__IO
uint32_t LOCAL_DESC_MEM_FREE_FLAG_SET_1; 180: }; 181: 182:
union
{ 183:
__IO
uint32_t LOCAL_DESC_MEM_FREE_FLAG_SET_2; 184: }; 185: 186:
union
{ 187:
__IO
uint32_t LOCAL_DESC_MEM_FREE_FLAG_SET_3; 188: }; 189: 190:
union
{ 191:
__IO
uint32_t ENDIAN_CONVERSION; 192: 193:
struct
{ 194:
__IO
uint32_t EndianConvert : 8; 195: uint32_t : 8; 196:
__IO
uint32_t LMEC : 1; 197: } ENDIAN_CONVERSION_bits; 198: }; 199: 200:
union
{ 201:
__IO
uint32_t CONSTANT_VALUE_WRITE_ONLY; 202: }; 203: 204: 205: }
AG903_DMAC_Type
; 206: 207: 208:
typedef
struct
{ 209: 210:
union
{ 211:
__IO
uint32_t CTRL_REG; 212: 213:
struct
{ 214:
__IO
uint32_t ChWEvent : 8; 215:
__IO
uint32_t WSync : 1; 216:
__IO
uint32_t ChSEvent : 3; 217:
__IO
uint32_t SEventEn : 1; 218:
__IO
uint32_t WEventEn : 1; 219:
__IO
uint32_t DEn : 1; 220:
__IO
uint32_t ExpEn : 1; 221:
__IO
uint32_t ChEn : 1; 222:
__IO
uint32_t WDTEn : 1; 223:
__IO
uint32_t DstCtrl : 2; 224:
__IO
uint32_t SrcCtrl : 2; 225:
__IO
uint32_t DstWidth : 3; 226:
__IO
uint32_t SrcWidth : 3; 227:
__IO
uint32_t TCMsk : 1; 228:
__IO
uint32_t SrcTcnt : 3; 229: } CTRL_REG_bits; 230: }; 231: 232:
union
{ 233:
__IO
uint32_t CFG_REG; 234: 235:
struct
{ 236:
__IO
uint32_t TCIntMsk : 1; 237:
__IO
uint32_t ErrIntMsk : 1; 238:
__IO
uint32_t AbtIntMsk : 1; 239:
__IO
uint32_t SrcRS : 4; 240:
__IO
uint32_t SrcHEn : 1; 241: uint32_t : 1; 242:
__IO
uint32_t DstRS : 4; 243:
__IO
uint32_t DstHEn : 1; 244: uint32_t : 2; 245:
__I
uint32_t LLPCnt : 4; 246:
__IO
uint32_t ChGntWin : 8; 247:
__IO
uint32_t ChPri : 1; 248: uint32_t : 1; 249:
__IO
uint32_t WOMode : 1; 250:
__IO
uint32_t UnalignMode : 1; 251: } CFG_REG_bits; 252: }; 253: 254:
union
{ 255:
__IO
uint32_t SRC_ADDR; 256: }; 257: 258:
union
{ 259:
__IO
uint32_t DST_ADDR; 260: }; 261: 262:
union
{ 263:
__IO
uint32_t LINK_LIST_POINTER; 264: }; 265: 266:
union
{ 267:
__IO
uint32_t TRNS_SIZE_1D; 268: 269:
struct
{ 270:
__IO
uint32_t TCnt : 22; 271: } TRNS_SIZE_1D_bits; 272: 273:
__IO
uint32_t TRNS_SIZE_2D; 274: 275:
struct
{ 276:
__IO
uint32_t XTCnt : 16; 277:
__IO
uint32_t YTCnt : 16; 278: } TRNS_SIZE_2D_bits; 279: }; 280: 281:
union
{ 282:
__IO
uint32_t STRIDE_SRC_DST_ADDR; 283: 284:
struct
{ 285:
__IO
uint32_t SrcStride : 16; 286:
__IO
uint32_t DstStride : 16; 287: } STRIDE_SRC_DST_ADDR_bits; 288: }; 289: 290: 291: }
AG903_DMACn_Type
; 292: 293:
#define
AG903_DMACn
(ch) ((
volatile
AG903_DMACn_Type
*)(
AG903_DMAC0_BASE
+ 0x20 * ch)) 294:
#define
AG903_DMACn_CTRL_REG
(ch)
AG903_DMACn
(ch)->CTRL_REG 295:
#define
AG903_DMACn_CFG_REG
(ch)
AG903_DMACn
(ch)->CFG_REG 296:
#define
AG903_DMACn_SRC_ADDR
(ch)
AG903_DMACn
(ch)->SRC_ADDR 297:
#define
AG903_DMACn_DST_ADDR
(ch)
AG903_DMACn
(ch)->DST_ADDR 298:
#define
AG903_DMACn_LINK_LIST_POINTER
(ch)
AG903_DMACn
(ch)->LINK_LIST_POINTER 299:
#define
AG903_DMACn_TRNS_SIZE_1D
(ch)
AG903_DMACn
(ch)->TRNS_SIZE_1D 300:
#define
AG903_DMACn_TRNS_SIZE_2D
(ch)
AG903_DMACn
(ch)->TRNS_SIZE_2D 301:
#define
AG903_DMACn_STRIDE_SRC_DST_ADDR
(ch)
AG903_DMACn
(ch)->STRIDE_SRC_DST_ADDR 302: 303:
#define
AG903_DMAC
((
volatile
AG903_DMAC_Type
*)
AG903_DMAC_BASE
) 304:
#define
AG903_DMAC0
((
volatile
AG903_DMACn_Type
*)
AG903_DMAC0_BASE
) 305:
#define
AG903_DMAC1
((
volatile
AG903_DMACn_Type
*)
AG903_DMAC1_BASE
) 306:
#define
AG903_DMAC2
((
volatile
AG903_DMACn_Type
*)
AG903_DMAC2_BASE
) 307:
#define
AG903_DMAC3
((
volatile
AG903_DMACn_Type
*)
AG903_DMAC3_BASE
) 308:
#define
AG903_DMAC4
((
volatile
AG903_DMACn_Type
*)
AG903_DMAC4_BASE
) 309:
#define
AG903_DMAC5
((
volatile
AG903_DMACn_Type
*)
AG903_DMAC5_BASE
) 310:
#define
AG903_DMAC6
((
volatile
AG903_DMACn_Type
*)
AG903_DMAC6_BASE
) 311:
#define
AG903_DMAC7
((
volatile
AG903_DMACn_Type
*)
AG903_DMAC7_BASE
) 312: 313: 314:
#define
AG903_DMAC_INT_Intr_POS
0 315:
#define
AG903_DMAC_INT_Intr_MSK
(0xffUL <<
AG903_DMAC_INT_Intr_POS
) 316: 317:
#define
AG903_DMAC_TIMECOUNT_INT_TCIntr_POS
0 318:
#define
AG903_DMAC_TIMECOUNT_INT_TCIntr_MSK
(0xffUL <<
AG903_DMAC_TIMECOUNT_INT_TCIntr_POS
) 319: 320:
#define
AG903_DMAC_TIMECOUNT_INT_CLEAR_TCIntrClr_POS
0 321:
#define
AG903_DMAC_TIMECOUNT_INT_CLEAR_TCIntrClr_MSK
(0xffUL <<
AG903_DMAC_TIMECOUNT_INT_CLEAR_TCIntrClr_POS
) 322: 323:
#define
AG903_DMAC_ERR_ABORT_INT_ErrIntr_POS
0 324:
#define
AG903_DMAC_ERR_ABORT_INT_ErrIntr_MSK
(0xffUL <<
AG903_DMAC_ERR_ABORT_INT_ErrIntr_POS
) 325:
#define
AG903_DMAC_ERR_ABORT_INT_WdtIntr_POS
8 326:
#define
AG903_DMAC_ERR_ABORT_INT_WdtIntr_MSK
(0xffUL <<
AG903_DMAC_ERR_ABORT_INT_WdtIntr_POS
) 327:
#define
AG903_DMAC_ERR_ABORT_INT_AbtIntr_POS
16 328:
#define
AG903_DMAC_ERR_ABORT_INT_AbtIntr_MSK
(0xffUL <<
AG903_DMAC_ERR_ABORT_INT_AbtIntr_POS
) 329: 330:
#define
AG903_DMAC_ERR_ABORT_INT_CLEAR_ErrIntrClr_POS
0 331:
#define
AG903_DMAC_ERR_ABORT_INT_CLEAR_ErrIntrClr_MSK
(0xffUL <<
AG903_DMAC_ERR_ABORT_INT_CLEAR_ErrIntrClr_POS
) 332:
#define
AG903_DMAC_ERR_ABORT_INT_CLEAR_WdtIntrClr_POS
8 333:
#define
AG903_DMAC_ERR_ABORT_INT_CLEAR_WdtIntrClr_MSK
(0xffUL <<
AG903_DMAC_ERR_ABORT_INT_CLEAR_WdtIntrClr_POS
) 334:
#define
AG903_DMAC_ERR_ABORT_INT_CLEAR_AbtIntrClr_POS
16 335:
#define
AG903_DMAC_ERR_ABORT_INT_CLEAR_AbtIntrClr_MSK
(0xffUL <<
AG903_DMAC_ERR_ABORT_INT_CLEAR_AbtIntrClr_POS
) 336: 337:
#define
AG903_DMAC_TIMECOUNT_STATUS_TCStatus_POS
0 338:
#define
AG903_DMAC_TIMECOUNT_STATUS_TCStatus_MSK
(0xffUL <<
AG903_DMAC_TIMECOUNT_STATUS_TCStatus_POS
) 339: 340:
#define
AG903_DMAC_ERR_ABORT_STATUS_ErrStatus_POS
0 341:
#define
AG903_DMAC_ERR_ABORT_STATUS_ErrStatus_MSK
(0xffUL <<
AG903_DMAC_ERR_ABORT_STATUS_ErrStatus_POS
) 342:
#define
AG903_DMAC_ERR_ABORT_STATUS_WdtStatus_POS
8 343:
#define
AG903_DMAC_ERR_ABORT_STATUS_WdtStatus_MSK
(0xffUL <<
AG903_DMAC_ERR_ABORT_STATUS_WdtStatus_POS
) 344:
#define
AG903_DMAC_ERR_ABORT_STATUS_AbtStatus_POS
16 345:
#define
AG903_DMAC_ERR_ABORT_STATUS_AbtStatus_MSK
(0xffUL <<
AG903_DMAC_ERR_ABORT_STATUS_AbtStatus_POS
) 346: 347:
#define
AG903_DMAC_CHANNEL_ENABLE_ChEnable_POS
0 348:
#define
AG903_DMAC_CHANNEL_ENABLE_ChEnable_MSK
(0xffUL <<
AG903_DMAC_CHANNEL_ENABLE_ChEnable_POS
) 349: 350:
#define
AG903_DMAC_SYNC_PERI_IF_SyncDmaReq_POS
0 351:
#define
AG903_DMAC_SYNC_PERI_IF_SyncDmaReq_MSK
(0xffffUL <<
AG903_DMAC_SYNC_PERI_IF_SyncDmaReq_POS
) 352: 353:
#define
AG903_DMAC_LOCAL_DESC_MEM_BASE_LDMBase_POS
20 354:
#define
AG903_DMAC_LOCAL_DESC_MEM_BASE_LDMBase_MSK
(0xfffUL <<
AG903_DMAC_LOCAL_DESC_MEM_BASE_LDMBase_POS
) 355: 356:
#define
AG903_DMAC_WATCHDOG_TIMER_WDTimer_POS
0 357:
#define
AG903_DMAC_WATCHDOG_TIMER_WDTimer_MSK
(0xffffUL <<
AG903_DMAC_WATCHDOG_TIMER_WDTimer_POS
) 358: 359:
#define
AG903_DMAC_GLOBAL_EVENT_GlbEvent_POS
0 360:
#define
AG903_DMAC_GLOBAL_EVENT_GlbEvent_MSK
(0xffUL <<
AG903_DMAC_GLOBAL_EVENT_GlbEvent_POS
) 361:
#define
AG903_DMAC_GLOBAL_EVENT_GlbEventSet_POS
8 362:
#define
AG903_DMAC_GLOBAL_EVENT_GlbEventSet_MSK
(0xffUL <<
AG903_DMAC_GLOBAL_EVENT_GlbEventSet_POS
) 363:
#define
AG903_DMAC_GLOBAL_EVENT_GlbEventClr_POS
16 364:
#define
AG903_DMAC_GLOBAL_EVENT_GlbEventClr_MSK
(0xffUL <<
AG903_DMAC_GLOBAL_EVENT_GlbEventClr_POS
) 365: 366:
#define
AG903_DMAC_PSLVERR_ENABLE_PSlvErrEn_POS
0 367:
#define
AG903_DMAC_PSLVERR_ENABLE_PSlvErrEn_MSK
(0x1UL <<
AG903_DMAC_PSLVERR_ENABLE_PSlvErrEn_POS
) 368: 369:
#define
AG903_DMAC_REVISION_NUMBER_RevNum_POS
0 370:
#define
AG903_DMAC_REVISION_NUMBER_RevNum_MSK
(0xffffffffUL <<
AG903_DMAC_REVISION_NUMBER_RevNum_POS
) 371: 372:
#define
AG903_DMAC_HW_FEATURE_ChNum_POS
0 373:
#define
AG903_DMAC_HW_FEATURE_ChNum_MSK
(0x7UL <<
AG903_DMAC_HW_FEATURE_ChNum_POS
) 374:
#define
AG903_DMAC_HW_FEATURE_UnalignMode_POS
3 375:
#define
AG903_DMAC_HW_FEATURE_UnalignMode_MSK
(0x1UL <<
AG903_DMAC_HW_FEATURE_UnalignMode_POS
) 376:
#define
AG903_DMAC_HW_FEATURE_DWidth_POS
4 377:
#define
AG903_DMAC_HW_FEATURE_DWidth_MSK
(0x3UL <<
AG903_DMAC_HW_FEATURE_DWidth_POS
) 378:
#define
AG903_DMAC_HW_FEATURE_SLVDWidth_POS
6 379:
#define
AG903_DMAC_HW_FEATURE_SLVDWidth_MSK
(0x3UL <<
AG903_DMAC_HW_FEATURE_SLVDWidth_POS
) 380:
#define
AG903_DMAC_HW_FEATURE_DFDepth_POS
8 381:
#define
AG903_DMAC_HW_FEATURE_DFDepth_MSK
(0x7UL <<
AG903_DMAC_HW_FEATURE_DFDepth_POS
) 382:
#define
AG903_DMAC_HW_FEATURE_PriOn_POS
12 383:
#define
AG903_DMAC_HW_FEATURE_PriOn_MSK
(0x1UL <<
AG903_DMAC_HW_FEATURE_PriOn_POS
) 384:
#define
AG903_DMAC_HW_FEATURE_PriNum_POS
16 385:
#define
AG903_DMAC_HW_FEATURE_PriNum_MSK
(0xfUL <<
AG903_DMAC_HW_FEATURE_PriNum_POS
) 386:
#define
AG903_DMAC_HW_FEATURE_LdmOn_POS
20 387:
#define
AG903_DMAC_HW_FEATURE_LdmOn_MSK
(0x1UL <<
AG903_DMAC_HW_FEATURE_LdmOn_POS
) 388:
#define
AG903_DMAC_HW_FEATURE_LdmDepth_POS
24 389:
#define
AG903_DMAC_HW_FEATURE_LdmDepth_MSK
(0x3UL <<
AG903_DMAC_HW_FEATURE_LdmDepth_POS
) 390:
#define
AG903_DMAC_HW_FEATURE_CmdDepth_POS
28 391:
#define
AG903_DMAC_HW_FEATURE_CmdDepth_MSK
(0x3UL <<
AG903_DMAC_HW_FEATURE_CmdDepth_POS
) 392: 393:
#define
AG903_DMAC_LOCAL_DESC_MEM_FREE_FLAG_SET_0_FreeFlagS0_POS
0 394:
#define
AG903_DMAC_LOCAL_DESC_MEM_FREE_FLAG_SET_0_FreeFlagS0_MSK
(0xffffffffUL <<
AG903_DMAC_LOCAL_DESC_MEM_FREE_FLAG_SET_0_FreeFlagS0_POS
) 395: 396:
#define
AG903_DMAC_LOCAL_DESC_MEM_FREE_FLAG_SET_1_FreeFlagS1_POS
0 397:
#define
AG903_DMAC_LOCAL_DESC_MEM_FREE_FLAG_SET_1_FreeFlagS1_MSK
(0xffffffffUL <<
AG903_DMAC_LOCAL_DESC_MEM_FREE_FLAG_SET_1_FreeFlagS1_POS
) 398: 399:
#define
AG903_DMAC_LOCAL_DESC_MEM_FREE_FLAG_SET_2_FreeFlagS2_POS
0 400:
#define
AG903_DMAC_LOCAL_DESC_MEM_FREE_FLAG_SET_2_FreeFlagS2_MSK
(0xffffffffUL <<
AG903_DMAC_LOCAL_DESC_MEM_FREE_FLAG_SET_2_FreeFlagS2_POS
) 401: 402:
#define
AG903_DMAC_LOCAL_DESC_MEM_FREE_FLAG_SET_3_FreeFlagS3_POS
0 403:
#define
AG903_DMAC_LOCAL_DESC_MEM_FREE_FLAG_SET_3_FreeFlagS3_MSK
(0xffffffffUL <<
AG903_DMAC_LOCAL_DESC_MEM_FREE_FLAG_SET_3_FreeFlagS3_POS
) 404: 405:
#define
AG903_DMAC_ENDIAN_CONVERSION_EndianConvert_POS
0 406:
#define
AG903_DMAC_ENDIAN_CONVERSION_EndianConvert_MSK
(0xffUL <<
AG903_DMAC_ENDIAN_CONVERSION_EndianConvert_POS
) 407:
#define
AG903_DMAC_ENDIAN_CONVERSION_LMEC_POS
16 408:
#define
AG903_DMAC_ENDIAN_CONVERSION_LMEC_MSK
(0x1UL <<
AG903_DMAC_ENDIAN_CONVERSION_LMEC_POS
) 409: 410:
#define
AG903_DMAC_CONSTANT_VALUE_WRITE_ONLY_WOValue_POS
0 411:
#define
AG903_DMAC_CONSTANT_VALUE_WRITE_ONLY_WOValue_MSK
(0xffffffffUL <<
AG903_DMAC_CONSTANT_VALUE_WRITE_ONLY_WOValue_POS
) 412: 413:
#define
AG903_DMACn_CTRL_REG_ChWEvent_POS
0 414:
#define
AG903_DMACn_CTRL_REG_ChWEvent_MSK
(0xffUL <<
AG903_DMACn_CTRL_REG_ChWEvent_POS
) 415:
#define
AG903_DMACn_CTRL_REG_WSync_POS
8 416:
#define
AG903_DMACn_CTRL_REG_WSync_MSK
(0x1UL <<
AG903_DMACn_CTRL_REG_WSync_POS
) 417:
#define
AG903_DMACn_CTRL_REG_ChSEvent_POS
9 418:
#define
AG903_DMACn_CTRL_REG_ChSEvent_MSK
(0x7UL <<
AG903_DMACn_CTRL_REG_ChSEvent_POS
) 419:
#define
AG903_DMACn_CTRL_REG_SEventEn_POS
12 420:
#define
AG903_DMACn_CTRL_REG_SEventEn_MSK
(0x1UL <<
AG903_DMACn_CTRL_REG_SEventEn_POS
) 421:
#define
AG903_DMACn_CTRL_REG_WEventEn_POS
13 422:
#define
AG903_DMACn_CTRL_REG_WEventEn_MSK
(0x1UL <<
AG903_DMACn_CTRL_REG_WEventEn_POS
) 423:
#define
AG903_DMACn_CTRL_REG_DEn_POS
14 424:
#define
AG903_DMACn_CTRL_REG_DEn_MSK
(0x1UL <<
AG903_DMACn_CTRL_REG_DEn_POS
) 425:
#define
AG903_DMACn_CTRL_REG_ExpEn_POS
15 426:
#define
AG903_DMACn_CTRL_REG_ExpEn_MSK
(0x1UL <<
AG903_DMACn_CTRL_REG_ExpEn_POS
) 427:
#define
AG903_DMACn_CTRL_REG_ChEn_POS
16 428:
#define
AG903_DMACn_CTRL_REG_ChEn_MSK
(0x1UL <<
AG903_DMACn_CTRL_REG_ChEn_POS
) 429:
#define
AG903_DMACn_CTRL_REG_WDTEn_POS
17 430:
#define
AG903_DMACn_CTRL_REG_WDTEn_MSK
(0x1UL <<
AG903_DMACn_CTRL_REG_WDTEn_POS
) 431:
#define
AG903_DMACn_CTRL_REG_DstCtrl_POS
18 432:
#define
AG903_DMACn_CTRL_REG_DstCtrl_MSK
(0x3UL <<
AG903_DMACn_CTRL_REG_DstCtrl_POS
) 433:
#define
AG903_DMACn_CTRL_REG_SrcCtrl_POS
20 434:
#define
AG903_DMACn_CTRL_REG_SrcCtrl_MSK
(0x3UL <<
AG903_DMACn_CTRL_REG_SrcCtrl_POS
) 435:
#define
AG903_DMACn_CTRL_REG_DstWidth_POS
22 436:
#define
AG903_DMACn_CTRL_REG_DstWidth_MSK
(0x7UL <<
AG903_DMACn_CTRL_REG_DstWidth_POS
) 437:
#define
AG903_DMACn_CTRL_REG_SrcWidth_POS
25 438:
#define
AG903_DMACn_CTRL_REG_SrcWidth_MSK
(0x7UL <<
AG903_DMACn_CTRL_REG_SrcWidth_POS
) 439:
#define
AG903_DMACn_CTRL_REG_TCMsk_POS
28 440:
#define
AG903_DMACn_CTRL_REG_TCMsk_MSK
(0x1UL <<
AG903_DMACn_CTRL_REG_TCMsk_POS
) 441:
#define
AG903_DMACn_CTRL_REG_SrcTcnt_POS
29 442:
#define
AG903_DMACn_CTRL_REG_SrcTcnt_MSK
(0x7UL <<
AG903_DMACn_CTRL_REG_SrcTcnt_POS
) 443: 444:
#define
AG903_DMACn_CFG_REG_TCIntMsk_POS
0 445:
#define
AG903_DMACn_CFG_REG_TCIntMsk_MSK
(0x1UL <<
AG903_DMACn_CFG_REG_TCIntMsk_POS
) 446:
#define
AG903_DMACn_CFG_REG_ErrIntMsk_POS
1 447:
#define
AG903_DMACn_CFG_REG_ErrIntMsk_MSK
(0x1UL <<
AG903_DMACn_CFG_REG_ErrIntMsk_POS
) 448:
#define
AG903_DMACn_CFG_REG_AbtIntMsk_POS
2 449:
#define
AG903_DMACn_CFG_REG_AbtIntMsk_MSK
(0x1UL <<
AG903_DMACn_CFG_REG_AbtIntMsk_POS
) 450:
#define
AG903_DMACn_CFG_REG_SrcRS_POS
3 451:
#define
AG903_DMACn_CFG_REG_SrcRS_MSK
(0xfUL <<
AG903_DMACn_CFG_REG_SrcRS_POS
) 452:
#define
AG903_DMACn_CFG_REG_SrcHEn_POS
7 453:
#define
AG903_DMACn_CFG_REG_SrcHEn_MSK
(0x1UL <<
AG903_DMACn_CFG_REG_SrcHEn_POS
) 454:
#define
AG903_DMACn_CFG_REG_DstRS_POS
9 455:
#define
AG903_DMACn_CFG_REG_DstRS_MSK
(0xfUL <<
AG903_DMACn_CFG_REG_DstRS_POS
) 456:
#define
AG903_DMACn_CFG_REG_DstHEn_POS
13 457:
#define
AG903_DMACn_CFG_REG_DstHEn_MSK
(0x1UL <<
AG903_DMACn_CFG_REG_DstHEn_POS
) 458:
#define
AG903_DMACn_CFG_REG_LLPCnt_POS
16 459:
#define
AG903_DMACn_CFG_REG_LLPCnt_MSK
(0xfUL <<
AG903_DMACn_CFG_REG_LLPCnt_POS
) 460:
#define
AG903_DMACn_CFG_REG_ChGntWin_POS
20 461:
#define
AG903_DMACn_CFG_REG_ChGntWin_MSK
(0xffUL <<
AG903_DMACn_CFG_REG_ChGntWin_POS
) 462:
#define
AG903_DMACn_CFG_REG_ChPri_POS
28 463:
#define
AG903_DMACn_CFG_REG_ChPri_MSK
(0x1UL <<
AG903_DMACn_CFG_REG_ChPri_POS
) 464:
#define
AG903_DMACn_CFG_REG_WOMode_POS
30 465:
#define
AG903_DMACn_CFG_REG_WOMode_MSK
(0x1UL <<
AG903_DMACn_CFG_REG_WOMode_POS
) 466:
#define
AG903_DMACn_CFG_REG_UnalignMode_POS
31 467:
#define
AG903_DMACn_CFG_REG_UnalignMode_MSK
(0x1UL <<
AG903_DMACn_CFG_REG_UnalignMode_POS
) 468: 469:
#define
AG903_DMACn_SRC_ADDR_SrcAddr_POS
0 470:
#define
AG903_DMACn_SRC_ADDR_SrcAddr_MSK
(0xffffffffUL <<
AG903_DMACn_SRC_ADDR_SrcAddr_POS
) 471: 472:
#define
AG903_DMACn_DST_ADDR_DstAddr_POS
0 473:
#define
AG903_DMACn_DST_ADDR_DstAddr_MSK
(0xffffffffUL <<
AG903_DMACn_DST_ADDR_DstAddr_POS
) 474: 475:
#define
AG903_DMACn_LINK_LIST_POINTER_LLP_POS
0 476:
#define
AG903_DMACn_LINK_LIST_POINTER_LLP_MSK
(0xffffffffUL <<
AG903_DMACn_LINK_LIST_POINTER_LLP_POS
) 477: 478:
#define
AG903_DMACn_TRNS_SIZE_1D_TCnt_POS
0 479:
#define
AG903_DMACn_TRNS_SIZE_1D_TCnt_MSK
(0x3fffffUL <<
AG903_DMACn_TRNS_SIZE_1D_TCnt_POS
) 480: 481:
#define
AG903_DMACn_TRNS_SIZE_2D_XTCnt_POS
0 482:
#define
AG903_DMACn_TRNS_SIZE_2D_XTCnt_MSK
(0xffffUL <<
AG903_DMACn_TRNS_SIZE_2D_XTCnt_POS
) 483:
#define
AG903_DMACn_TRNS_SIZE_2D_YTCnt_POS
16 484:
#define
AG903_DMACn_TRNS_SIZE_2D_YTCnt_MSK
(0xffffUL <<
AG903_DMACn_TRNS_SIZE_2D_YTCnt_POS
) 485: 486:
#define
AG903_DMACn_STRIDE_SRC_DST_ADDR_SrcStride_POS
0 487:
#define
AG903_DMACn_STRIDE_SRC_DST_ADDR_SrcStride_MSK
(0xffffUL <<
AG903_DMACn_STRIDE_SRC_DST_ADDR_SrcStride_POS
) 488:
#define
AG903_DMACn_STRIDE_SRC_DST_ADDR_DstStride_POS
16 489:
#define
AG903_DMACn_STRIDE_SRC_DST_ADDR_DstStride_MSK
(0xffffUL <<
AG903_DMACn_STRIDE_SRC_DST_ADDR_DstStride_POS
) 490: 491:
#endif
492:
Copyright (c) 2017-2025 Axell Corporation. All rights reserved.
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