1:
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16:
17:
#include "AG903_errno.h"
18:
#include "AG903_intno.h"
19:
#include "timr/timrmgr.h"
20:
#include "timr/timrprm.h"
21:
#include "int/intmgr.h"
22:
23:
typedef void (*AG903_TIMRMgrIntHdr)(
void);
24:
25:
typedef struct _AG903_TIMRMgrInthdrStat {
26: int32_t hdrid;
27:
void* func;
28: }AG903_TIMRMgrInthdrStat;
29:
30:
typedef struct _AG903_TIMRMgrChStat{
31: AG903_TIMRMgrInthdrStat inthdr[
AG903_TIMR_INTHDR_NUM];
32: uint8_t mode;
33: uint8_t outmode;
34: uint8_t reserve[2];
35: } AG903_TIMRMgrChStat;
36:
37:
typedef struct _AG903_TIMRMgrHandleStat{
38: uint8_t lock;
39: uint8_t reserve[3];
40: } AG903_TIMRMgrHandleStat;
41:
42:
static AG903_TIMRMgrChStat TimrChStat[
AG903_TIMR_CH_NUM];
43:
static AG903_TIMRMgrHandleStat TimrHandleStat[
AG903_TIMR_CH_NUM];
44:
45:
static const uint8_t TimrResolutionTypeTbl[AG903_TIMR_CNT_TYPENUM] =
46: {AG903_TIMR_RES_SYSCLK, AG903_TIMR_RES_TICK0, AG903_TIMR_RES_TICK1};
47:
static const uint8_t TimrOutModeTbl[AG903_TIMR_OUT_MODENUM] =
48: {AG903_TIMR_OUTMOD_PLUSE, AG903_TIMR_OUTMOD_LEVEL, AG903_TIMR_OUTMOD_PWM};
49:
static const uint8_t TimrInputReTbl[AG903_TIMR_INPUT_RETYPENUM][2] =
50: {{0,0},{0,2},{1,0},{1,2}};
51:
static const uint8_t TimrInputTbl[AG903_TIMR_INPUT_TYPENUM][2] =
52: {{0,0},{0,1},{0,2},{0,3},{1,0},{1,1},{1,2},{1,3}};
53:
static const uint8_t TimrResetTriggerTbl[AG903_TIMR_RSTTRG_TYPENUM] =
54: {AG903_TIMR_RSTEN_EXTPORT, AG903_TIMR_RSTEN_EVENT};
55:
56:
static void TIMRMgr_Init(uint8_t ch);
57:
static int32_t TIMRMgr_CheckHandle(
AG903_TIMRMgrHandle* handle, uint8_t* ch);
58:
static _Bool TIMRMgr_CheckIdle(uint8_t ch);
59:
60:
69: int32_t
AG903_TIMRMgrInit(
void)
70: {
71: int32_t retval =
AG903_ENONE;
72: uint32_t loop;
73:
74:
for(loop=0; loop<
AG903_TIMR_CH_NUM; loop++) {
75: TIMRMgr_Init(loop);
76: }
77:
78:
return retval;
79: }
80:
81:
90: int32_t
AG903_TIMRMgrGetHandle(
AG903_TIMRMgrHandle** handle)
91: {
92: int32_t retval =
AG903_ENONE;
93: uint32_t loop;
94:
95:
if(NULL == handle) {
96:
return -
AG903_EINVAL;
97: }
98:
99:
for(loop=0; loop<
AG903_TIMR_CH_NUM; loop++) {
100:
if(
false == TimrHandleStat[loop].lock) {
101: TimrHandleStat[loop].lock =
true;
102:
break;
103: }
104: }
105:
if(
AG903_TIMR_CH_NUM <= loop) {
106:
return -
AG903_EBUSY;
107: }
108:
109: (*handle) = (
AG903_TIMRMgrHandle*)&TimrHandleStat[loop];
110:
111:
return retval;
112: }
113:
114:
124: int32_t
AG903_TIMRMgrGetHandleCh(
AG903_TIMRMgrHandle** handle,
int ch)
125: {
126: int32_t retval =
AG903_ENONE;
127:
128:
if(NULL == handle) {
129:
return -
AG903_EINVAL;
130: }
131:
if (ch < 0 ||
AG903_TIMR_CH_NUM <= ch) {
132:
return -
AG903_EINVAL;
133: }
134:
135:
if(
false == TimrHandleStat[ch].lock) {
136: TimrHandleStat[ch].lock =
true;
137: }
else {
138:
return -
AG903_EBUSY;
139: }
140:
141: (*handle) = (
AG903_TIMRMgrHandle*)&TimrHandleStat[ch];
142:
143:
return retval;
144: }
145:
146:
156: int32_t
AG903_TIMRMgrReleaseHandle(
AG903_TIMRMgrHandle* handle)
157: {
158: int32_t retval =
AG903_ENONE;
159: int32_t result;
160: uint8_t ch;
161: uint8_t idle;
162:
163: result = TIMRMgr_CheckHandle(handle, &ch);
164:
if(
AG903_ENONE != result) {
165:
return -
AG903_EINVAL;
166: }
167: idle = TIMRMgr_CheckIdle(ch);
168:
if(
true != idle) {
169:
return -
AG903_EBUSY;
170: }
171:
172: TimrHandleStat[ch].lock =
false;
173:
174:
return retval;
175: }
176:
177:
200: int32_t
AG903_TIMRMgrSetIntHandler(
AG903_TIMRMgrHandle* handle,
void* func,
void* param)
201: {
202:
AG903_INTMgrHdrPrm inthdr;
203: int32_t retval =
AG903_ENONE;
204: int32_t result;
205: int32_t hdrid;
206: uint32_t loop;
207: uint8_t ch;
208:
209: result = TIMRMgr_CheckHandle(handle, &ch);
210:
if(
AG903_ENONE != result) {
211:
return -
AG903_EINVAL;
212: }
213:
if(NULL == func) {
214:
return -
AG903_EINVAL;
215: }
216:
for(loop=0; loop<
AG903_TIMR_INTHDR_NUM; loop++) {
217:
if(NULL == TimrChStat[ch].inthdr[loop].func) {
218:
break;
219: }
220: }
221:
if(
AG903_TIMR_INTHDR_NUM <= loop) {
222:
return -
AG903_EFAULT;
223: }
224:
225: inthdr.atr =
AG903_INT_HLNG;
226: inthdr.intno =
AG903_IRQ0_TIM0+ch;
227: inthdr.func = func;
228: inthdr.exinf = param;
229: hdrid =
AG903_INTMgrSetHandler(&inthdr);
230:
if(0 >= hdrid) {
231:
return -
AG903_EFAULT;
232: }
233:
AG903_INTMgrEnableInt(
AG903_IRQ0_TIM0+ch);
234: TimrChStat[ch].inthdr[loop].hdrid = hdrid;
235: TimrChStat[ch].inthdr[loop].func = func;
236:
237:
return retval;
238: }
239:
240:
249: int32_t
AG903_TIMRMgrDeleteIntHandler(
AG903_TIMRMgrHandle* handle,
void* func)
250: {
251: int32_t retval =
AG903_ENONE;
252: int32_t result;
253: uint32_t loop;
254: uint8_t ch;
255:
256: result = TIMRMgr_CheckHandle(handle, &ch);
257:
if(
AG903_ENONE != result) {
258:
return -
AG903_EINVAL;
259: }
260:
if(NULL == func) {
261:
return -
AG903_EINVAL;
262: }
263:
for(loop=0; loop<
AG903_TIMR_INTHDR_NUM; loop++) {
264:
if(func == TimrChStat[ch].inthdr[loop].func) {
265:
break;
266: }
267: }
268:
if(
AG903_TIMR_INTHDR_NUM <= loop) {
269:
return -
AG903_EINVAL;
270: }
271:
272: retval =
AG903_INTMgrDeleteHandler(TimrChStat[ch].inthdr[loop].hdrid);
273:
if(
AG903_ENONE == retval) {
274: TimrChStat[ch].inthdr[loop].hdrid = 0;
275: TimrChStat[ch].inthdr[loop].func = NULL;
276: }
277:
278:
return retval;
279: }
280:
281:
292: int32_t
AG903_TIMRMgrSetRotaryEncoderMode(
AG903_TIMRMgrHandle* handle,
AG903_TIMRMgrRotaryEncParam* param)
293: {
294:
AG903_TIMRPrmInModeParam inprm = {0};
295:
AG903_TIMRPrmOutModeParam outprm = {0};
296:
AG903_TIMRPrmResetTriggerParam rstprm = {0};
297: int32_t retval =
AG903_ENONE;
298: int32_t result;
299: uint8_t ch;
300: uint8_t idle;
301:
302: result = TIMRMgr_CheckHandle(handle, &ch);
303:
if(
AG903_ENONE != result) {
304:
return -
AG903_EINVAL;
305: }
306:
if(NULL == param) {
307:
return -
AG903_EINVAL;
308: }
309:
if( (AG903_TIMR_INPUT_RETYPENUM <= param->intype) ||
310: (AG903_TIMR_CNT_TYPENUM <= param->sampling) ) {
311:
return -
AG903_EINVAL;
312: }
313:
if(NULL != param->output) {
314:
if( (
AG903_TIMR_EXTOUT_NUM <= param->output->portch) ||
315: (AG903_TIMR_POL_TYPENUM <= param->output->polarity) ||
316: (AG903_TIMR_OUT_PWM <= param->output->mode) ||
317: ((AG903_TIMR_OUT_PLUSE == param->output->mode)&&(
AG903_TIMR_PLUSEWIDTH_MAX < param->output->plusewidth)) ) {
318:
return -
AG903_EINVAL;
319: }
320: }
321: idle = TIMRMgr_CheckIdle(ch);
322:
if(
true != idle) {
323:
return -
AG903_EBUSY;
324: }
325:
326: inprm.res = TimrResolutionTypeTbl[param->sampling];
327: inprm.lo = TimrInputReTbl[param->intype][0];
328: inprm.ch = TimrInputReTbl[param->intype][1];
329:
AG903_TIMRPrmSetInMode(ch, &inprm);
330:
AG903_TIMRPrmSetPeriod(ch, param->range);
331:
AG903_TIMRPrmSetMatch(ch, param->match);
332:
333:
if(NULL == param->output) {
334: outprm.mod = AG903_TIMR_OUTMOD_DISABLE;
335: }
336:
else {
337: outprm.ovf = 1;
338: outprm.ch = param->output->portch;
339: outprm.pol = param->output->polarity;
340: outprm.mod = TimrOutModeTbl[param->output->mode];
341: }
342:
AG903_TIMRPrmSetOutMode(ch, &outprm);
343:
if(AG903_TIMR_OUTMOD_PLUSE == outprm.mod) {
344:
AG903_TIMRPrmSetPluseWidth(ch, param->output->plusewidth);
345: }
346:
347: rstprm.en = AG903_TIMR_RSTEN_DISABLE;
348:
AG903_TIMRPrmSetResetTrigger(ch, &rstprm);
349:
350: TimrChStat[ch].outmode = outprm.mod;
351: TimrChStat[ch].mode = AG903_TIMR_CTRLMOD_REIN;
352:
353:
return retval;
354: }
355:
356:
367: int32_t
AG903_TIMRMgrSetPwmInMode(
AG903_TIMRMgrHandle* handle,
AG903_TIMRMgrPwmInParam* param)
368: {
369:
AG903_TIMRPrmInModeParam inprm = {0};
370:
AG903_TIMRPrmOutModeParam outprm = {0};
371:
AG903_TIMRPrmResetTriggerParam rstprm = {0};
372: int32_t retval =
AG903_ENONE;
373: int32_t result;
374: uint8_t ch;
375: uint8_t idle;
376:
377: result = TIMRMgr_CheckHandle(handle, &ch);
378:
if(
AG903_ENONE != result) {
379:
return -
AG903_EINVAL;
380: }
381:
if(NULL == param) {
382:
return -
AG903_EINVAL;
383: }
384:
if( (AG903_TIMR_INPUT_TYPENUM <= param->intype) ||
385: (AG903_TIMR_CNT_TYPENUM <= param->resolution) ||
386: (AG903_TIMR_POL_TYPENUM <= param->polarity) ) {
387:
return -
AG903_EINVAL;
388: }
389:
if(NULL != param->output) {
390:
if( (
AG903_TIMR_EXTOUT_NUM <= param->output->portch) ||
391: (AG903_TIMR_POL_TYPENUM <= param->output->polarity) ||
392: (AG903_TIMR_OUT_PWM <= param->output->mode) ||
393: ((AG903_TIMR_OUT_PLUSE == param->output->mode)&&(
AG903_TIMR_PLUSEWIDTH_MAX < param->output->plusewidth)) ) {
394:
return -
AG903_EINVAL;
395: }
396: }
397: idle = TIMRMgr_CheckIdle(ch);
398:
if(
true != idle) {
399:
return -
AG903_EBUSY;
400: }
401:
402: inprm.res = TimrResolutionTypeTbl[param->resolution];
403: inprm.lo = TimrInputTbl[param->intype][0];
404: inprm.ch = TimrInputTbl[param->intype][1];
405: inprm.pol = param->polarity;
406:
AG903_TIMRPrmSetInMode(ch, &inprm);
407:
if(
true == param->oneshot) {
408:
AG903_TIMRPrmEnableOneshot(ch);
409: }
410:
else {
411:
AG903_TIMRPrmDisableOneshot(ch);
412: }
413:
414:
if(NULL == param->output) {
415: outprm.mod = AG903_TIMR_OUTMOD_DISABLE;
416: }
417:
else {
418: outprm.cm = 1;
419: outprm.ch = param->output->portch;
420: outprm.pol = param->output->polarity;
421: outprm.mod = TimrOutModeTbl[param->output->mode];
422: }
423:
AG903_TIMRPrmSetOutMode(ch, &outprm);
424:
if(AG903_TIMR_OUTMOD_PLUSE == outprm.mod) {
425:
AG903_TIMRPrmSetPluseWidth(ch, param->output->plusewidth);
426: }
427:
428: rstprm.en = AG903_TIMR_RSTEN_DISABLE;
429:
AG903_TIMRPrmSetResetTrigger(ch, &rstprm);
430:
431: TimrChStat[ch].outmode = outprm.mod;
432: TimrChStat[ch].mode = AG903_TIMR_CTRLMOD_PWMIN;
433:
434:
return retval;
435: }
436:
437:
447: int32_t
AG903_TIMRMgrSetTickCountMode(
AG903_TIMRMgrHandle* handle,
AG903_TIMRMgrTickCntParam* param)
448: {
449:
AG903_TIMRPrmInModeParam inprm = {0};
450:
AG903_TIMRPrmOutModeParam outprm = {0};
451:
AG903_TIMRPrmResetTriggerParam rstprm = {0};
452: int32_t retval =
AG903_ENONE;
453: int32_t result;
454: uint8_t ch;
455: uint8_t idle;
456:
457: result = TIMRMgr_CheckHandle(handle, &ch);
458:
if(
AG903_ENONE != result) {
459:
return -
AG903_EINVAL;
460: }
461:
if(NULL == param) {
462:
return -
AG903_EINVAL;
463: }
464:
if(AG903_TIMR_CNT_TYPENUM <= param->resolution) {
465:
return -
AG903_EINVAL;
466: }
467:
if(NULL != param->output) {
468:
if( (
AG903_TIMR_EXTOUT_NUM <= param->output->portch) ||
469: (AG903_TIMR_POL_TYPENUM <= param->output->polarity) ||
470: (AG903_TIMR_OUT_MODENUM <= param->output->mode) ||
471: ((AG903_TIMR_OUT_PLUSE == param->output->mode)&&(
AG903_TIMR_PLUSEWIDTH_MAX < param->output->plusewidth)) ) {
472:
return -
AG903_EINVAL;
473: }
474: }
475: idle = TIMRMgr_CheckIdle(ch);
476:
if(
true != idle) {
477:
return -
AG903_EBUSY;
478: }
479:
480: inprm.res = TimrResolutionTypeTbl[param->resolution];
481:
AG903_TIMRPrmSetInMode(ch, &inprm);
482:
AG903_TIMRPrmSetPeriod(ch, param->period);
483:
AG903_TIMRPrmSetMatch(ch, param->match);
484:
if(
true == param->oneshot) {
485:
AG903_TIMRPrmEnableOneshot(ch);
486: }
487:
else {
488:
AG903_TIMRPrmDisableOneshot(ch);
489: }
490:
491:
if(NULL == param->output) {
492: outprm.mod = AG903_TIMR_OUTMOD_DISABLE;
493: }
494:
else {
495:
if(
AG903_TIMR_COMPARE_BIT & param->output->mask) {
496: outprm.cm = 1;
497: }
498:
if(
AG903_TIMR_OVERFLOW_BIT & param->output->mask) {
499: outprm.ovf = 1;
500: }
501: outprm.ch = param->output->portch;
502: outprm.pol = param->output->polarity;
503: outprm.mod = TimrOutModeTbl[param->output->mode];
504: }
505:
AG903_TIMRPrmSetOutMode(ch, &outprm);
506:
if(AG903_TIMR_OUTMOD_PLUSE == outprm.mod) {
507:
AG903_TIMRPrmSetPluseWidth(ch, param->output->plusewidth);
508: }
509:
510: rstprm.en = AG903_TIMR_RSTEN_DISABLE;
511: rstprm.boot = AG903_TIMR_RSTBOOT_TICKCNT;
512:
AG903_TIMRPrmSetResetTrigger(ch, &rstprm);
513:
514: TimrChStat[ch].outmode = outprm.mod;
515: TimrChStat[ch].mode = AG903_TIMR_CTRLMOD_TICKCNT;
516:
517:
return retval;
518: }
519:
520:
531: int32_t
AG903_TIMRMgrSetEventCountMode(
AG903_TIMRMgrHandle* handle,
AG903_TIMRMgrEventCntParam* param)
532: {
533:
AG903_TIMRPrmInModeParam inprm = {0};
534:
AG903_TIMRPrmOutModeParam outprm = {0};
535:
AG903_TIMRPrmResetTriggerParam rstprm = {0};
536: int32_t retval =
AG903_ENONE;
537: int32_t result;
538: uint8_t ch;
539: uint8_t idle;
540:
541: result = TIMRMgr_CheckHandle(handle, &ch);
542:
if(
AG903_ENONE != result) {
543:
return -
AG903_EINVAL;
544: }
545:
if(NULL == param) {
546:
return -
AG903_EINVAL;
547: }
548:
if(
AG903_TIMR_EVENT_NUM <= param->event) {
549:
return -
AG903_EINVAL;
550: }
551:
if(NULL != param->output) {
552:
if( (
AG903_TIMR_EXTOUT_NUM <= param->output->portch) ||
553: (AG903_TIMR_POL_TYPENUM <= param->output->polarity) ||
554: (AG903_TIMR_OUT_PWM <= param->output->mode) ||
555: ((AG903_TIMR_OUT_PLUSE == param->output->mode)&&(
AG903_TIMR_PLUSEWIDTH_MAX < param->output->plusewidth)) ) {
556:
return -
AG903_EINVAL;
557: }
558: }
559: idle = TIMRMgr_CheckIdle(ch);
560:
if(
true != idle) {
561:
return -
AG903_EBUSY;
562: }
563:
564: inprm.eve = param->event;
565:
AG903_TIMRPrmSetInMode(ch, &inprm);
566:
AG903_TIMRPrmSetPeriod(ch, param->period);
567:
AG903_TIMRPrmSetMatch(ch, param->match);
568:
if(
true == param->oneshot) {
569:
AG903_TIMRPrmEnableOneshot(ch);
570: }
571:
else {
572:
AG903_TIMRPrmDisableOneshot(ch);
573: }
574:
575:
if(NULL == param->output) {
576: outprm.mod = AG903_TIMR_OUTMOD_DISABLE;
577: }
578:
else {
579:
if(
AG903_TIMR_COMPARE_BIT & param->output->mask) {
580: outprm.cm = 1;
581: }
582:
if(
AG903_TIMR_OVERFLOW_BIT & param->output->mask) {
583: outprm.ovf = 1;
584: }
585: outprm.ch = param->output->portch;
586: outprm.pol = param->output->polarity;
587: outprm.mod = TimrOutModeTbl[param->output->mode];
588: }
589:
AG903_TIMRPrmSetOutMode(ch, &outprm);
590:
if(AG903_TIMR_OUTMOD_PLUSE == outprm.mod) {
591:
AG903_TIMRPrmSetPluseWidth(ch, param->output->plusewidth);
592: }
593:
594: rstprm.en = AG903_TIMR_RSTEN_DISABLE;
595: rstprm.boot = AG903_TIMR_RSTBOOT_EVENTCNT;
596:
AG903_TIMRPrmSetResetTrigger(ch, &rstprm);
597:
598: TimrChStat[ch].outmode = outprm.mod;
599: TimrChStat[ch].mode = AG903_TIMR_CTRLMOD_EVENTCNT;
600:
601:
return retval;
602: }
603:
604:
615: int32_t
AG903_TIMRMgrSetPulseCountMode(
AG903_TIMRMgrHandle* handle,
AG903_TIMRMgrPulseCntParam* param)
616: {
617:
AG903_TIMRPrmInModeParam inprm = {0};
618:
AG903_TIMRPrmOutModeParam outprm = {0};
619:
AG903_TIMRPrmResetTriggerParam rstprm = {0};
620: int32_t retval =
AG903_ENONE;
621: int32_t result;
622: uint8_t ch;
623: uint8_t idle;
624:
625: result = TIMRMgr_CheckHandle(handle, &ch);
626:
if(
AG903_ENONE != result) {
627:
return -
AG903_EINVAL;
628: }
629:
if(NULL == param) {
630:
return -
AG903_EINVAL;
631: }
632:
if( (AG903_TIMR_INPUT_TYPENUM <= param->intype) ||
633: (AG903_TIMR_CNT_TYPENUM <= param->sampling) ||
634: (AG903_TIMR_POL_TYPENUM <= param->polarity) ) {
635:
return -
AG903_EINVAL;
636: }
637:
if(NULL != param->output) {
638:
if( (
AG903_TIMR_EXTOUT_NUM <= param->output->portch) ||
639: (AG903_TIMR_POL_TYPENUM <= param->output->polarity) ||
640: (AG903_TIMR_OUT_PWM <= param->output->mode) ||
641: ((AG903_TIMR_OUT_PLUSE == param->output->mode)&&(
AG903_TIMR_PLUSEWIDTH_MAX < param->output->plusewidth)) ) {
642:
return -
AG903_EINVAL;
643: }
644: }
645: idle = TIMRMgr_CheckIdle(ch);
646:
if(
true != idle) {
647:
return -
AG903_EBUSY;
648: }
649:
650: inprm.res = TimrResolutionTypeTbl[param->sampling];
651: inprm.lo = TimrInputTbl[param->intype][0];
652: inprm.ch = TimrInputTbl[param->intype][1];
653: inprm.pol = param->polarity;
654:
AG903_TIMRPrmSetInMode(ch, &inprm);
655:
AG903_TIMRPrmSetPeriod(ch, param->period);
656:
AG903_TIMRPrmSetMatch(ch, param->match);
657:
if(
true == param->oneshot) {
658:
AG903_TIMRPrmEnableOneshot(ch);
659: }
660:
else {
661:
AG903_TIMRPrmDisableOneshot(ch);
662: }
663:
664:
if(NULL == param->output) {
665: outprm.mod = AG903_TIMR_OUTMOD_DISABLE;
666: }
667:
else {
668:
if(
AG903_TIMR_COMPARE_BIT & param->output->mask) {
669: outprm.cm = 1;
670: }
671:
if(
AG903_TIMR_OVERFLOW_BIT & param->output->mask) {
672: outprm.ovf = 1;
673: }
674: outprm.ch = param->output->portch;
675: outprm.pol = param->output->polarity;
676: outprm.mod = TimrOutModeTbl[param->output->mode];
677: }
678:
AG903_TIMRPrmSetOutMode(ch, &outprm);
679:
if(AG903_TIMR_OUTMOD_PLUSE == outprm.mod) {
680:
AG903_TIMRPrmSetPluseWidth(ch, param->output->plusewidth);
681: }
682:
683: rstprm.en = AG903_TIMR_RSTEN_DISABLE;
684: rstprm.boot = AG903_TIMR_RSTBOOT_PLUSECNT;
685:
AG903_TIMRPrmSetResetTrigger(ch, &rstprm);
686:
687: TimrChStat[ch].outmode = outprm.mod;
688: TimrChStat[ch].mode = AG903_TIMR_CTRLMOD_PLUSECNT;
689:
690:
return retval;
691: }
692:
693:
704: int32_t
AG903_TIMRMgrSetLevelCountMode(
AG903_TIMRMgrHandle* handle,
AG903_TIMRMgrLevelCntParam* param)
705: {
706:
AG903_TIMRPrmInModeParam inprm = {0};
707:
AG903_TIMRPrmOutModeParam outprm = {0};
708:
AG903_TIMRPrmResetTriggerParam rstprm = {0};
709: int32_t retval =
AG903_ENONE;
710: int32_t result;
711: uint8_t ch;
712: uint8_t idle;
713:
714: result = TIMRMgr_CheckHandle(handle, &ch);
715:
if(
AG903_ENONE != result) {
716:
return -
AG903_EINVAL;
717: }
718:
if(NULL == param) {
719:
return -
AG903_EINVAL;
720: }
721:
if( (AG903_TIMR_INPUT_TYPENUM <= param->intype) ||
722: (AG903_TIMR_CNT_TYPENUM <= param->sampling) ||
723: (AG903_TIMR_POL_TYPENUM <= param->polarity) ) {
724:
return -
AG903_EINVAL;
725: }
726:
if(NULL != param->output) {
727:
if( (
AG903_TIMR_EXTOUT_NUM <= param->output->portch) ||
728: (AG903_TIMR_POL_TYPENUM <= param->output->polarity) ||
729: (AG903_TIMR_OUT_PWM <= param->output->mode) ||
730: ((AG903_TIMR_OUT_PLUSE == param->output->mode)&&(
AG903_TIMR_PLUSEWIDTH_MAX < param->output->plusewidth)) ) {
731:
return -
AG903_EINVAL;
732: }
733: }
734: idle = TIMRMgr_CheckIdle(ch);
735:
if(
true != idle) {
736:
return -
AG903_EBUSY;
737: }
738:
739: inprm.res = TimrResolutionTypeTbl[param->sampling];
740: inprm.lo = TimrInputTbl[param->intype][0];
741: inprm.ch = TimrInputTbl[param->intype][1];
742: inprm.pol = param->polarity;
743:
AG903_TIMRPrmSetInMode(ch, &inprm);
744:
AG903_TIMRPrmSetPeriod(ch, param->period);
745:
AG903_TIMRPrmSetMatch(ch, param->match);
746:
if(
true == param->oneshot) {
747:
AG903_TIMRPrmEnableOneshot(ch);
748: }
749:
else {
750:
AG903_TIMRPrmDisableOneshot(ch);
751: }
752:
753:
if(NULL == param->output) {
754: outprm.mod = AG903_TIMR_OUTMOD_DISABLE;
755: }
756:
else {
757:
if(
AG903_TIMR_COMPARE_BIT & param->output->mask) {
758: outprm.cm = 1;
759: }
760:
if(
AG903_TIMR_OVERFLOW_BIT & param->output->mask) {
761: outprm.ovf = 1;
762: }
763: outprm.ch = param->output->portch;
764: outprm.pol = param->output->polarity;
765: outprm.mod = TimrOutModeTbl[param->output->mode];
766: }
767:
AG903_TIMRPrmSetOutMode(ch, &outprm);
768:
if(AG903_TIMR_OUTMOD_PLUSE == outprm.mod) {
769:
AG903_TIMRPrmSetPluseWidth(ch, param->output->plusewidth);
770: }
771:
772: rstprm.en = AG903_TIMR_RSTEN_DISABLE;
773: rstprm.boot = AG903_TIMR_RSTBOOT_LEVELCNT;
774:
AG903_TIMRPrmSetResetTrigger(ch, &rstprm);
775:
776: TimrChStat[ch].outmode = outprm.mod;
777: TimrChStat[ch].mode = AG903_TIMR_CTRLMOD_LEVELCNT;
778:
779:
return retval;
780: }
781:
782:
796: int32_t
AG903_TIMRMgrStart(
AG903_TIMRMgrHandle* handle)
797: {
798: int32_t retval =
AG903_ENONE;
799: int32_t result;
800: uint8_t ch;
801: uint8_t idle;
802:
803: result = TIMRMgr_CheckHandle(handle, &ch);
804:
if(
AG903_ENONE != result) {
805:
return -
AG903_EINVAL;
806: }
807:
if(AG903_TIMR_CTRLMOD_MODENUM <= TimrChStat[ch].mode) {
808:
return -
AG903_EFAULT;
809: }
810: idle = TIMRMgr_CheckIdle(ch);
811:
if(
true != idle) {
812:
return -
AG903_EBUSY;
813: }
814:
815:
AG903_TIMRPrmSetCntMode(ch, TimrChStat[ch].mode);
816:
817:
return retval;
818: }
819:
820:
828: int32_t
AG903_TIMRMgrStop(
AG903_TIMRMgrHandle* handle)
829: {
830: int32_t retval =
AG903_ENONE;
831: int32_t result;
832: uint8_t ch;
833:
834: result = TIMRMgr_CheckHandle(handle, &ch);
835:
if(
AG903_ENONE != result) {
836:
return -
AG903_EINVAL;
837: }
838:
839:
AG903_TIMRPrmSetCntMode(ch, AG903_TIMR_CTRLMOD_STOP);
840:
841:
return retval;
842: }
843:
844:
855: int32_t
AG903_TIMRMgrStartMulti(uint8_t chbit)
856: {
857: int32_t retval =
AG903_ENONE;
858:
859:
AG903_TIMRPrmSetBootTrigger(chbit);
860:
861:
return retval;
862: }
863:
864:
876: int32_t
AG903_TIMRMgrEnableResetTrigger(
AG903_TIMRMgrHandle* handle,
AG903_TIMRMgrResetParam* param)
877: {
878:
AG903_TIMRPrmResetTriggerParam rstprm = {0};
879: int32_t retval =
AG903_ENONE;
880: int32_t result;
881: uint8_t ch;
882:
883: result = TIMRMgr_CheckHandle(handle, &ch);
884:
if(
AG903_ENONE != result) {
885:
return -
AG903_EINVAL;
886: }
887:
if(NULL == param) {
888:
return -
AG903_EINVAL;
889: }
890:
if(AG903_TIMR_RSTTRG_TYPENUM <= param->trigger) {
891:
return -
AG903_EINVAL;
892: }
893:
if(AG903_TIMR_RSTTRG_EXTPORT == param->trigger) {
894:
if( (AG903_TIMR_INPUT_TYPENUM <= param->intype) ||
895: (AG903_TIMR_CNT_TYPENUM <= param->sampling) ||
896: (AG903_TIMR_POL_TYPENUM <= param->polarity) ) {
897:
return -
AG903_EINVAL;
898: }
899: }
900:
else {
901:
if(
AG903_TIMR_EVENT_NUM <= param->event) {
902:
return -
AG903_EINVAL;
903: }
904: }
905:
906:
switch(TimrChStat[ch].mode) {
907:
case AG903_TIMR_CTRLMOD_TICKCNT:
908: rstprm.boot = AG903_TIMR_RSTBOOT_TICKCNT;
909:
break;
910:
case AG903_TIMR_CTRLMOD_EVENTCNT:
911: rstprm.boot = AG903_TIMR_RSTBOOT_EVENTCNT;
912:
break;
913:
case AG903_TIMR_CTRLMOD_PLUSECNT:
914: rstprm.boot = AG903_TIMR_RSTBOOT_PLUSECNT;
915:
break;
916:
case AG903_TIMR_CTRLMOD_LEVELCNT:
917: rstprm.boot = AG903_TIMR_RSTBOOT_LEVELCNT;
918:
break;
919:
default:
920: retval = -
AG903_EFAULT;
921:
break;
922: }
923:
924:
if(
AG903_ENONE == retval) {
925: rstprm.en = TimrResetTriggerTbl[param->trigger];
926:
if(AG903_TIMR_RSTEN_EXTPORT == rstprm.en) {
927: rstprm.res = TimrResolutionTypeTbl[param->sampling];
928: rstprm.lo = TimrInputTbl[param->intype][0];
929: rstprm.ch = TimrInputTbl[param->intype][1];
930: rstprm.pol = param->polarity;
931: }
932:
else {
933: rstprm.eve = param->event;
934: }
935:
AG903_TIMRPrmSetResetTrigger(ch, &rstprm);
936: }
937:
938:
return retval;
939: }
940:
941:
950: int32_t
AG903_TIMRMgrDisableResetTrigger(
AG903_TIMRMgrHandle* handle)
951: {
952:
AG903_TIMRPrmResetTriggerParam rstprm = {0};
953: int32_t retval =
AG903_ENONE;
954: int32_t result;
955: uint8_t ch;
956:
957: result = TIMRMgr_CheckHandle(handle, &ch);
958:
if(
AG903_ENONE != result) {
959:
return -
AG903_EINVAL;
960: }
961:
962: rstprm.en = AG903_TIMR_RSTEN_DISABLE;
963:
AG903_TIMRPrmSetResetTrigger(ch, &rstprm);
964:
965:
return retval;
966: }
967:
968:
980: int32_t
AG903_TIMRMgrEnableOneShot(
AG903_TIMRMgrHandle* handle)
981: {
982: int32_t retval =
AG903_ENONE;
983: int32_t result;
984: uint8_t ch;
985:
986: result = TIMRMgr_CheckHandle(handle, &ch);
987:
if(
AG903_ENONE != result) {
988:
return -
AG903_EINVAL;
989: }
990:
if(AG903_TIMR_CTRLMOD_REIN == TimrChStat[ch].mode) {
991:
return -
AG903_EFAULT;
992: }
993:
994:
AG903_TIMRPrmEnableOneshot(ch);
995:
996:
return retval;
997: }
998:
999:
1008: int32_t
AG903_TIMRMgrDisableOneShot(
AG903_TIMRMgrHandle* handle)
1009: {
1010: int32_t retval =
AG903_ENONE;
1011: int32_t result;
1012: uint8_t ch;
1013:
1014: result = TIMRMgr_CheckHandle(handle, &ch);
1015:
if(
AG903_ENONE != result) {
1016:
return -
AG903_EINVAL;
1017: }
1018:
1019:
AG903_TIMRPrmDisableOneshot(ch);
1020:
1021:
return retval;
1022: }
1023:
1024:
1040: int32_t
AG903_TIMRMgrEnableIntMask(
AG903_TIMRMgrHandle* handle, uint8_t target)
1041: {
1042: int32_t retval =
AG903_ENONE;
1043: int32_t result;
1044: uint32_t setbit = 0;
1045: uint8_t ch;
1046:
1047: result = TIMRMgr_CheckHandle(handle, &ch);
1048:
if(
AG903_ENONE != result) {
1049:
return -
AG903_EINVAL;
1050: }
1051:
1052:
if(
AG903_TIMR_COMPARE_BIT & target) {
1053: setbit |=
AG903_TIMR_INTMSK_CM_BIT;
1054: }
1055:
if(
AG903_TIMR_OVERFLOW_BIT & target) {
1056: setbit |=
AG903_TIMR_INTMSK_OVF_BIT;
1057: }
1058:
1059:
if(0 != setbit) {
1060:
AG903_TIMRPrmEnableMask(ch, setbit);
1061: }
1062:
1063:
return retval;
1064: }
1065:
1066:
1082: int32_t
AG903_TIMRMgrDisableIntMask(
AG903_TIMRMgrHandle* handle, uint8_t target)
1083: {
1084: int32_t retval =
AG903_ENONE;
1085: int32_t result;
1086: uint8_t clrbit = 0;
1087: uint8_t ch;
1088:
1089: result = TIMRMgr_CheckHandle(handle, &ch);
1090:
if(
AG903_ENONE != result) {
1091:
return -
AG903_EINVAL;
1092: }
1093:
1094:
if(
AG903_TIMR_COMPARE_BIT & target) {
1095: clrbit |=
AG903_TIMR_INTMSK_CM_BIT;
1096: }
1097:
if(
AG903_TIMR_OVERFLOW_BIT & target) {
1098: clrbit |=
AG903_TIMR_INTMSK_OVF_BIT;
1099: }
1100:
1101:
if(0 != clrbit) {
1102:
AG903_TIMRPrmDisableMask(ch, clrbit);
1103: }
1104:
1105:
return retval;
1106: }
1107:
1108:
1124: int32_t
AG903_TIMRMgrEnableEventTrigger(
AG903_TIMRMgrHandle* handle, uint8_t target)
1125: {
1126: int32_t retval =
AG903_ENONE;
1127: int32_t result;
1128: uint32_t setbit = 0;
1129: uint8_t ch;
1130:
1131: result = TIMRMgr_CheckHandle(handle, &ch);
1132:
if(
AG903_ENONE != result) {
1133:
return -
AG903_EINVAL;
1134: }
1135:
1136:
if(
AG903_TIMR_COMPARE_BIT & target) {
1137: setbit |=
AG903_TIMR_TRIGGER_CM_BIT;
1138: }
1139:
if(
AG903_TIMR_OVERFLOW_BIT & target) {
1140: setbit |=
AG903_TIMR_TRIGGER_OVF_BIT;
1141: }
1142:
1143:
if(0 != setbit) {
1144:
AG903_TIMRPrmEnableEventTrigger(ch, setbit);
1145: }
1146:
1147:
return retval;
1148: }
1149:
1150:
1166: int32_t
AG903_TIMRMgrDisableEventTrigger(
AG903_TIMRMgrHandle* handle, uint8_t target)
1167: {
1168: int32_t retval =
AG903_ENONE;
1169: int32_t result;
1170: uint32_t clrbit = 0;
1171: uint8_t ch;
1172:
1173: result = TIMRMgr_CheckHandle(handle, &ch);
1174:
if(
AG903_ENONE != result) {
1175:
return -
AG903_EINVAL;
1176: }
1177:
1178:
if(
AG903_TIMR_COMPARE_BIT & target) {
1179: clrbit |=
AG903_TIMR_TRIGGER_CM_BIT;
1180: }
1181:
if(
AG903_TIMR_OVERFLOW_BIT & target) {
1182: clrbit |=
AG903_TIMR_TRIGGER_OVF_BIT;
1183: }
1184:
1185:
if(0 != clrbit) {
1186:
AG903_TIMRPrmDisableEventTrigger(ch, clrbit);
1187: }
1188:
1189:
return retval;
1190: }
1191:
1192:
1208: int32_t
AG903_TIMRMgrEnableDmaRequest(
AG903_TIMRMgrHandle* handle, uint8_t target)
1209: {
1210: int32_t retval =
AG903_ENONE;
1211: int32_t result;
1212: uint32_t setbit = 0;
1213: uint8_t ch;
1214:
1215: result = TIMRMgr_CheckHandle(handle, &ch);
1216:
if(
AG903_ENONE != result) {
1217:
return -
AG903_EINVAL;
1218: }
1219:
1220:
if(
AG903_TIMR_COMPARE_BIT & target) {
1221: setbit |=
AG903_TIMR_DMAREQ_CM_BIT;
1222: }
1223:
if(
AG903_TIMR_OVERFLOW_BIT & target) {
1224: setbit |=
AG903_TIMR_DMAREQ_OVF_BIT;
1225: }
1226:
1227:
if(0 != setbit) {
1228:
AG903_TIMRPrmEnableDmaRequest(ch, setbit);
1229: }
1230:
1231:
return retval;
1232: }
1233:
1234:
1250: int32_t
AG903_TIMRMgrDisableDmaRequest(
AG903_TIMRMgrHandle* handle, uint8_t target)
1251: {
1252: int32_t retval =
AG903_ENONE;
1253: int32_t result;
1254: uint32_t clrbit = 0;
1255: uint8_t ch;
1256:
1257: result = TIMRMgr_CheckHandle(handle, &ch);
1258:
if(
AG903_ENONE != result) {
1259:
return -
AG903_EINVAL;
1260: }
1261:
1262:
if(
AG903_TIMR_COMPARE_BIT & target) {
1263: clrbit |=
AG903_TIMR_DMAREQ_CM_BIT;
1264: }
1265:
if(
AG903_TIMR_OVERFLOW_BIT & target) {
1266: clrbit |=
AG903_TIMR_DMAREQ_OVF_BIT;
1267: }
1268:
1269:
if(0 != clrbit) {
1270:
AG903_TIMRPrmDisableDmaRequest(ch, clrbit);
1271: }
1272:
1273:
return retval;
1274: }
1275:
1276:
1286: int32_t
AG903_TIMRMgrGetStatus(
AG903_TIMRMgrHandle* handle, uint32_t* status)
1287: {
1288: int32_t retval =
AG903_ENONE;
1289: int32_t result;
1290: uint8_t ch;
1291:
1292: result = TIMRMgr_CheckHandle(handle, &ch);
1293:
if(
AG903_ENONE != result) {
1294:
return -
AG903_EINVAL;
1295: }
1296:
if(NULL == status) {
1297:
return -
AG903_EINVAL;
1298: }
1299:
1300:
AG903_TIMRPrmGetStatus(ch, status);
1301:
1302:
return retval;
1303: }
1304:
1305:
1321: int32_t
AG903_TIMRMgrClearStatus(
AG903_TIMRMgrHandle* handle, uint32_t target)
1322: {
1323: int32_t retval =
AG903_ENONE;
1324: int32_t result;
1325: uint32_t clrbit = 0;
1326: uint8_t ch;
1327:
1328: result = TIMRMgr_CheckHandle(handle, &ch);
1329:
if(
AG903_ENONE != result) {
1330:
return -
AG903_EINVAL;
1331: }
1332:
1333:
if(
AG903_TIMR_COMPARE_BIT & target) {
1334: clrbit |=
AG903_TIMR_STAT_CM_BIT;
1335: }
1336:
if(
AG903_TIMR_OVERFLOW_BIT & target) {
1337: clrbit |=
AG903_TIMR_STAT_OVF_BIT;
1338: }
1339:
1340:
if(0 != clrbit) {
1341:
AG903_TIMRPrmClearStatus(ch, clrbit);
1342: }
1343:
1344:
return retval;
1345: }
1346:
1347:
1356: int32_t
AG903_TIMRMgrGetCount(
AG903_TIMRMgrHandle* handle, uint32_t* count)
1357: {
1358: int32_t retval =
AG903_ENONE;
1359: int32_t result;
1360: uint8_t ch;
1361:
1362: result = TIMRMgr_CheckHandle(handle, &ch);
1363:
if(
AG903_ENONE != result) {
1364:
return -
AG903_EINVAL;
1365: }
1366:
if(NULL == count) {
1367:
return -
AG903_EINVAL;
1368: }
1369:
1370:
AG903_TIMRPrmGetCount(ch, count);
1371:
1372:
return retval;
1373: }
1374:
1375:
1386: int32_t
AG903_TIMRMgrSetCount(
AG903_TIMRMgrHandle* handle, uint32_t count)
1387: {
1388: int32_t retval =
AG903_ENONE;
1389: int32_t result;
1390: uint8_t ch;
1391: uint8_t idle;
1392:
1393: result = TIMRMgr_CheckHandle(handle, &ch);
1394:
if(
AG903_ENONE != result) {
1395:
return -
AG903_EINVAL;
1396: }
1397: idle = TIMRMgr_CheckIdle(ch);
1398:
if(
true != idle) {
1399:
return -
AG903_EBUSY;
1400: }
1401:
1402:
AG903_TIMRPrmSetCount(ch, count);
1403:
1404:
return retval;
1405: }
1406:
1407:
1416: int32_t
AG903_TIMRMgrGetPeriodValue(
AG903_TIMRMgrHandle* handle, uint32_t* period)
1417: {
1418: int32_t retval =
AG903_ENONE;
1419: int32_t result;
1420: uint8_t ch;
1421:
1422: result = TIMRMgr_CheckHandle(handle, &ch);
1423:
if(
AG903_ENONE != result) {
1424:
return -
AG903_EINVAL;
1425: }
1426:
if(NULL == period) {
1427:
return -
AG903_EINVAL;
1428: }
1429:
1430:
AG903_TIMRPrmGetPeriod(ch, period);
1431:
1432:
return retval;
1433: }
1434:
1435:
1444: int32_t
AG903_TIMRMgrSetPeriodValue(
AG903_TIMRMgrHandle* handle, uint32_t period)
1445: {
1446: int32_t retval =
AG903_ENONE;
1447: int32_t result;
1448: uint8_t ch;
1449:
1450: result = TIMRMgr_CheckHandle(handle, &ch);
1451:
if(
AG903_ENONE != result) {
1452:
return -
AG903_EINVAL;
1453: }
1454:
1455:
AG903_TIMRPrmSetPeriod(ch, period);
1456:
1457:
return retval;
1458: }
1459:
1460:
1469: int32_t
AG903_TIMRMgrGetMatchValue(
AG903_TIMRMgrHandle* handle, uint32_t* match)
1470: {
1471: int32_t retval =
AG903_ENONE;
1472: int32_t result;
1473: uint8_t ch;
1474:
1475: result = TIMRMgr_CheckHandle(handle, &ch);
1476:
if(
AG903_ENONE != result) {
1477:
return -
AG903_EINVAL;
1478: }
1479:
if(NULL == match) {
1480:
return -
AG903_EINVAL;
1481: }
1482:
1483:
AG903_TIMRPrmGetMatch(ch, match);
1484:
1485:
return retval;
1486: }
1487:
1488:
1497: int32_t
AG903_TIMRMgrSetMatchValue(
AG903_TIMRMgrHandle* handle, uint32_t match)
1498: {
1499: int32_t retval =
AG903_ENONE;
1500: int32_t result;
1501: uint8_t ch;
1502:
1503: result = TIMRMgr_CheckHandle(handle, &ch);
1504:
if(
AG903_ENONE != result) {
1505:
return -
AG903_EINVAL;
1506: }
1507:
1508:
AG903_TIMRPrmSetMatch(ch, match);
1509:
1510:
return retval;
1511: }
1512:
1513:
1522: int32_t
AG903_TIMRMgrGetChannel(
AG903_TIMRMgrHandle* handle, uint8_t* ch)
1523: {
1524: int32_t retval =
AG903_ENONE;
1525: int32_t result;
1526:
1527:
if(NULL == ch) {
1528:
return -
AG903_EINVAL;
1529: }
1530:
1531: result = TIMRMgr_CheckHandle(handle, ch);
1532:
if(
AG903_ENONE != result) {
1533:
return -
AG903_EINVAL;
1534: }
1535:
1536:
return retval;
1537: }
1538:
1539:
1543:
static void TIMRMgr_Init(uint8_t ch)
1544: {
1545: uint32_t loop;
1546:
1547:
if(
AG903_TIMR_CH_NUM <= ch) {
1548:
return;
1549: }
1550:
1551:
for(loop=0; loop<
AG903_TIMR_INTHDR_NUM; loop++) {
1552: TimrChStat[ch].inthdr[loop].hdrid = 0;
1553: TimrChStat[ch].inthdr[loop].func = NULL;
1554: }
1555: TimrChStat[ch].mode = AG903_TIMR_CTRLMOD_STOP;
1556: TimrChStat[ch].outmode = AG903_TIMR_OUTMOD_DISABLE;
1557:
AG903_TIMRPrmSetCntMode(ch, AG903_TIMR_CTRLMOD_STOP);
1558:
1559: TimrHandleStat[ch].lock =
false;
1560:
1561:
return;
1562: }
1563:
1564:
1569:
static int32_t TIMRMgr_CheckHandle(
AG903_TIMRMgrHandle* handle, uint8_t* ch)
1570: {
1571: int32_t retval =
AG903_ENONE;
1572: uint32_t get_ch;
1573:
1574: get_ch = ((uint32_t)handle - (uint32_t)TimrHandleStat) /
sizeof(AG903_TIMRMgrHandleStat);
1575:
1576:
if( (
AG903_TIMR_CH_NUM <= get_ch) ||
1577: (&TimrHandleStat[get_ch] != (AG903_TIMRMgrHandleStat*)handle) ) {
1578:
return -
AG903_EINVAL;
1579: }
1580: (*ch) = (uint8_t)get_ch;
1581:
1582:
return retval;
1583: }
1584:
1585:
1590:
static _Bool TIMRMgr_CheckIdle(uint8_t ch)
1591: {
1592: uint8_t mode=0;
1593: _Bool retval=
false;
1594:
1595:
AG903_TIMRPrmGetCntMode(ch, &mode);
1596:
if(AG903_TIMR_CTRLMOD_STOP == mode) {
1597: retval=
true;
1598: }
1599:
1600:
return retval;
1601: }