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#ifndef __DSPMGR_H__
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#define __DSPMGR_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "AG903_common.h"
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#define AG903_DSP_CH_NUM (2)
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#define AG903_DSP_LUT_NUM (64)
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#define AG903_DSP_DITHAREA_NUM (4)
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#define AG903_DSP_WND_MAX (16)
44:
47:
#define AG903_DSP_ATTR_MAX (256)
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49:
50:
54:
enum AG903_DSP_CTRL_ENUM{
55: AG903_DSP_CTRL_OFF = 0 ,
56: AG903_DSP_CTRL_ON ,
57: };
58:
63:
enum AG903_DSP_POLARITY_ENUM{
64: AG903_DSP_POLARITY_NEGA = 0 ,
65: AG903_DSP_POLARITY_POSI ,
66: };
67:
71:
enum AG903_DSP_RGBDE_SIGNAL_ENUM{
72: AG903_DSP_RGBDE_SIGNAL_DATA = 0 ,
73: AG903_DSP_RGBDE_SIGNAL_CSYNC ,
74: };
75:
79:
enum AG903_DSP_ATTR_TIMING_ENUM{
80: AG903_DSP_ATTR_END_OF_VSYNC = 0 ,
81: AG903_DSP_ATTR_START_OF_VSYNC ,
82: AG903_DSP_ATTR_START_OF_VBLANK ,
83: };
84:
88:
enum AG903_DSP_FFMT_ENUM{
89: AG903_DSP_FFMT_A8R8G8B8 = 0 ,
90: AG903_DSP_FFMT_X8R8G8B8 ,
91: AG903_DSP_FFMT_R8G8B8 ,
92: AG903_DSP_FFMT_R5G6B5 ,
93: AG903_DSP_FFMT_A1R5G5B5 ,
94: AG903_DSP_FFMT_X1R5G5B5 ,
95: AG903_DSP_FFMT_A4R4G4B4 ,
96: AG903_DSP_FFMT_X4R4G4B4 ,
97: AG903_DSP_FFMT_YUV422_BT601_LIMIT ,
98: AG903_DSP_FFMT_YUV422_BT601_FULL ,
99: AG903_DSP_FFMT_YUV422_BT709_LIMIT ,
100: AG903_DSP_FFMT_YUV422_BT709_FULL ,
101: AG903_DSP_FFMT_256_PALLET0 ,
102: AG903_DSP_FFMT_256_PALLET1 ,
103: AG903_DSP_FFMT_16_PALLET ,
104: AG903_DSP_FFMT_2_PALLET ,
105: };
106:
110:
enum AG903_DSP_PFMT_ENUM{
111: AG903_DSP_PFMT_A8R8G8B8 = 0 ,
112: AG903_DSP_PFMT_X8R8G8B8 ,
113: AG903_DSP_PFMT_R8G8B8 ,
114: AG903_DSP_PFMT_R5G6B5 ,
115: AG903_DSP_PFMT_A1R5G5B5 ,
116: AG903_DSP_PFMT_X1R5G5B5 ,
117: AG903_DSP_PFMT_A4R4G4B4 ,
118: AG903_DSP_PFMT_X4R4G4B4 ,
119: };
120:
124:
enum AG903_DSP_BMU_ENUM{
125: AG903_DSP_BMU_WINDATA = 0 ,
126: AG903_DSP_BMU_WINATTR ,
127: };
128:
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enum AG903_DSP_VMODE_ENUM{
133: AG903_DSP_VMODE_NONINTERLACE = 0 ,
134: AG903_DSP_VMODE_INTERLACE ,
135: };
136:
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enum AG903_DSP_SCALING_ENUM{
141: AG903_DSP_SCALING_POINT_SAMPLING = 0 ,
142: AG903_DSP_SCALING_BILINEAR ,
143: };
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enum AG903_DSP_INT_BLANK_TIMING_ENUM{
149: AG903_DSP_INT_START_OF_VBLANK = 0 ,
150: AG903_DSP_INT_END_OF_VBLANK ,
151: };
152:
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enum AG903_DSP_INT_LINE_TIMING_ENUM{
157: AG903_DSP_INT_START_OF_LINE = 0 ,
158: AG903_DSP_INT_END_OF_LINE ,
159: };
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enum AG903_DSP_EVENT_ENUM{
165: AG903_DSP_EVENT_VT = 0 ,
166: AG903_DSP_EVENT_HRZ ,
167: };
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enum AG903_DSP_TRG_HRZ_TIMING_ENUM{
173: AG903_DSP_TRG_HRZ_START_OF_LINE = 0 ,
174: AG903_DSP_TRG_HRZ_END_OF_LINE ,
175: };
176:
180:
enum AG903_DSP_TRG_VT_TIMING_ENUM{
181: AG903_DSP_TRG_VT_START_OF_VBLANK = 0 ,
182: AG903_DSP_TRG_VT_START_OF_VSYNC ,
183: AG903_DSP_TRG_VT_END_OF_VSYNC ,
184: AG903_DSP_TRG_VT_END_OF_VBLANK ,
185: };
186:
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enum AG903_DSP_EXSYNC_ENUM{
191: AG903_DSP_EXSYNC_NONE = 0 ,
192: AG903_DSP_EXSYNC_OTHER_DSP ,
193: AG903_DSP_EXSYNC_EXTSYNC0 = 4 ,
194: AG903_DSP_EXSYNC_EXTSYNC1 ,
195: AG903_DSP_EXSYNC_VSYNC0 ,
196: AG903_DSP_EXSYNC_VSYNC1 ,
197: AG903_DSP_EXSYNC_DIGITAL_VSYNC0 ,
198: AG903_DSP_EXSYNC_DIGITAL_VSYNC1 ,
199: AG903_DSP_EXSYNC_DIGITAL_VSYNC2 ,
200: AG903_DSP_EXSYNC_DIGITAL_VSYNC3 ,
201: AG903_DSP_EXSYNC_ANALOG_VSYNC0 ,
202: AG903_DSP_EXSYNC_ANALOG_VSYNC1 ,
203: AG903_DSP_EXSYNC_ANALOG_VSYNC2 ,
204: AG903_DSP_EXSYNC_ANALOG_VSYNC3 ,
205: AG903_DSP_EXSYNC_TIMR0 ,
206: AG903_DSP_EXSYNC_TIMR1 ,
207: AG903_DSP_EXSYNC_TIMR2 ,
208: AG903_DSP_EXSYNC_TIMR3 ,
209: AG903_DSP_EXSYNC_TIMR4 ,
210: AG903_DSP_EXSYNC_TIMR5 ,
211: AG903_DSP_EXSYNC_TIMR6 ,
212: AG903_DSP_EXSYNC_TIMR7 ,
213: };
214:
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enum AG903_DSP_DMA_ENUM{
219: AG903_DSP_DMA_NONE = 0 ,
220: AG903_DSP_DMA_END_OF_VBLANK1 = 3 ,
221: AG903_DSP_DMA_START_OF_VBLANK ,
222: AG903_DSP_DMA_START_OF_VSYNC ,
223: AG903_DSP_DMA_END_OF_VSYNC ,
224: AG903_DSP_DMA_END_OF_VBLANK2 ,
225: };
226:
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enum AG903_DSP_STAT_ENUM{
231: AG903_DSP_STAT_STOP = 0 ,
232: AG903_DSP_STAT_RUN ,
233: };
234:
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enum AG903_DSP_SIGNAL_ENUM{
239: AG903_DSP_SIGNAL_ENABLE = 0 ,
240: AG903_DSP_SIGNAL_DISABLE ,
241: };
242:
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enum AG903_VOD0_PORTSEL_ENUM{
247: AG903_VOD0_PORTSEL_LVCMOS24 = 0 ,
248: AG903_VOD0_PORTSEL_LVCMOS16 ,
249: AG903_VOD0_PORTSEL_LVCMOS8 ,
250: AG903_VOD0_PORTSEL_LVDS_SINGLE ,
251: };
252:
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enum AG903_VOD1_PORTSEL_ENUM{
257: AG903_VOD1_PORTSEL_LVDS_DUAL = 0 ,
258: AG903_VOD1_PORTSEL_LVCMOS8 = 2 ,
259: AG903_VOD1_PORTSEL_LVDS_SINGLE ,
260: };
261:
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enum AG903_VOD_DOTCLK_CHANGE_ENUM{
266: AG903_VOD_DOTCLK_CHANGE_RISE = 0 ,
267: AG903_VOD_DOTCLK_CHANGE_FALL ,
268: };
269:
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enum AG903_VOD_DOTCLK_LATCH_ENUM{
277: AG903_VOD_DOTCLK_LATCH_FALL = 0 ,
278: AG903_VOD_DOTCLK_LATCH_RISE ,
279: };
280:
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enum AG903_VOD_MOD_YUV_ENUM{
285: AG903_VOD_MOD_YUV_BT601 = 0 ,
286: AG903_VOD_MOD_YUV_BT709 ,
287: };
288:
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enum AG903_VOD_PDX_ENUM{
293: AG903_VOD_PDX_PWRDOWN = 0 ,
294: AG903_VOD_PDX_NORMAL ,
295: };
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enum AG903_VOD_PM_ENUM{
301: AG903_VOD_PM_AUTO = 0 ,
302: AG903_VOD_PM_MANUAL ,
303: };
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enum AG903_VOD_FR_ENUM{
309: AG903_VOD_FR_8_16MHZ = 0 ,
310: AG903_VOD_FR_16_32MHZ ,
311: AG903_VOD_FR_32_54MHZ ,
312: AG903_VOD_FR_54_100MHZ ,
313: };
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enum AG903_VOD_BPWR_UNIT_ENUM{
319: AG903_VOD_BPWR_UNIT_FRAME = 0 ,
320: AG903_VOD_BPWR_UNIT_SCLK ,
321: };
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enum AG903_VOD_VODSTAT_ENUM{
327: AG903_VOD_VODSTAT_STOP = 0 ,
328: AG903_VOD_VODSTAT_INIT ,
329: AG903_VOD_VODSTAT_WAIT_DCLK ,
330: AG903_VOD_VODSTAT_PPWRON ,
331: AG903_VOD_VODSTAT_BPWRON ,
332: AG903_VOD_VODSTAT_BLGTON ,
333: AG903_VOD_VODSTAT_IDLE = 8 ,
334: AG903_VOD_VODSTAT_WAIT_SYNC = 10,
335: AG903_VOD_VODSTAT_BLGTOFF ,
336: AG903_VOD_VODSTAT_BPWROFF ,
337: AG903_VOD_VODSTAT_PPWROFF ,
338: AG903_VOD_VODSTAT_WAIT_FIFO ,
339: AG903_VOD_VODSTAT_WAIT_DSPSTOP ,
340: };
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typedef uint32_t
AG903_DSPMgrHandle;
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typedef struct _AG903_DSPMgrSyncParam {
355:
356: uint32_t rgbde_sel;
357: uint32_t vsync_polarity;
358: uint32_t field_hsync_polarity;
359: uint32_t hrz_pulsewidth;
360: uint32_t hrz_backporch;
361: uint32_t hrz_frontporch;
362: uint32_t vt_pulsewidth;
363: uint32_t odd_frontporch_plus1;
364: uint32_t odd_backporch_plus1;
365: uint32_t even_frontporch_plus1;
366: uint32_t even_backporch_plus1;
367: uint32_t vt_backporch;
368: uint32_t vt_frontporch;
369:
370: }
AG903_DSPMgrSyncParam;
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typedef struct _AG903_DSPMgrCtrlParam {
377:
378: uint32_t ip_sel;
379: uint32_t hrz_framesize;
380: uint32_t vt_framesize;
381:
AG903_DSPMgrSyncParam *syncparam;
382:
383: }
AG903_DSPMgrCtrlParam;
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typedef struct _AG903_DSPMgrWindowParam {
390:
391: uint32_t update_timing;
392: uint32_t background;
393: uint32_t num_config;
394: uint32_t num_attr;
395: uint32_t window_attr_base;
396: uint32_t window_attr_update;
397: uint32_t palette_update;
398:
399: }
AG903_DSPMgrWindowParam;
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401:
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typedef struct _AG903_DSPMgrIntParam {
406:
407: uint32_t bmureq_timing;
408: uint32_t int_line_no;
409: uint32_t int_framecount;
410: uint32_t int_hrz_line;
411: uint32_t int_vt_blank;
412: uint32_t trigger_out;
413: uint32_t trigger_hrz;
414: uint32_t trigger_vt;
415: uint32_t mask_vt_blank;
416: uint32_t mask_hrz_line;
417: uint32_t mask_dspoff;
418: uint32_t mask_error;
419:
420: }
AG903_DSPMgrIntParam;
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typedef struct _AG903_DSPMgrIntStat {
426:
427: uint32_t int_vt_blank;
428: uint32_t int_hrz_line;
429: uint32_t int_dspoff;
430: uint32_t dreq;
431: uint32_t clr_vt_blank;
432: uint32_t clr_hrz_line;
433: uint32_t clr_dspoff;
434:
435: }
AG903_DSPMgrIntStat;
436:
437:
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typedef struct _AG903_DSPMgrStat {
442:
443: uint32_t ctrl_status;
444: uint32_t work_pix;
445: uint32_t hrz_status;
446: uint32_t work_line;
447: uint32_t vt_status;
448: uint32_t frameconut;
449: uint32_t err_line;
450: uint32_t err_ue;
451: uint32_t err_le;
452: uint32_t err_pe;
453: uint32_t errclr_line;
454: uint32_t errclr_ue;
455: uint32_t errclr_le;
456: uint32_t errclr_pe;
457:
458: }
AG903_DSPMgrStat;
459:
460:
464:
typedef struct _AG903_DSPMgrWinAttribute {
465:
466: uint16_t position_x;
467: uint16_t position_y;
468: uint16_t destination_width;
469: uint16_t destination_height;
470: uint32_t framebuffer_base;
471: uint16_t source_width;
472: uint16_t source_height;
473: uint32_t hrz_size;
474: uint8_t transparent_color_b;
475: uint8_t transparent_color_g;
476: uint8_t transparent_color_r;
477: uint8_t transparent_color_a;
478: uint32_t pallet_base;
479:
480:
481:
struct {
482: uint32_t valid :1;
483: uint32_t biliner :1;
484: uint32_t hrz_flip :1;
485: uint32_t vt_flip :1;
486: uint32_t swap_1bit :1;
487: uint32_t swap_4bit :1;
488: uint32_t swap_half :1;
489: uint32_t swap_word :1;
490: uint32_t default_alpha :8;
491: uint32_t framebuffer_format :4;
492: uint32_t pallet_format :3;
493: uint32_t :1;
494: uint32_t transparent_en_b :1;
495: uint32_t transparent_en_g :1;
496: uint32_t transparent_en_r :1;
497: uint32_t transparent_en_a :1;
498: uint32_t transparent_en :1;
499: }conf;
500:
501: }
AG903_DSPMgrWinAttribute;
502:
503:
507:
typedef struct _AG903_DSPMgrExSyncParam {
508:
509: uint32_t sync_sel;
510: uint32_t delay_ctrl_en;
511: uint32_t ip_sel;
512: uint32_t vsync_polarity;
513: uint32_t field_hsync_polarity;
514: uint32_t sync_mask_en;
515:
516: }
AG903_DSPMgrExSyncParam;
517:
518:
521:
typedef struct _AG903_DSPMgrLutParam {
522:
523:
524:
struct {
525: uint8_t r0;
526: uint8_t r1;
527: uint8_t r2;
528: uint8_t r3;
529: }LUTR[
AG903_DSP_LUT_NUM];
530:
531:
struct {
532: uint8_t g0;
533: uint8_t g1;
534: uint8_t g2;
535: uint8_t g3;
536: }LUTG[
AG903_DSP_LUT_NUM];
537:
538:
struct {
539: uint8_t b0;
540: uint8_t b1;
541: uint8_t b2;
542: uint8_t b3;
543: }LUTB[
AG903_DSP_LUT_NUM];
544:
545: }
AG903_DSPMgrLutParam;
546:
547:
550:
typedef struct _AG903_DSPMgrDithParam {
551:
552:
553:
struct {
554: uint32_t x0;
555: uint32_t y0;
556: uint32_t x1;
557: uint32_t y1;
558: }DITHAREA[
AG903_DSP_DITHAREA_NUM];
559:
560: }
AG903_DSPMgrDithParam;
561:
562:
565:
typedef struct _AG903_DSPMgrCDParam {
566:
567: uint32_t colordetect_en_b;
568: uint32_t colordetect_en_g;
569: uint32_t colordetect_en_r;
570: uint32_t colordetect_en_a;
571: uint32_t colordetect_color_b;
572: uint32_t colordetect_color_g;
573: uint32_t colordetect_color_r;
574: uint32_t colordetect_color_a;
575:
576: }
AG903_DSPMgrCDParam;
577:
578:
582:
typedef struct _AG903_DSPMgrCMOSParam {
583:
584: uint32_t rgbde_polarity;
585: uint32_t vsync_polarity;
586: uint32_t hsync_polarity;
587: uint32_t field_polarity;
588: uint32_t colordetect_polarity;
589: uint32_t rgbde_en;
590: uint32_t vsync_en;
591: uint32_t hsync_en;
592: uint32_t field_en;
593: uint32_t colordetect_en;
594: uint32_t pixeldata_en;
595: uint32_t dotclk_polarity;
596: uint32_t code_en;
597: uint32_t yuv_mode;
598:
599: }
AG903_DSPMgrCMOSParam;
600:
601:
605:
typedef struct _AG903_DSPMgrLVDSParam {
606:
607: uint32_t rgbde_polarity;
608: uint32_t vsync_polarity;
609: uint32_t hsync_polarity;
610: uint32_t field_polarity;
611: uint32_t colordetect_polarity;
612: uint32_t rgbde_en;
613: uint32_t vsync_en;
614: uint32_t hsync_en;
615: uint32_t field_en;
616: uint32_t colordetect_en;
617: uint32_t pixeldata_en;
618: uint32_t format;
619: uint32_t ctrl0;
620: uint32_t ctrl1;
621: uint32_t freq_range;
622: uint32_t auto_powermanage;
623: uint32_t macro_power;
624:
625: }
AG903_DSPMgrLVDSParam;
626:
627:
631:
typedef struct _AG903_DSPMgrBPwrModeParam {
632:
633: uint32_t backlight_en;
634: uint32_t cnt_unit;
635: uint32_t panel_pwroncnt;
636: uint32_t backlight_pwroncnt;
637: uint32_t backlight_oncnt;
638: uint32_t panel_pwroffcnt;
639: uint32_t backlight_pwroffcnt;
640: uint32_t backlight_offcnt;
641: uint32_t pwm_period;
642: uint32_t pwm_cnt;
643:
644: }
AG903_DSPMgrBPwrModeParam;
645:
646:
647: int32_t
AG903_DSPMgrInit(
void);
648: int32_t
AG903_DSPMgrGetHandle(uint8_t ch,
AG903_DSPMgrHandle **handle);
649: int32_t
AG903_DSPMgrReleaseHandle(
AG903_DSPMgrHandle *handle);
650: int32_t
AG903_DSPMgrCheckStopped(
AG903_DSPMgrHandle *handle);
651: int32_t
AG903_DSPMgrEnable(
AG903_DSPMgrHandle *handle);
652: int32_t
AG903_DSPMgrDisable(
AG903_DSPMgrHandle *handle);
653: int32_t
AG903_DSPMgrGetCtrlParam(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrCtrlParam *param);
654: int32_t
AG903_DSPMgrSetWindowParam(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrWindowParam *param);
655: int32_t
AG903_DSPMgrSetAttributeList(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrWindowParam *param);
656: int32_t
AG903_DSPMgrSetIntParam(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrIntParam *param);
657: int32_t
AG903_DSPMgrSetIntMask(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrIntParam *param);
658: int32_t
AG903_DSPMgrGetIntStat(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrIntStat *stat);
659: int32_t
AG903_DSPMgrClearIntStat(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrIntStat *stat);
660: int32_t
AG903_DSPMgrGetStat(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrStat *stat);
661: int32_t
AG903_DSPMgrClearStat(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrStat *stat);
662:
665: int32_t
AG903_DSPMgrGetAttribute(
AG903_DSPMgrHandle *handle, uint8_t listno,
AG903_DSPMgrWinAttribute **attr);
666: int32_t
AG903_DSPMgrSetAttribute(
AG903_DSPMgrHandle *handle, uint8_t listno);
667:
670: int32_t
AG903_DSPMgrSetExSyncParam(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrExSyncParam *param);
671: int32_t
AG903_DSPMgrSetLutParam(
AG903_DSPMgrHandle *handle, _Bool en,
AG903_DSPMgrLutParam *param);
672: int32_t
AG903_DSPMgrSetDithParam(
AG903_DSPMgrHandle *handle, _Bool en,
AG903_DSPMgrDithParam *param);
673: int32_t
AG903_DSPMgrSetCDParam(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrCDParam *param);
674: int32_t
AG903_DSPMgrSetDMAReq(
AG903_DSPMgrHandle *handle, uint8_t req);
675:
678: int32_t
AG903_DSPMgrGetPortSel(
AG903_DSPMgrHandle *handle, uint8_t *sel);
679: int32_t
AG903_DSPMgrSetPortSel(
AG903_DSPMgrHandle *handle, uint8_t sel);
680: int32_t
AG903_DSPMgrSetCMOSParam(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrCtrlParam *ctrl,
AG903_DSPMgrCMOSParam *param);
681: int32_t
AG903_DSPMgrSetLVDSParam(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrCtrlParam *ctrl,
AG903_DSPMgrLVDSParam *param);
682: int32_t
AG903_DSPMgrSetBPwrModeParam(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrBPwrModeParam *param);
683: int32_t
AG903_DSPMgrGetBPwrModeParam(
AG903_DSPMgrHandle *handle,
AG903_DSPMgrBPwrModeParam *param);
684:
685:
686:
687:
#ifdef __cplusplus
688: }
689:
#endif
690:
691:
#endif