AG903ライブラリリファレンス
Body Source
AG903_sscreg.h
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1: 8: 9: 13: 14:
#ifndef
_AG903_SSC_REGMAP_H_ 15:
#define
_AG903_SSC_REGMAP_H_ 16: 17: 18:
#include
"AG903_regmap.h" 19: 20:
#ifndef
__I
21: 22:
#define
__I
volatile
const
23:
#endif
24:
#ifndef
__O
25: 26:
#define
__O
volatile
27:
#endif
28:
#ifndef
__IO
29: 30:
#define
__IO
volatile
31:
#endif
32: 33: 34:
typedef
struct
{ 35: 36:
union
{ 37:
__I
uint32_t REVISION; 38: }; 39: 40:
union
{ 41:
__I
uint32_t READTEST; 42: }; 43: 44:
union
{ 45:
__IO
uint32_t WRITETEST; 46: }; 47: 48:
union
{ 49:
__IO
uint32_t MODE_STATUS; 50: 51:
struct
{ 52:
__I
uint32_t BOOTMODE : 4; 53:
__I
uint32_t BOOTTEST : 4; 54:
__IO
uint32_t WDTCA5 : 1; 55:
__IO
uint32_t WDTGPP : 1; 56:
__IO
uint32_t WDTPIN : 1; 57:
__IO
uint32_t INITPIN : 1; 58: } MODE_STATUS_bits; 59: }; 60: 61:
union
{ 62:
__I
uint32_t IRQ_STATUS_LOWER; 63: }; 64: 65:
union
{ 66:
__I
uint32_t IRQ_STATUS_UPPER; 67: }; 68: 69:
__I
uint32_t RESERVED1[2]; 70: 71:
union
{ 72:
__I
uint32_t IRQ_BUS_STATUS; 73: 74:
struct
{ 75:
__I
uint32_t IRQBUSSTATUS : 8; 76: } IRQ_BUS_STATUS_bits; 77: }; 78: 79:
union
{ 80:
__IO
uint32_t IRQ_BUS_ENABLE; 81: 82:
struct
{ 83:
__IO
uint32_t IRQBUSENABLE : 8; 84: } IRQ_BUS_ENABLE_bits; 85: }; 86: 87:
__I
uint32_t RESERVED2[2]; 88: 89:
union
{ 90:
__I
uint32_t INT_STATUS_LOWER; 91: }; 92: 93:
union
{ 94:
__I
uint32_t INT_STATUS_MIDDLE; 95: }; 96: 97:
union
{ 98:
__I
uint32_t INT_STATUS_UPPER; 99: }; 100: 101:
__I
uint32_t RESERVED3[1]; 102: 103:
union
{ 104:
__IO
uint32_t INT0_ENABLE_LOWER; 105: }; 106: 107:
union
{ 108:
__IO
uint32_t INT0_ENABLE_MIDDLE; 109: }; 110: 111:
union
{ 112:
__IO
uint32_t INT0_ENABLE_UPPER; 113: }; 114: 115:
__I
uint32_t RESERVED4[1]; 116: 117:
union
{ 118:
__IO
uint32_t INT1_ENABLE_LOWER; 119: }; 120: 121:
union
{ 122:
__IO
uint32_t INT1_ENABLE_MIDDLE; 123: }; 124: 125:
union
{ 126:
__IO
uint32_t INT1_ENABLE_UPPER; 127: }; 128: 129:
__I
uint32_t RESERVED5[1]; 130: 131:
union
{ 132:
__IO
uint32_t INT2_ENABLE_LOWER; 133: }; 134: 135:
union
{ 136:
__IO
uint32_t INT2_ENABLE_MIDDLE; 137: }; 138: 139:
union
{ 140:
__IO
uint32_t INT2_ENABLE_UPPER; 141: }; 142: 143:
__I
uint32_t RESERVED6[1]; 144: 145:
union
{ 146:
__IO
uint32_t INT3_ENABLE_LOWER; 147: }; 148: 149:
union
{ 150:
__IO
uint32_t INT3_ENABLE_MIDDLE; 151: }; 152: 153:
union
{ 154:
__IO
uint32_t INT3_ENABLE_UPPER; 155: }; 156: 157:
__I
uint32_t RESERVED7[1]; 158: 159:
union
{ 160:
__IO
uint32_t CLKDUTY_GFX; 161: 162:
struct
{ 163:
__IO
uint32_t DUTY : 8; 164:
__IO
uint32_t VSON : 1; 165: } CLKDUTY_GFX_bits; 166: }; 167: 168:
union
{ 169:
__IO
uint32_t CLKDUTY_GVD; 170: 171:
struct
{ 172:
__IO
uint32_t DUTY : 8; 173: } CLKDUTY_GVD_bits; 174: }; 175: 176:
__I
uint32_t RESERVED8[10]; 177: 178:
union
{ 179:
__IO
uint32_t WDTOUT_INTMODE; 180: 181:
struct
{ 182:
__IO
uint32_t LEVEL : 1; 183: } WDTOUT_INTMODE_bits; 184: }; 185: 186:
union
{ 187:
__O
uint32_t WDTOUT_INTCLEAR; 188: 189:
struct
{ 190:
__O
uint32_t CLEAR : 1; 191: } WDTOUT_INTCLEAR_bits; 192: }; 193: 194:
union
{ 195:
__IO
uint32_t WDTOUT_SETUP; 196: 197:
struct
{ 198:
__IO
uint32_t OUT : 1; 199:
__IO
uint32_t OD : 1; 200:
__IO
uint32_t
WDT
: 1; 201:
__IO
uint32_t INIT : 1; 202: } WDTOUT_SETUP_bits; 203: }; 204: 205:
__I
uint32_t RESERVED9[1]; 206: 207:
union
{ 208:
__IO
uint32_t PIN_FUNC0; 209: 210:
struct
{ 211:
__IO
uint32_t FUNC0 : 2; 212:
__IO
uint32_t FUNC1 : 2; 213:
__IO
uint32_t FUNC2 : 2; 214:
__IO
uint32_t FUNC3 : 2; 215:
__IO
uint32_t FUNC4 : 2; 216:
__IO
uint32_t FUNC5 : 2; 217:
__IO
uint32_t FUNC6 : 2; 218:
__IO
uint32_t FUNC7 : 2; 219:
__IO
uint32_t FUNC8 : 2; 220:
__IO
uint32_t FUNC9 : 2; 221:
__IO
uint32_t FUNC10 : 2; 222:
__IO
uint32_t FUNC11 : 2; 223:
__IO
uint32_t FUNC12 : 2; 224:
__IO
uint32_t FUNC13 : 2; 225:
__IO
uint32_t FUNC14 : 2; 226:
__IO
uint32_t FUNC15 : 2; 227: } PIN_FUNC0_bits; 228: }; 229: 230:
union
{ 231:
__IO
uint32_t PIN_FUNC1; 232: 233:
struct
{ 234:
__IO
uint32_t FUNC16 : 2; 235:
__IO
uint32_t FUNC17 : 2; 236:
__IO
uint32_t FUNC18 : 2; 237:
__IO
uint32_t FUNC19 : 2; 238:
__IO
uint32_t FUNC20 : 2; 239:
__IO
uint32_t FUNC21 : 2; 240:
__IO
uint32_t FUNC22 : 2; 241:
__IO
uint32_t FUNC23 : 2; 242:
__IO
uint32_t FUNC24 : 2; 243:
__IO
uint32_t FUNC25 : 2; 244:
__IO
uint32_t FUNC26 : 2; 245:
__IO
uint32_t FUNC27 : 2; 246:
__IO
uint32_t FUNC28 : 2; 247:
__IO
uint32_t FUNC29 : 2; 248:
__IO
uint32_t FUNC30 : 2; 249:
__IO
uint32_t FUNC31 : 2; 250: } PIN_FUNC1_bits; 251: }; 252: 253:
union
{ 254:
__IO
uint32_t PIN_SETUP_INDEX; 255: 256:
struct
{ 257:
__IO
uint32_t INDEX : 8; 258: } PIN_SETUP_INDEX_bits; 259: }; 260: 261:
union
{ 262:
__IO
uint32_t PIN_SETUP_DATA; 263: 264:
struct
{ 265:
__IO
uint32_t SETUP : 8; 266: } PIN_SETUP_DATA_bits; 267: }; 268: 269:
union
{ 270:
__IO
uint32_t PIN_GPIO_ENABLE[4]; 271: }; 272: 273:
union
{ 274:
__IO
uint32_t PIN_GPIO_PIN_PU[4]; 275: }; 276: 277:
union
{ 278:
__IO
uint32_t PIN_GPIO_PIN_PD[4]; 279: }; 280: 281:
union
{ 282:
__IO
uint32_t CA5_RUN_SETUP; 283: 284:
struct
{ 285:
__IO
uint32_t GCLK : 1; 286:
__IO
uint32_t RESET : 1; 287: uint32_t : 2; 288:
__IO
uint32_t VINITHI : 1; 289: } CA5_RUN_SETUP_bits; 290: }; 291: 292:
union
{ 293:
__O
uint32_t CA5_RUN_CTRL; 294: 295:
struct
{ 296: uint32_t : 16; 297:
__O
uint32_t CLREV : 1; 298: } CA5_RUN_CTRL_bits; 299: }; 300: 301:
union
{ 302:
__IO
uint32_t CA5_RUN_STATUS; 303: 304:
struct
{ 305:
__I
uint32_t GCLK : 1; 306:
__I
uint32_t RESET : 1; 307: uint32_t : 6; 308:
__I
uint32_t WFE : 1; 309: uint32_t : 3; 310:
__I
uint32_t WFI : 1; 311: uint32_t : 3; 312:
__IO
uint32_t EVENTO : 1; 313: } CA5_RUN_STATUS_bits; 314: }; 315: 316:
union
{ 317:
__IO
uint32_t CA5_ACP_SETUP; 318: 319:
struct
{ 320: uint32_t : 29; 321:
__IO
uint32_t ACPADDR : 3; 322: } CA5_ACP_SETUP_bits; 323: }; 324: 325:
union
{ 326:
__IO
uint32_t DMA_SELECT0; 327: 328:
struct
{ 329:
__IO
uint32_t DMASELECT0 : 8; 330:
__IO
uint32_t DMASELECT1 : 8; 331:
__IO
uint32_t DMASELECT2 : 8; 332:
__IO
uint32_t DMASELECT3 : 8; 333: } DMA_SELECT0_bits; 334: }; 335: 336:
union
{ 337:
__IO
uint32_t DMA_SELECT1; 338: 339:
struct
{ 340:
__IO
uint32_t DMASELECT4 : 8; 341:
__IO
uint32_t DMASELECT5 : 8; 342:
__IO
uint32_t DMASELECT6 : 8; 343:
__IO
uint32_t DMASELECT7 : 8; 344: } DMA_SELECT1_bits; 345: }; 346: 347:
union
{ 348:
__IO
uint32_t DMA_SELECT2; 349: 350:
struct
{ 351:
__IO
uint32_t DMASELECT8 : 8; 352:
__IO
uint32_t DMASELECT9 : 8; 353:
__IO
uint32_t DMASELECT10 : 8; 354:
__IO
uint32_t DMASELECT11 : 8; 355: } DMA_SELECT2_bits; 356: }; 357: 358:
union
{ 359:
__IO
uint32_t DMA_SELECT3; 360: 361:
struct
{ 362:
__IO
uint32_t DMASELECT12 : 8; 363:
__IO
uint32_t DMASELECT13 : 8; 364:
__IO
uint32_t DMASELECT14 : 8; 365:
__IO
uint32_t DMASELECT15 : 8; 366: } DMA_SELECT3_bits; 367: }; 368: 369:
union
{ 370:
__IO
uint32_t DMA_SELECT_PBD; 371: 372:
struct
{ 373:
__IO
uint32_t DMASELECT : 8; 374: } DMA_SELECT_PBD_bits; 375: }; 376: 377:
union
{ 378:
__IO
uint32_t DSP_SETUP; 379: 380:
struct
{ 381:
__IO
uint32_t VSYNC0_DIR : 1; 382:
__IO
uint32_t FIELD0_DIR : 1; 383:
__IO
uint32_t DOT0_DIR : 1; 384: uint32_t : 1; 385:
__IO
uint32_t VSYNC1_DIR : 1; 386:
__IO
uint32_t FIELD1_DIR : 1; 387:
__IO
uint32_t DOT1_DIR : 1; 388: } DSP_SETUP_bits; 389: }; 390: 391:
__I
uint32_t RESERVED10[2]; 392: 393:
union
{ 394:
__IO
uint32_t TICK0_SETUP; 395: 396:
struct
{ 397:
__IO
uint32_t DIVNUM : 24; 398:
__IO
uint32_t CLKSEL : 4; 399: } TICK0_SETUP_bits; 400: }; 401: 402:
union
{ 403:
__IO
uint32_t TICK1_SETUP; 404: 405:
struct
{ 406:
__IO
uint32_t DIVNUM : 24; 407:
__IO
uint32_t CLKSEL : 4; 408: } TICK1_SETUP_bits; 409: }; 410: 411:
union
{ 412:
__IO
uint32_t TIM_SETUP; 413: 414:
struct
{ 415:
__IO
uint32_t TIM_DIR : 4; 416: } TIM_SETUP_bits; 417: }; 418: 419:
union
{ 420:
__IO
uint32_t SSP_SETUP; 421: 422:
struct
{ 423:
__IO
uint32_t SSP0_DIR : 1; 424:
__IO
uint32_t SSP0_MODE : 1; 425:
__IO
uint32_t SSP0_MCLK_DIR : 1; 426:
__IO
uint32_t SSP0_MCLK_DIV : 5; 427:
__IO
uint32_t SSP1_DIR : 1; 428:
__IO
uint32_t SSP1_MODE : 1; 429:
__IO
uint32_t SSP1_MCLK_DIR : 1; 430:
__IO
uint32_t SSP1_MCLK_DIV : 5; 431:
__IO
uint32_t SSP2_DIR : 1; 432:
__IO
uint32_t SSP2_MODE : 1; 433:
__IO
uint32_t SSP2_MCLK_DIR : 1; 434:
__IO
uint32_t SSP2_MCLK_DIV : 5; 435:
__IO
uint32_t SSP3_DIR : 1; 436:
__IO
uint32_t SSP3_MODE : 1; 437:
__IO
uint32_t SSP3_MCLK_DIR : 1; 438:
__IO
uint32_t SSP3_MCLK_DIV : 5; 439: } SSP_SETUP_bits; 440: }; 441: 442:
union
{ 443:
__IO
uint32_t PBD_ADDRCHECK_START; 444: 445:
struct
{ 446: uint32_t : 2; 447:
__IO
uint32_t START_ADDR : 30; 448: } PBD_ADDRCHECK_START_bits; 449: }; 450: 451:
union
{ 452:
__IO
uint32_t PBD_ADDRCHECK_END; 453: 454:
struct
{ 455: uint32_t : 2; 456:
__IO
uint32_t END_ADDR : 30; 457: } PBD_ADDRCHECK_END_bits; 458: }; 459: 460:
union
{ 461:
__IO
uint32_t PBD_ADDRCHECK_ENABLE; 462: 463:
struct
{ 464:
__IO
uint32_t ENABLE : 1; 465: } PBD_ADDRCHECK_ENABLE_bits; 466: }; 467: 468:
union
{ 469:
__I
uint32_t PBD_ADDRCHECK_STATUS; 470: 471:
struct
{ 472:
__I
uint32_t STATUS : 1; 473: } PBD_ADDRCHECK_STATUS_bits; 474: }; 475: 476:
union
{ 477:
__I
uint32_t BMU_STATUS; 478: 479:
struct
{ 480:
__I
uint32_t SNKRDY : 4; 481:
__I
uint32_t SNKREQ : 4; 482:
__I
uint32_t SRCRDY : 11; 483: uint32_t : 1; 484:
__I
uint32_t SRCREQ : 11; 485: } BMU_STATUS_bits; 486: }; 487: 488:
union
{ 489:
__O
uint32_t BMU_CONTROL; 490: 491:
struct
{ 492:
__O
uint32_t CLR_SNK : 4; 493:
__O
uint32_t SET_SNK : 4; 494:
__O
uint32_t CLR_SRC : 11; 495: uint32_t : 1; 496:
__O
uint32_t SET_SRC : 11; 497: } BMU_CONTROL_bits; 498: }; 499: 500:
union
{ 501:
__I
uint32_t BMU_TRIG_STATUS; 502: 503:
struct
{ 504:
__I
uint32_t SNKRDY : 4; 505:
__I
uint32_t SNKREQ : 4; 506:
__I
uint32_t SRCRDY : 11; 507: uint32_t : 1; 508:
__I
uint32_t SRCREQ : 11; 509: } BMU_TRIG_STATUS_bits; 510: }; 511: 512:
union
{ 513:
__O
uint32_t BMU_TRIG_CLEAR; 514: 515:
struct
{ 516:
__O
uint32_t SNKRDY : 4; 517:
__O
uint32_t SNKREQ : 4; 518:
__O
uint32_t SRCRDY : 11; 519: uint32_t : 1; 520:
__O
uint32_t SRCREQ : 11; 521: } BMU_TRIG_CLEAR_bits; 522: }; 523: 524:
__I
uint32_t RESERVED11[26]; 525: 526:
union
{ 527:
__IO
uint32_t PORT_WAIT; 528: 529:
struct
{ 530:
__IO
uint32_t CYCLE : 16; 531: } PORT_WAIT_bits; 532: }; 533: 534:
union
{ 535:
__IO
uint32_t PBH_MODE; 536: 537:
struct
{ 538: uint32_t : 1; 539:
__IO
uint32_t WAIT : 1; 540: } PBH_MODE_bits; 541: }; 542: 543:
union
{ 544:
__IO
uint32_t TDM0_SETUP; 545: 546:
struct
{ 547:
__IO
uint32_t ST_RX : 1; 548:
__IO
uint32_t ST_TX : 1; 549:
__IO
uint32_t SCLK_N : 3; 550:
__IO
uint32_t TDM_N : 2; 551:
__IO
uint32_t DIR_TX : 1; 552:
__IO
uint32_t FS_RXERR : 1; 553:
__IO
uint32_t FS_DIST : 1; 554:
__IO
uint32_t FS_TXPW : 1; 555:
__IO
uint32_t FS_POL : 1; 556:
__IO
uint32_t SCLK_POL : 1; 557:
__IO
uint32_t TDM_EN : 1; 558: } TDM0_SETUP_bits; 559: }; 560: 561:
union
{ 562:
__IO
uint32_t TDM1_SETUP; 563: 564:
struct
{ 565:
__IO
uint32_t ST_RX : 1; 566:
__IO
uint32_t ST_TX : 1; 567:
__IO
uint32_t SCLK_N : 3; 568:
__IO
uint32_t TDM_N : 2; 569:
__IO
uint32_t DIR_TX : 1; 570:
__IO
uint32_t FS_RXERR : 1; 571:
__IO
uint32_t FS_DIST : 1; 572:
__IO
uint32_t FS_TXPW : 1; 573:
__IO
uint32_t FS_POL : 1; 574:
__IO
uint32_t SCLK_POL : 1; 575:
__IO
uint32_t TDM_EN : 1; 576: } TDM1_SETUP_bits; 577: }; 578: 579:
union
{ 580:
__IO
uint32_t TDM2_SETUP; 581: 582:
struct
{ 583:
__IO
uint32_t ST_RX : 1; 584:
__IO
uint32_t ST_TX : 1; 585:
__IO
uint32_t SCLK_N : 3; 586:
__IO
uint32_t TDM_N : 2; 587:
__IO
uint32_t DIR_TX : 1; 588:
__IO
uint32_t FS_RXERR : 1; 589:
__IO
uint32_t FS_DIST : 1; 590:
__IO
uint32_t FS_TXPW : 1; 591:
__IO
uint32_t FS_POL : 1; 592:
__IO
uint32_t SCLK_POL : 1; 593:
__IO
uint32_t TDM_EN : 1; 594: } TDM2_SETUP_bits; 595: }; 596: 597:
union
{ 598:
__IO
uint32_t TDM3_SETUP; 599: 600:
struct
{ 601:
__IO
uint32_t ST_RX : 1; 602:
__IO
uint32_t ST_TX : 1; 603:
__IO
uint32_t SCLK_N : 3; 604:
__IO
uint32_t TDM_N : 2; 605:
__IO
uint32_t DIR_TX : 1; 606:
__IO
uint32_t FS_RXERR : 1; 607:
__IO
uint32_t FS_DIST : 1; 608:
__IO
uint32_t FS_TXPW : 1; 609:
__IO
uint32_t FS_POL : 1; 610:
__IO
uint32_t SCLK_POL : 1; 611:
__IO
uint32_t TDM_EN : 1; 612: } TDM3_SETUP_bits; 613: }; 614: 615:
union
{ 616:
__IO
uint32_t USB_POWER_SETUP; 617: 618:
struct
{ 619:
__IO
uint32_t PWR_PROT_EN : 1; 620:
__IO
uint32_t PWR_INT_EN : 1; 621:
__IO
uint32_t PWR_MODE : 1; 622: } USB_POWER_SETUP_bits; 623: }; 624: 625:
union
{ 626:
__I
uint32_t USB_POWER_STATUS; 627: 628:
struct
{ 629:
__I
uint32_t PWR_PROT_STATE : 1; 630:
__I
uint32_t PWR_PROT_PIN : 1; 631:
__I
uint32_t VBUS_PIN : 1; 632: } USB_POWER_STATUS_bits; 633: }; 634: 635:
union
{ 636:
__O
uint32_t USB_POWER_CLEAR; 637: 638:
struct
{ 639:
__O
uint32_t PWR_PROT_CLR : 1; 640: } USB_POWER_CLEAR_bits; 641: }; 642: 643:
__I
uint32_t RESERVED12[1]; 644: 645:
union
{ 646:
__IO
uint32_t SD_POWER_SETUP; 647: 648:
struct
{ 649:
__IO
uint32_t PWR_PROT_EN : 1; 650:
__IO
uint32_t PWR_INT_EN : 1; 651: } SD_POWER_SETUP_bits; 652: }; 653: 654:
union
{ 655:
__I
uint32_t SD_POWER_STATUS; 656: 657:
struct
{ 658:
__I
uint32_t PWR_PROT_STATE : 1; 659:
__I
uint32_t PWR_PROT_PIN : 1; 660: } SD_POWER_STATUS_bits; 661: }; 662: 663:
union
{ 664:
__O
uint32_t SD_POWER_CLEAR; 665: 666:
struct
{ 667:
__O
uint32_t PWR_PROT_CLR : 1; 668: } SD_POWER_CLEAR_bits; 669: }; 670: 671:
__I
uint32_t RESERVED13[1]; 672: 673:
union
{ 674:
__IO
uint32_t VIDEOADC_SETUP; 675: 676:
struct
{ 677:
__IO
uint32_t GHO : 4; 678:
__IO
uint32_t CLHO : 4; 679:
__IO
uint32_t CTHO : 4; 680:
__IO
uint32_t DATEN : 4; 681:
__IO
uint32_t ACQEN : 4; 682:
__IO
uint32_t ACQCLR : 4; 683: } VIDEOADC_SETUP_bits; 684: }; 685: 686:
__I
uint32_t RESERVED14[1]; 687: 688:
union
{ 689:
__IO
uint32_t CVBSDEC_ADDR; 690: 691:
struct
{ 692:
__IO
uint32_t ADDR : 12; 693: uint32_t : 4; 694:
__IO
uint32_t CH : 2; 695: } CVBSDEC_ADDR_bits; 696: }; 697: 698:
union
{ 699:
__IO
uint32_t CVBSDEC_DATA; 700: 701:
struct
{ 702:
__IO
uint32_t DATA : 16; 703: } CVBSDEC_DATA_bits; 704: }; 705: 706:
union
{ 707:
__I
uint32_t VIDEOADC_MAXMIN[4]; 708: 709:
struct
{ 710:
__I
uint32_t MIN : 10; 711: uint32_t : 6; 712:
__I
uint32_t MAX : 10; 713: } VIDEOADC_MAXMIN_bits[4]; 714: }; 715: 716:
__I
uint32_t RESERVED15[8]; 717: 718:
union
{ 719:
__I
uint32_t SGI_STATUS; 720: }; 721: 722:
union
{ 723:
__O
uint32_t SGI_SET; 724: }; 725: 726:
union
{ 727:
__O
uint32_t SGI_CLEAR; 728: }; 729: 730:
__I
uint32_t RESERVED16[1]; 731: 732:
union
{ 733:
__IO
uint32_t CA5_JUMPADDR; 734: }; 735: 736:
__I
uint32_t RESERVED17[3]; 737: 738:
union
{ 739:
__IO
uint32_t COUNT64_LOWER; 740: }; 741: 742:
union
{ 743:
__IO
uint32_t COUNT64_UPPER; 744: }; 745: 746: 747: }
AG903_SSC_Type
; 748: 749:
#define
AG903_SSC
((
volatile
AG903_SSC_Type
*)
AG903_SSC_BASE
) 750: 751: 752:
#define
AG903_SSC_REVISION_REVISION_POS
0 753:
#define
AG903_SSC_REVISION_REVISION_MSK
(0xffffffffUL <<
AG903_SSC_REVISION_REVISION_POS
) 754: 755:
#define
AG903_SSC_READTEST_READTEST_POS
0 756:
#define
AG903_SSC_READTEST_READTEST_MSK
(0xffffffffUL <<
AG903_SSC_READTEST_READTEST_POS
) 757: 758:
#define
AG903_SSC_WRITETEST_WRITETEST_POS
0 759:
#define
AG903_SSC_WRITETEST_WRITETEST_MSK
(0xffffffffUL <<
AG903_SSC_WRITETEST_WRITETEST_POS
) 760: 761:
#define
AG903_SSC_MODE_STATUS_BOOTMODE_POS
0 762:
#define
AG903_SSC_MODE_STATUS_BOOTMODE_MSK
(0xfUL <<
AG903_SSC_MODE_STATUS_BOOTMODE_POS
) 763:
#define
AG903_SSC_MODE_STATUS_BOOTTEST_POS
4 764:
#define
AG903_SSC_MODE_STATUS_BOOTTEST_MSK
(0xfUL <<
AG903_SSC_MODE_STATUS_BOOTTEST_POS
) 765:
#define
AG903_SSC_MODE_STATUS_WDTCA5_POS
8 766:
#define
AG903_SSC_MODE_STATUS_WDTCA5_MSK
(0x1UL <<
AG903_SSC_MODE_STATUS_WDTCA5_POS
) 767:
#define
AG903_SSC_MODE_STATUS_WDTGPP_POS
9 768:
#define
AG903_SSC_MODE_STATUS_WDTGPP_MSK
(0x1UL <<
AG903_SSC_MODE_STATUS_WDTGPP_POS
) 769:
#define
AG903_SSC_MODE_STATUS_WDTPIN_POS
10 770:
#define
AG903_SSC_MODE_STATUS_WDTPIN_MSK
(0x1UL <<
AG903_SSC_MODE_STATUS_WDTPIN_POS
) 771:
#define
AG903_SSC_MODE_STATUS_INITPIN_POS
11 772:
#define
AG903_SSC_MODE_STATUS_INITPIN_MSK
(0x1UL <<
AG903_SSC_MODE_STATUS_INITPIN_POS
) 773: 774:
#define
AG903_SSC_IRQ_STATUS_LOWER_IRQSTATUS_POS
0 775:
#define
AG903_SSC_IRQ_STATUS_LOWER_IRQSTATUS_MSK
(0xffffffffUL <<
AG903_SSC_IRQ_STATUS_LOWER_IRQSTATUS_POS
) 776: 777:
#define
AG903_SSC_IRQ_STATUS_UPPER_IRQSTATUS_POS
0 778:
#define
AG903_SSC_IRQ_STATUS_UPPER_IRQSTATUS_MSK
(0xffffffffUL <<
AG903_SSC_IRQ_STATUS_UPPER_IRQSTATUS_POS
) 779: 780:
#define
AG903_SSC_IRQ_BUS_STATUS_IRQBUSSTATUS_POS
0 781:
#define
AG903_SSC_IRQ_BUS_STATUS_IRQBUSSTATUS_MSK
(0xffUL <<
AG903_SSC_IRQ_BUS_STATUS_IRQBUSSTATUS_POS
) 782: 783:
#define
AG903_SSC_IRQ_BUS_ENABLE_IRQBUSENABLE_POS
0 784:
#define
AG903_SSC_IRQ_BUS_ENABLE_IRQBUSENABLE_MSK
(0xffUL <<
AG903_SSC_IRQ_BUS_ENABLE_IRQBUSENABLE_POS
) 785: 786:
#define
AG903_SSC_INT_STATUS_LOWER_INTSTATUS_POS
0 787:
#define
AG903_SSC_INT_STATUS_LOWER_INTSTATUS_MSK
(0xffffffffUL <<
AG903_SSC_INT_STATUS_LOWER_INTSTATUS_POS
) 788: 789:
#define
AG903_SSC_INT_STATUS_MIDDLE_INTSTATUS_POS
0 790:
#define
AG903_SSC_INT_STATUS_MIDDLE_INTSTATUS_MSK
(0xffffffffUL <<
AG903_SSC_INT_STATUS_MIDDLE_INTSTATUS_POS
) 791: 792:
#define
AG903_SSC_INT_STATUS_UPPER_INTSTATUS_POS
0 793:
#define
AG903_SSC_INT_STATUS_UPPER_INTSTATUS_MSK
(0xffffffffUL <<
AG903_SSC_INT_STATUS_UPPER_INTSTATUS_POS
) 794: 795:
#define
AG903_SSC_INT0_ENABLE_LOWER_INTENABLE_POS
0 796:
#define
AG903_SSC_INT0_ENABLE_LOWER_INTENABLE_MSK
(0xffffffffUL <<
AG903_SSC_INT0_ENABLE_LOWER_INTENABLE_POS
) 797: 798:
#define
AG903_SSC_INT0_ENABLE_MIDDLE_INTENABLE_POS
0 799:
#define
AG903_SSC_INT0_ENABLE_MIDDLE_INTENABLE_MSK
(0xffffffffUL <<
AG903_SSC_INT0_ENABLE_MIDDLE_INTENABLE_POS
) 800: 801:
#define
AG903_SSC_INT0_ENABLE_UPPER_INTENABLE_POS
0 802:
#define
AG903_SSC_INT0_ENABLE_UPPER_INTENABLE_MSK
(0xffffffffUL <<
AG903_SSC_INT0_ENABLE_UPPER_INTENABLE_POS
) 803: 804:
#define
AG903_SSC_INT1_ENABLE_LOWER_INTENABLE_POS
0 805:
#define
AG903_SSC_INT1_ENABLE_LOWER_INTENABLE_MSK
(0xffffffffUL <<
AG903_SSC_INT1_ENABLE_LOWER_INTENABLE_POS
) 806: 807:
#define
AG903_SSC_INT1_ENABLE_MIDDLE_INTENABLE_POS
0 808:
#define
AG903_SSC_INT1_ENABLE_MIDDLE_INTENABLE_MSK
(0xffffffffUL <<
AG903_SSC_INT1_ENABLE_MIDDLE_INTENABLE_POS
) 809: 810:
#define
AG903_SSC_INT1_ENABLE_UPPER_INTENABLE_POS
0 811:
#define
AG903_SSC_INT1_ENABLE_UPPER_INTENABLE_MSK
(0xffffffffUL <<
AG903_SSC_INT1_ENABLE_UPPER_INTENABLE_POS
) 812: 813:
#define
AG903_SSC_INT2_ENABLE_LOWER_INTENABLE_POS
0 814:
#define
AG903_SSC_INT2_ENABLE_LOWER_INTENABLE_MSK
(0xffffffffUL <<
AG903_SSC_INT2_ENABLE_LOWER_INTENABLE_POS
) 815: 816:
#define
AG903_SSC_INT2_ENABLE_MIDDLE_INTENABLE_POS
0 817:
#define
AG903_SSC_INT2_ENABLE_MIDDLE_INTENABLE_MSK
(0xffffffffUL <<
AG903_SSC_INT2_ENABLE_MIDDLE_INTENABLE_POS
) 818: 819:
#define
AG903_SSC_INT2_ENABLE_UPPER_INTENABLE_POS
0 820:
#define
AG903_SSC_INT2_ENABLE_UPPER_INTENABLE_MSK
(0xffffffffUL <<
AG903_SSC_INT2_ENABLE_UPPER_INTENABLE_POS
) 821: 822:
#define
AG903_SSC_INT3_ENABLE_LOWER_INTENABLE_POS
0 823:
#define
AG903_SSC_INT3_ENABLE_LOWER_INTENABLE_MSK
(0xffffffffUL <<
AG903_SSC_INT3_ENABLE_LOWER_INTENABLE_POS
) 824: 825:
#define
AG903_SSC_INT3_ENABLE_MIDDLE_INTENABLE_POS
0 826:
#define
AG903_SSC_INT3_ENABLE_MIDDLE_INTENABLE_MSK
(0xffffffffUL <<
AG903_SSC_INT3_ENABLE_MIDDLE_INTENABLE_POS
) 827: 828:
#define
AG903_SSC_INT3_ENABLE_UPPER_INTENABLE_POS
0 829:
#define
AG903_SSC_INT3_ENABLE_UPPER_INTENABLE_MSK
(0xffffffffUL <<
AG903_SSC_INT3_ENABLE_UPPER_INTENABLE_POS
) 830: 831:
#define
AG903_SSC_CLKDUTY_GFX_DUTY_POS
0 832:
#define
AG903_SSC_CLKDUTY_GFX_DUTY_MSK
(0xffUL <<
AG903_SSC_CLKDUTY_GFX_DUTY_POS
) 833:
#define
AG903_SSC_CLKDUTY_GFX_VSON_POS
8 834:
#define
AG903_SSC_CLKDUTY_GFX_VSON_MSK
(0x1UL <<
AG903_SSC_CLKDUTY_GFX_VSON_POS
) 835: 836:
#define
AG903_SSC_CLKDUTY_GVD_DUTY_POS
0 837:
#define
AG903_SSC_CLKDUTY_GVD_DUTY_MSK
(0xffUL <<
AG903_SSC_CLKDUTY_GVD_DUTY_POS
) 838: 839:
#define
AG903_SSC_WDTOUT_INTMODE_LEVEL_POS
0 840:
#define
AG903_SSC_WDTOUT_INTMODE_LEVEL_MSK
(0x1UL <<
AG903_SSC_WDTOUT_INTMODE_LEVEL_POS
) 841: 842:
#define
AG903_SSC_WDTOUT_INTCLEAR_CLEAR_POS
0 843:
#define
AG903_SSC_WDTOUT_INTCLEAR_CLEAR_MSK
(0x1UL <<
AG903_SSC_WDTOUT_INTCLEAR_CLEAR_POS
) 844: 845:
#define
AG903_SSC_WDTOUT_SETUP_OUT_POS
0 846:
#define
AG903_SSC_WDTOUT_SETUP_OUT_MSK
(0x1UL <<
AG903_SSC_WDTOUT_SETUP_OUT_POS
) 847:
#define
AG903_SSC_WDTOUT_SETUP_OD_POS
1 848:
#define
AG903_SSC_WDTOUT_SETUP_OD_MSK
(0x1UL <<
AG903_SSC_WDTOUT_SETUP_OD_POS
) 849:
#define
AG903_SSC_WDTOUT_SETUP_WDT_POS
2 850:
#define
AG903_SSC_WDTOUT_SETUP_WDT_MSK
(0x1UL <<
AG903_SSC_WDTOUT_SETUP_WDT_POS
) 851:
#define
AG903_SSC_WDTOUT_SETUP_INIT_POS
3 852:
#define
AG903_SSC_WDTOUT_SETUP_INIT_MSK
(0x1UL <<
AG903_SSC_WDTOUT_SETUP_INIT_POS
) 853: 854:
#define
AG903_SSC_PIN_FUNC0_FUNC0_POS
0 855:
#define
AG903_SSC_PIN_FUNC0_FUNC0_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC0_POS
) 856:
#define
AG903_SSC_PIN_FUNC0_FUNC1_POS
2 857:
#define
AG903_SSC_PIN_FUNC0_FUNC1_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC1_POS
) 858:
#define
AG903_SSC_PIN_FUNC0_FUNC2_POS
4 859:
#define
AG903_SSC_PIN_FUNC0_FUNC2_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC2_POS
) 860:
#define
AG903_SSC_PIN_FUNC0_FUNC3_POS
6 861:
#define
AG903_SSC_PIN_FUNC0_FUNC3_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC3_POS
) 862:
#define
AG903_SSC_PIN_FUNC0_FUNC4_POS
8 863:
#define
AG903_SSC_PIN_FUNC0_FUNC4_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC4_POS
) 864:
#define
AG903_SSC_PIN_FUNC0_FUNC5_POS
10 865:
#define
AG903_SSC_PIN_FUNC0_FUNC5_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC5_POS
) 866:
#define
AG903_SSC_PIN_FUNC0_FUNC6_POS
12 867:
#define
AG903_SSC_PIN_FUNC0_FUNC6_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC6_POS
) 868:
#define
AG903_SSC_PIN_FUNC0_FUNC7_POS
14 869:
#define
AG903_SSC_PIN_FUNC0_FUNC7_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC7_POS
) 870:
#define
AG903_SSC_PIN_FUNC0_FUNC8_POS
16 871:
#define
AG903_SSC_PIN_FUNC0_FUNC8_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC8_POS
) 872:
#define
AG903_SSC_PIN_FUNC0_FUNC9_POS
18 873:
#define
AG903_SSC_PIN_FUNC0_FUNC9_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC9_POS
) 874:
#define
AG903_SSC_PIN_FUNC0_FUNC10_POS
20 875:
#define
AG903_SSC_PIN_FUNC0_FUNC10_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC10_POS
) 876:
#define
AG903_SSC_PIN_FUNC0_FUNC11_POS
22 877:
#define
AG903_SSC_PIN_FUNC0_FUNC11_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC11_POS
) 878:
#define
AG903_SSC_PIN_FUNC0_FUNC12_POS
24 879:
#define
AG903_SSC_PIN_FUNC0_FUNC12_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC12_POS
) 880:
#define
AG903_SSC_PIN_FUNC0_FUNC13_POS
26 881:
#define
AG903_SSC_PIN_FUNC0_FUNC13_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC13_POS
) 882:
#define
AG903_SSC_PIN_FUNC0_FUNC14_POS
28 883:
#define
AG903_SSC_PIN_FUNC0_FUNC14_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC14_POS
) 884:
#define
AG903_SSC_PIN_FUNC0_FUNC15_POS
30 885:
#define
AG903_SSC_PIN_FUNC0_FUNC15_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC0_FUNC15_POS
) 886: 887:
#define
AG903_SSC_PIN_FUNC1_FUNC16_POS
0 888:
#define
AG903_SSC_PIN_FUNC1_FUNC16_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC16_POS
) 889:
#define
AG903_SSC_PIN_FUNC1_FUNC17_POS
2 890:
#define
AG903_SSC_PIN_FUNC1_FUNC17_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC17_POS
) 891:
#define
AG903_SSC_PIN_FUNC1_FUNC18_POS
4 892:
#define
AG903_SSC_PIN_FUNC1_FUNC18_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC18_POS
) 893:
#define
AG903_SSC_PIN_FUNC1_FUNC19_POS
6 894:
#define
AG903_SSC_PIN_FUNC1_FUNC19_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC19_POS
) 895:
#define
AG903_SSC_PIN_FUNC1_FUNC20_POS
8 896:
#define
AG903_SSC_PIN_FUNC1_FUNC20_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC20_POS
) 897:
#define
AG903_SSC_PIN_FUNC1_FUNC21_POS
10 898:
#define
AG903_SSC_PIN_FUNC1_FUNC21_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC21_POS
) 899:
#define
AG903_SSC_PIN_FUNC1_FUNC22_POS
12 900:
#define
AG903_SSC_PIN_FUNC1_FUNC22_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC22_POS
) 901:
#define
AG903_SSC_PIN_FUNC1_FUNC23_POS
14 902:
#define
AG903_SSC_PIN_FUNC1_FUNC23_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC23_POS
) 903:
#define
AG903_SSC_PIN_FUNC1_FUNC24_POS
16 904:
#define
AG903_SSC_PIN_FUNC1_FUNC24_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC24_POS
) 905:
#define
AG903_SSC_PIN_FUNC1_FUNC25_POS
18 906:
#define
AG903_SSC_PIN_FUNC1_FUNC25_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC25_POS
) 907:
#define
AG903_SSC_PIN_FUNC1_FUNC26_POS
20 908:
#define
AG903_SSC_PIN_FUNC1_FUNC26_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC26_POS
) 909:
#define
AG903_SSC_PIN_FUNC1_FUNC27_POS
22 910:
#define
AG903_SSC_PIN_FUNC1_FUNC27_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC27_POS
) 911:
#define
AG903_SSC_PIN_FUNC1_FUNC28_POS
24 912:
#define
AG903_SSC_PIN_FUNC1_FUNC28_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC28_POS
) 913:
#define
AG903_SSC_PIN_FUNC1_FUNC29_POS
26 914:
#define
AG903_SSC_PIN_FUNC1_FUNC29_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC29_POS
) 915:
#define
AG903_SSC_PIN_FUNC1_FUNC30_POS
28 916:
#define
AG903_SSC_PIN_FUNC1_FUNC30_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC30_POS
) 917:
#define
AG903_SSC_PIN_FUNC1_FUNC31_POS
30 918:
#define
AG903_SSC_PIN_FUNC1_FUNC31_MSK
(0x3UL <<
AG903_SSC_PIN_FUNC1_FUNC31_POS
) 919: 920:
#define
AG903_SSC_PIN_SETUP_INDEX_INDEX_POS
0 921:
#define
AG903_SSC_PIN_SETUP_INDEX_INDEX_MSK
(0xffUL <<
AG903_SSC_PIN_SETUP_INDEX_INDEX_POS
) 922: 923:
#define
AG903_SSC_PIN_SETUP_DATA_SETUP_POS
0 924:
#define
AG903_SSC_PIN_SETUP_DATA_SETUP_MSK
(0xffUL <<
AG903_SSC_PIN_SETUP_DATA_SETUP_POS
) 925: 926:
#define
AG903_SSC_PIN_GPIO_ENABLE_GPIOENABLE_POS
0 927:
#define
AG903_SSC_PIN_GPIO_ENABLE_GPIOENABLE_MSK
(0xffffffffUL <<
AG903_SSC_PIN_GPIO_ENABLE_GPIOENABLE_POS
) 928: 929:
#define
AG903_SSC_PIN_GPIO_PIN_PU_GPIOPINPU_POS
0 930:
#define
AG903_SSC_PIN_GPIO_PIN_PU_GPIOPINPU_MSK
(0xffffffffUL <<
AG903_SSC_PIN_GPIO_PIN_PU_GPIOPINPU_POS
) 931: 932:
#define
AG903_SSC_PIN_GPIO_PIN_PD_GPIOPINPD_POS
0 933:
#define
AG903_SSC_PIN_GPIO_PIN_PD_GPIOPINPD_MSK
(0xffffffffUL <<
AG903_SSC_PIN_GPIO_PIN_PD_GPIOPINPD_POS
) 934: 935:
#define
AG903_SSC_CA5_RUN_SETUP_GCLK_POS
0 936:
#define
AG903_SSC_CA5_RUN_SETUP_GCLK_MSK
(0x1UL <<
AG903_SSC_CA5_RUN_SETUP_GCLK_POS
) 937:
#define
AG903_SSC_CA5_RUN_SETUP_RESET_POS
1 938:
#define
AG903_SSC_CA5_RUN_SETUP_RESET_MSK
(0x1UL <<
AG903_SSC_CA5_RUN_SETUP_RESET_POS
) 939:
#define
AG903_SSC_CA5_RUN_SETUP_VINITHI_POS
4 940:
#define
AG903_SSC_CA5_RUN_SETUP_VINITHI_MSK
(0x1UL <<
AG903_SSC_CA5_RUN_SETUP_VINITHI_POS
) 941: 942:
#define
AG903_SSC_CA5_RUN_CTRL_CLREV_POS
16 943:
#define
AG903_SSC_CA5_RUN_CTRL_CLREV_MSK
(0x1UL <<
AG903_SSC_CA5_RUN_CTRL_CLREV_POS
) 944: 945:
#define
AG903_SSC_CA5_RUN_STATUS_GCLK_POS
0 946:
#define
AG903_SSC_CA5_RUN_STATUS_GCLK_MSK
(0x1UL <<
AG903_SSC_CA5_RUN_STATUS_GCLK_POS
) 947:
#define
AG903_SSC_CA5_RUN_STATUS_RESET_POS
1 948:
#define
AG903_SSC_CA5_RUN_STATUS_RESET_MSK
(0x1UL <<
AG903_SSC_CA5_RUN_STATUS_RESET_POS
) 949:
#define
AG903_SSC_CA5_RUN_STATUS_WFE_POS
8 950:
#define
AG903_SSC_CA5_RUN_STATUS_WFE_MSK
(0x1UL <<
AG903_SSC_CA5_RUN_STATUS_WFE_POS
) 951:
#define
AG903_SSC_CA5_RUN_STATUS_WFI_POS
12 952:
#define
AG903_SSC_CA5_RUN_STATUS_WFI_MSK
(0x1UL <<
AG903_SSC_CA5_RUN_STATUS_WFI_POS
) 953:
#define
AG903_SSC_CA5_RUN_STATUS_EVENTO_POS
16 954:
#define
AG903_SSC_CA5_RUN_STATUS_EVENTO_MSK
(0x1UL <<
AG903_SSC_CA5_RUN_STATUS_EVENTO_POS
) 955: 956:
#define
AG903_SSC_CA5_ACP_SETUP_ACPADDR_POS
29 957:
#define
AG903_SSC_CA5_ACP_SETUP_ACPADDR_MSK
(0x7UL <<
AG903_SSC_CA5_ACP_SETUP_ACPADDR_POS
) 958: 959:
#define
AG903_SSC_DMA_SELECT0_DMASELECT0_POS
0 960:
#define
AG903_SSC_DMA_SELECT0_DMASELECT0_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT0_DMASELECT0_POS
) 961:
#define
AG903_SSC_DMA_SELECT0_DMASELECT1_POS
8 962:
#define
AG903_SSC_DMA_SELECT0_DMASELECT1_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT0_DMASELECT1_POS
) 963:
#define
AG903_SSC_DMA_SELECT0_DMASELECT2_POS
16 964:
#define
AG903_SSC_DMA_SELECT0_DMASELECT2_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT0_DMASELECT2_POS
) 965:
#define
AG903_SSC_DMA_SELECT0_DMASELECT3_POS
24 966:
#define
AG903_SSC_DMA_SELECT0_DMASELECT3_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT0_DMASELECT3_POS
) 967: 968:
#define
AG903_SSC_DMA_SELECT1_DMASELECT4_POS
0 969:
#define
AG903_SSC_DMA_SELECT1_DMASELECT4_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT1_DMASELECT4_POS
) 970:
#define
AG903_SSC_DMA_SELECT1_DMASELECT5_POS
8 971:
#define
AG903_SSC_DMA_SELECT1_DMASELECT5_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT1_DMASELECT5_POS
) 972:
#define
AG903_SSC_DMA_SELECT1_DMASELECT6_POS
16 973:
#define
AG903_SSC_DMA_SELECT1_DMASELECT6_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT1_DMASELECT6_POS
) 974:
#define
AG903_SSC_DMA_SELECT1_DMASELECT7_POS
24 975:
#define
AG903_SSC_DMA_SELECT1_DMASELECT7_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT1_DMASELECT7_POS
) 976: 977:
#define
AG903_SSC_DMA_SELECT2_DMASELECT8_POS
0 978:
#define
AG903_SSC_DMA_SELECT2_DMASELECT8_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT2_DMASELECT8_POS
) 979:
#define
AG903_SSC_DMA_SELECT2_DMASELECT9_POS
8 980:
#define
AG903_SSC_DMA_SELECT2_DMASELECT9_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT2_DMASELECT9_POS
) 981:
#define
AG903_SSC_DMA_SELECT2_DMASELECT10_POS
16 982:
#define
AG903_SSC_DMA_SELECT2_DMASELECT10_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT2_DMASELECT10_POS
) 983:
#define
AG903_SSC_DMA_SELECT2_DMASELECT11_POS
24 984:
#define
AG903_SSC_DMA_SELECT2_DMASELECT11_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT2_DMASELECT11_POS
) 985: 986:
#define
AG903_SSC_DMA_SELECT3_DMASELECT12_POS
0 987:
#define
AG903_SSC_DMA_SELECT3_DMASELECT12_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT3_DMASELECT12_POS
) 988:
#define
AG903_SSC_DMA_SELECT3_DMASELECT13_POS
8 989:
#define
AG903_SSC_DMA_SELECT3_DMASELECT13_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT3_DMASELECT13_POS
) 990:
#define
AG903_SSC_DMA_SELECT3_DMASELECT14_POS
16 991:
#define
AG903_SSC_DMA_SELECT3_DMASELECT14_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT3_DMASELECT14_POS
) 992:
#define
AG903_SSC_DMA_SELECT3_DMASELECT15_POS
24 993:
#define
AG903_SSC_DMA_SELECT3_DMASELECT15_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT3_DMASELECT15_POS
) 994: 995:
#define
AG903_SSC_DMA_SELECT_PBD_DMASELECT_POS
0 996:
#define
AG903_SSC_DMA_SELECT_PBD_DMASELECT_MSK
(0xffUL <<
AG903_SSC_DMA_SELECT_PBD_DMASELECT_POS
) 997: 998:
#define
AG903_SSC_DSP_SETUP_VSYNC0_DIR_POS
0 999:
#define
AG903_SSC_DSP_SETUP_VSYNC0_DIR_MSK
(0x1UL <<
AG903_SSC_DSP_SETUP_VSYNC0_DIR_POS
) 1000:
#define
AG903_SSC_DSP_SETUP_FIELD0_DIR_POS
1 1001:
#define
AG903_SSC_DSP_SETUP_FIELD0_DIR_MSK
(0x1UL <<
AG903_SSC_DSP_SETUP_FIELD0_DIR_POS
) 1002:
#define
AG903_SSC_DSP_SETUP_DOT0_DIR_POS
2 1003:
#define
AG903_SSC_DSP_SETUP_DOT0_DIR_MSK
(0x1UL <<
AG903_SSC_DSP_SETUP_DOT0_DIR_POS
) 1004:
#define
AG903_SSC_DSP_SETUP_VSYNC1_DIR_POS
4 1005:
#define
AG903_SSC_DSP_SETUP_VSYNC1_DIR_MSK
(0x1UL <<
AG903_SSC_DSP_SETUP_VSYNC1_DIR_POS
) 1006:
#define
AG903_SSC_DSP_SETUP_FIELD1_DIR_POS
5 1007:
#define
AG903_SSC_DSP_SETUP_FIELD1_DIR_MSK
(0x1UL <<
AG903_SSC_DSP_SETUP_FIELD1_DIR_POS
) 1008:
#define
AG903_SSC_DSP_SETUP_DOT1_DIR_POS
6 1009:
#define
AG903_SSC_DSP_SETUP_DOT1_DIR_MSK
(0x1UL <<
AG903_SSC_DSP_SETUP_DOT1_DIR_POS
) 1010: 1011:
#define
AG903_SSC_TICK0_SETUP_DIVNUM_POS
0 1012:
#define
AG903_SSC_TICK0_SETUP_DIVNUM_MSK
(0xffffffUL <<
AG903_SSC_TICK0_SETUP_DIVNUM_POS
) 1013:
#define
AG903_SSC_TICK0_SETUP_CLKSEL_POS
24 1014:
#define
AG903_SSC_TICK0_SETUP_CLKSEL_MSK
(0xfUL <<
AG903_SSC_TICK0_SETUP_CLKSEL_POS
) 1015: 1016:
#define
AG903_SSC_TICK1_SETUP_DIVNUM_POS
0 1017:
#define
AG903_SSC_TICK1_SETUP_DIVNUM_MSK
(0xffffffUL <<
AG903_SSC_TICK1_SETUP_DIVNUM_POS
) 1018:
#define
AG903_SSC_TICK1_SETUP_CLKSEL_POS
24 1019:
#define
AG903_SSC_TICK1_SETUP_CLKSEL_MSK
(0xfUL <<
AG903_SSC_TICK1_SETUP_CLKSEL_POS
) 1020: 1021:
#define
AG903_SSC_TIM_SETUP_TIM_DIR_POS
0 1022:
#define
AG903_SSC_TIM_SETUP_TIM_DIR_MSK
(0xfUL <<
AG903_SSC_TIM_SETUP_TIM_DIR_POS
) 1023: 1024:
#define
AG903_SSC_SSP_SETUP_SSP0_DIR_POS
0 1025:
#define
AG903_SSC_SSP_SETUP_SSP0_DIR_MSK
(0x1UL <<
AG903_SSC_SSP_SETUP_SSP0_DIR_POS
) 1026:
#define
AG903_SSC_SSP_SETUP_SSP0_MODE_POS
1 1027:
#define
AG903_SSC_SSP_SETUP_SSP0_MODE_MSK
(0x1UL <<
AG903_SSC_SSP_SETUP_SSP0_MODE_POS
) 1028:
#define
AG903_SSC_SSP_SETUP_SSP0_MCLK_DIR_POS
2 1029:
#define
AG903_SSC_SSP_SETUP_SSP0_MCLK_DIR_MSK
(0x1UL <<
AG903_SSC_SSP_SETUP_SSP0_MCLK_DIR_POS
) 1030:
#define
AG903_SSC_SSP_SETUP_SSP0_MCLK_DIV_POS
3 1031:
#define
AG903_SSC_SSP_SETUP_SSP0_MCLK_DIV_MSK
(0x1fUL <<
AG903_SSC_SSP_SETUP_SSP0_MCLK_DIV_POS
) 1032:
#define
AG903_SSC_SSP_SETUP_SSP1_DIR_POS
8 1033:
#define
AG903_SSC_SSP_SETUP_SSP1_DIR_MSK
(0x1UL <<
AG903_SSC_SSP_SETUP_SSP1_DIR_POS
) 1034:
#define
AG903_SSC_SSP_SETUP_SSP1_MODE_POS
9 1035:
#define
AG903_SSC_SSP_SETUP_SSP1_MODE_MSK
(0x1UL <<
AG903_SSC_SSP_SETUP_SSP1_MODE_POS
) 1036:
#define
AG903_SSC_SSP_SETUP_SSP1_MCLK_DIR_POS
10 1037:
#define
AG903_SSC_SSP_SETUP_SSP1_MCLK_DIR_MSK
(0x1UL <<
AG903_SSC_SSP_SETUP_SSP1_MCLK_DIR_POS
) 1038:
#define
AG903_SSC_SSP_SETUP_SSP1_MCLK_DIV_POS
11 1039:
#define
AG903_SSC_SSP_SETUP_SSP1_MCLK_DIV_MSK
(0x1fUL <<
AG903_SSC_SSP_SETUP_SSP1_MCLK_DIV_POS
) 1040:
#define
AG903_SSC_SSP_SETUP_SSP2_DIR_POS
16 1041:
#define
AG903_SSC_SSP_SETUP_SSP2_DIR_MSK
(0x1UL <<
AG903_SSC_SSP_SETUP_SSP2_DIR_POS
) 1042:
#define
AG903_SSC_SSP_SETUP_SSP2_MODE_POS
17 1043:
#define
AG903_SSC_SSP_SETUP_SSP2_MODE_MSK
(0x1UL <<
AG903_SSC_SSP_SETUP_SSP2_MODE_POS
) 1044:
#define
AG903_SSC_SSP_SETUP_SSP2_MCLK_DIR_POS
18 1045:
#define
AG903_SSC_SSP_SETUP_SSP2_MCLK_DIR_MSK
(0x1UL <<
AG903_SSC_SSP_SETUP_SSP2_MCLK_DIR_POS
) 1046:
#define
AG903_SSC_SSP_SETUP_SSP2_MCLK_DIV_POS
19 1047:
#define
AG903_SSC_SSP_SETUP_SSP2_MCLK_DIV_MSK
(0x1fUL <<
AG903_SSC_SSP_SETUP_SSP2_MCLK_DIV_POS
) 1048:
#define
AG903_SSC_SSP_SETUP_SSP3_DIR_POS
24 1049:
#define
AG903_SSC_SSP_SETUP_SSP3_DIR_MSK
(0x1UL <<
AG903_SSC_SSP_SETUP_SSP3_DIR_POS
) 1050:
#define
AG903_SSC_SSP_SETUP_SSP3_MODE_POS
25 1051:
#define
AG903_SSC_SSP_SETUP_SSP3_MODE_MSK
(0x1UL <<
AG903_SSC_SSP_SETUP_SSP3_MODE_POS
) 1052:
#define
AG903_SSC_SSP_SETUP_SSP3_MCLK_DIR_POS
26 1053:
#define
AG903_SSC_SSP_SETUP_SSP3_MCLK_DIR_MSK
(0x1UL <<
AG903_SSC_SSP_SETUP_SSP3_MCLK_DIR_POS
) 1054:
#define
AG903_SSC_SSP_SETUP_SSP3_MCLK_DIV_POS
27 1055:
#define
AG903_SSC_SSP_SETUP_SSP3_MCLK_DIV_MSK
(0x1fUL <<
AG903_SSC_SSP_SETUP_SSP3_MCLK_DIV_POS
) 1056: 1057:
#define
AG903_SSC_PBD_ADDRCHECK_START_START_ADDR_POS
2 1058:
#define
AG903_SSC_PBD_ADDRCHECK_START_START_ADDR_MSK
(0x3fffffffUL <<
AG903_SSC_PBD_ADDRCHECK_START_START_ADDR_POS
) 1059: 1060:
#define
AG903_SSC_PBD_ADDRCHECK_END_END_ADDR_POS
2 1061:
#define
AG903_SSC_PBD_ADDRCHECK_END_END_ADDR_MSK
(0x3fffffffUL <<
AG903_SSC_PBD_ADDRCHECK_END_END_ADDR_POS
) 1062: 1063:
#define
AG903_SSC_PBD_ADDRCHECK_ENABLE_ENABLE_POS
0 1064:
#define
AG903_SSC_PBD_ADDRCHECK_ENABLE_ENABLE_MSK
(0x1UL <<
AG903_SSC_PBD_ADDRCHECK_ENABLE_ENABLE_POS
) 1065: 1066:
#define
AG903_SSC_PBD_ADDRCHECK_STATUS_STATUS_POS
0 1067:
#define
AG903_SSC_PBD_ADDRCHECK_STATUS_STATUS_MSK
(0x1UL <<
AG903_SSC_PBD_ADDRCHECK_STATUS_STATUS_POS
) 1068: 1069:
#define
AG903_SSC_BMU_STATUS_SNKRDY_POS
0 1070:
#define
AG903_SSC_BMU_STATUS_SNKRDY_MSK
(0xfUL <<
AG903_SSC_BMU_STATUS_SNKRDY_POS
) 1071:
#define
AG903_SSC_BMU_STATUS_SNKREQ_POS
4 1072:
#define
AG903_SSC_BMU_STATUS_SNKREQ_MSK
(0xfUL <<
AG903_SSC_BMU_STATUS_SNKREQ_POS
) 1073:
#define
AG903_SSC_BMU_STATUS_SRCRDY_POS
8 1074:
#define
AG903_SSC_BMU_STATUS_SRCRDY_MSK
(0x7ffUL <<
AG903_SSC_BMU_STATUS_SRCRDY_POS
) 1075:
#define
AG903_SSC_BMU_STATUS_SRCREQ_POS
20 1076:
#define
AG903_SSC_BMU_STATUS_SRCREQ_MSK
(0x7ffUL <<
AG903_SSC_BMU_STATUS_SRCREQ_POS
) 1077: 1078:
#define
AG903_SSC_BMU_CONTROL_CLR_SNK_POS
0 1079:
#define
AG903_SSC_BMU_CONTROL_CLR_SNK_MSK
(0xfUL <<
AG903_SSC_BMU_CONTROL_CLR_SNK_POS
) 1080:
#define
AG903_SSC_BMU_CONTROL_SET_SNK_POS
4 1081:
#define
AG903_SSC_BMU_CONTROL_SET_SNK_MSK
(0xfUL <<
AG903_SSC_BMU_CONTROL_SET_SNK_POS
) 1082:
#define
AG903_SSC_BMU_CONTROL_CLR_SRC_POS
8 1083:
#define
AG903_SSC_BMU_CONTROL_CLR_SRC_MSK
(0x7ffUL <<
AG903_SSC_BMU_CONTROL_CLR_SRC_POS
) 1084:
#define
AG903_SSC_BMU_CONTROL_SET_SRC_POS
20 1085:
#define
AG903_SSC_BMU_CONTROL_SET_SRC_MSK
(0x7ffUL <<
AG903_SSC_BMU_CONTROL_SET_SRC_POS
) 1086: 1087:
#define
AG903_SSC_BMU_TRIG_STATUS_SNKRDY_POS
0 1088:
#define
AG903_SSC_BMU_TRIG_STATUS_SNKRDY_MSK
(0xfUL <<
AG903_SSC_BMU_TRIG_STATUS_SNKRDY_POS
) 1089:
#define
AG903_SSC_BMU_TRIG_STATUS_SNKREQ_POS
4 1090:
#define
AG903_SSC_BMU_TRIG_STATUS_SNKREQ_MSK
(0xfUL <<
AG903_SSC_BMU_TRIG_STATUS_SNKREQ_POS
) 1091:
#define
AG903_SSC_BMU_TRIG_STATUS_SRCRDY_POS
8 1092:
#define
AG903_SSC_BMU_TRIG_STATUS_SRCRDY_MSK
(0x7ffUL <<
AG903_SSC_BMU_TRIG_STATUS_SRCRDY_POS
) 1093:
#define
AG903_SSC_BMU_TRIG_STATUS_SRCREQ_POS
20 1094:
#define
AG903_SSC_BMU_TRIG_STATUS_SRCREQ_MSK
(0x7ffUL <<
AG903_SSC_BMU_TRIG_STATUS_SRCREQ_POS
) 1095: 1096:
#define
AG903_SSC_BMU_TRIG_CLEAR_SNKRDY_POS
0 1097:
#define
AG903_SSC_BMU_TRIG_CLEAR_SNKRDY_MSK
(0xfUL <<
AG903_SSC_BMU_TRIG_CLEAR_SNKRDY_POS
) 1098:
#define
AG903_SSC_BMU_TRIG_CLEAR_SNKREQ_POS
4 1099:
#define
AG903_SSC_BMU_TRIG_CLEAR_SNKREQ_MSK
(0xfUL <<
AG903_SSC_BMU_TRIG_CLEAR_SNKREQ_POS
) 1100:
#define
AG903_SSC_BMU_TRIG_CLEAR_SRCRDY_POS
8 1101:
#define
AG903_SSC_BMU_TRIG_CLEAR_SRCRDY_MSK
(0x7ffUL <<
AG903_SSC_BMU_TRIG_CLEAR_SRCRDY_POS
) 1102:
#define
AG903_SSC_BMU_TRIG_CLEAR_SRCREQ_POS
20 1103:
#define
AG903_SSC_BMU_TRIG_CLEAR_SRCREQ_MSK
(0x7ffUL <<
AG903_SSC_BMU_TRIG_CLEAR_SRCREQ_POS
) 1104: 1105:
#define
AG903_SSC_PORT_WAIT_CYCLE_POS
0 1106:
#define
AG903_SSC_PORT_WAIT_CYCLE_MSK
(0xffffUL <<
AG903_SSC_PORT_WAIT_CYCLE_POS
) 1107: 1108:
#define
AG903_SSC_PBH_MODE_WAIT_POS
1 1109:
#define
AG903_SSC_PBH_MODE_WAIT_MSK
(0x1UL <<
AG903_SSC_PBH_MODE_WAIT_POS
) 1110: 1111:
#define
AG903_SSC_TDM0_SETUP_ST_RX_POS
0 1112:
#define
AG903_SSC_TDM0_SETUP_ST_RX_MSK
(0x1UL <<
AG903_SSC_TDM0_SETUP_ST_RX_POS
) 1113:
#define
AG903_SSC_TDM0_SETUP_ST_TX_POS
1 1114:
#define
AG903_SSC_TDM0_SETUP_ST_TX_MSK
(0x1UL <<
AG903_SSC_TDM0_SETUP_ST_TX_POS
) 1115:
#define
AG903_SSC_TDM0_SETUP_SCLK_N_POS
2 1116:
#define
AG903_SSC_TDM0_SETUP_SCLK_N_MSK
(0x7UL <<
AG903_SSC_TDM0_SETUP_SCLK_N_POS
) 1117:
#define
AG903_SSC_TDM0_SETUP_TDM_N_POS
5 1118:
#define
AG903_SSC_TDM0_SETUP_TDM_N_MSK
(0x3UL <<
AG903_SSC_TDM0_SETUP_TDM_N_POS
) 1119:
#define
AG903_SSC_TDM0_SETUP_DIR_TX_POS
7 1120:
#define
AG903_SSC_TDM0_SETUP_DIR_TX_MSK
(0x1UL <<
AG903_SSC_TDM0_SETUP_DIR_TX_POS
) 1121:
#define
AG903_SSC_TDM0_SETUP_FS_RXERR_POS
8 1122:
#define
AG903_SSC_TDM0_SETUP_FS_RXERR_MSK
(0x1UL <<
AG903_SSC_TDM0_SETUP_FS_RXERR_POS
) 1123:
#define
AG903_SSC_TDM0_SETUP_FS_DIST_POS
9 1124:
#define
AG903_SSC_TDM0_SETUP_FS_DIST_MSK
(0x1UL <<
AG903_SSC_TDM0_SETUP_FS_DIST_POS
) 1125:
#define
AG903_SSC_TDM0_SETUP_FS_TXPW_POS
10 1126:
#define
AG903_SSC_TDM0_SETUP_FS_TXPW_MSK
(0x1UL <<
AG903_SSC_TDM0_SETUP_FS_TXPW_POS
) 1127:
#define
AG903_SSC_TDM0_SETUP_FS_POL_POS
11 1128:
#define
AG903_SSC_TDM0_SETUP_FS_POL_MSK
(0x1UL <<
AG903_SSC_TDM0_SETUP_FS_POL_POS
) 1129:
#define
AG903_SSC_TDM0_SETUP_SCLK_POL_POS
12 1130:
#define
AG903_SSC_TDM0_SETUP_SCLK_POL_MSK
(0x1UL <<
AG903_SSC_TDM0_SETUP_SCLK_POL_POS
) 1131:
#define
AG903_SSC_TDM0_SETUP_TDM_EN_POS
13 1132:
#define
AG903_SSC_TDM0_SETUP_TDM_EN_MSK
(0x1UL <<
AG903_SSC_TDM0_SETUP_TDM_EN_POS
) 1133: 1134:
#define
AG903_SSC_TDM1_SETUP_ST_RX_POS
0 1135:
#define
AG903_SSC_TDM1_SETUP_ST_RX_MSK
(0x1UL <<
AG903_SSC_TDM1_SETUP_ST_RX_POS
) 1136:
#define
AG903_SSC_TDM1_SETUP_ST_TX_POS
1 1137:
#define
AG903_SSC_TDM1_SETUP_ST_TX_MSK
(0x1UL <<
AG903_SSC_TDM1_SETUP_ST_TX_POS
) 1138:
#define
AG903_SSC_TDM1_SETUP_SCLK_N_POS
2 1139:
#define
AG903_SSC_TDM1_SETUP_SCLK_N_MSK
(0x7UL <<
AG903_SSC_TDM1_SETUP_SCLK_N_POS
) 1140:
#define
AG903_SSC_TDM1_SETUP_TDM_N_POS
5 1141:
#define
AG903_SSC_TDM1_SETUP_TDM_N_MSK
(0x3UL <<
AG903_SSC_TDM1_SETUP_TDM_N_POS
) 1142:
#define
AG903_SSC_TDM1_SETUP_DIR_TX_POS
7 1143:
#define
AG903_SSC_TDM1_SETUP_DIR_TX_MSK
(0x1UL <<
AG903_SSC_TDM1_SETUP_DIR_TX_POS
) 1144:
#define
AG903_SSC_TDM1_SETUP_FS_RXERR_POS
8 1145:
#define
AG903_SSC_TDM1_SETUP_FS_RXERR_MSK
(0x1UL <<
AG903_SSC_TDM1_SETUP_FS_RXERR_POS
) 1146:
#define
AG903_SSC_TDM1_SETUP_FS_DIST_POS
9 1147:
#define
AG903_SSC_TDM1_SETUP_FS_DIST_MSK
(0x1UL <<
AG903_SSC_TDM1_SETUP_FS_DIST_POS
) 1148:
#define
AG903_SSC_TDM1_SETUP_FS_TXPW_POS
10 1149:
#define
AG903_SSC_TDM1_SETUP_FS_TXPW_MSK
(0x1UL <<
AG903_SSC_TDM1_SETUP_FS_TXPW_POS
) 1150:
#define
AG903_SSC_TDM1_SETUP_FS_POL_POS
11 1151:
#define
AG903_SSC_TDM1_SETUP_FS_POL_MSK
(0x1UL <<
AG903_SSC_TDM1_SETUP_FS_POL_POS
) 1152:
#define
AG903_SSC_TDM1_SETUP_SCLK_POL_POS
12 1153:
#define
AG903_SSC_TDM1_SETUP_SCLK_POL_MSK
(0x1UL <<
AG903_SSC_TDM1_SETUP_SCLK_POL_POS
) 1154:
#define
AG903_SSC_TDM1_SETUP_TDM_EN_POS
13 1155:
#define
AG903_SSC_TDM1_SETUP_TDM_EN_MSK
(0x1UL <<
AG903_SSC_TDM1_SETUP_TDM_EN_POS
) 1156: 1157:
#define
AG903_SSC_TDM2_SETUP_ST_RX_POS
0 1158:
#define
AG903_SSC_TDM2_SETUP_ST_RX_MSK
(0x1UL <<
AG903_SSC_TDM2_SETUP_ST_RX_POS
) 1159:
#define
AG903_SSC_TDM2_SETUP_ST_TX_POS
1 1160:
#define
AG903_SSC_TDM2_SETUP_ST_TX_MSK
(0x1UL <<
AG903_SSC_TDM2_SETUP_ST_TX_POS
) 1161:
#define
AG903_SSC_TDM2_SETUP_SCLK_N_POS
2 1162:
#define
AG903_SSC_TDM2_SETUP_SCLK_N_MSK
(0x7UL <<
AG903_SSC_TDM2_SETUP_SCLK_N_POS
) 1163:
#define
AG903_SSC_TDM2_SETUP_TDM_N_POS
5 1164:
#define
AG903_SSC_TDM2_SETUP_TDM_N_MSK
(0x3UL <<
AG903_SSC_TDM2_SETUP_TDM_N_POS
) 1165:
#define
AG903_SSC_TDM2_SETUP_DIR_TX_POS
7 1166:
#define
AG903_SSC_TDM2_SETUP_DIR_TX_MSK
(0x1UL <<
AG903_SSC_TDM2_SETUP_DIR_TX_POS
) 1167:
#define
AG903_SSC_TDM2_SETUP_FS_RXERR_POS
8 1168:
#define
AG903_SSC_TDM2_SETUP_FS_RXERR_MSK
(0x1UL <<
AG903_SSC_TDM2_SETUP_FS_RXERR_POS
) 1169:
#define
AG903_SSC_TDM2_SETUP_FS_DIST_POS
9 1170:
#define
AG903_SSC_TDM2_SETUP_FS_DIST_MSK
(0x1UL <<
AG903_SSC_TDM2_SETUP_FS_DIST_POS
) 1171:
#define
AG903_SSC_TDM2_SETUP_FS_TXPW_POS
10 1172:
#define
AG903_SSC_TDM2_SETUP_FS_TXPW_MSK
(0x1UL <<
AG903_SSC_TDM2_SETUP_FS_TXPW_POS
) 1173:
#define
AG903_SSC_TDM2_SETUP_FS_POL_POS
11 1174:
#define
AG903_SSC_TDM2_SETUP_FS_POL_MSK
(0x1UL <<
AG903_SSC_TDM2_SETUP_FS_POL_POS
) 1175:
#define
AG903_SSC_TDM2_SETUP_SCLK_POL_POS
12 1176:
#define
AG903_SSC_TDM2_SETUP_SCLK_POL_MSK
(0x1UL <<
AG903_SSC_TDM2_SETUP_SCLK_POL_POS
) 1177:
#define
AG903_SSC_TDM2_SETUP_TDM_EN_POS
13 1178:
#define
AG903_SSC_TDM2_SETUP_TDM_EN_MSK
(0x1UL <<
AG903_SSC_TDM2_SETUP_TDM_EN_POS
) 1179: 1180:
#define
AG903_SSC_TDM3_SETUP_ST_RX_POS
0 1181:
#define
AG903_SSC_TDM3_SETUP_ST_RX_MSK
(0x1UL <<
AG903_SSC_TDM3_SETUP_ST_RX_POS
) 1182:
#define
AG903_SSC_TDM3_SETUP_ST_TX_POS
1 1183:
#define
AG903_SSC_TDM3_SETUP_ST_TX_MSK
(0x1UL <<
AG903_SSC_TDM3_SETUP_ST_TX_POS
) 1184:
#define
AG903_SSC_TDM3_SETUP_SCLK_N_POS
2 1185:
#define
AG903_SSC_TDM3_SETUP_SCLK_N_MSK
(0x7UL <<
AG903_SSC_TDM3_SETUP_SCLK_N_POS
) 1186:
#define
AG903_SSC_TDM3_SETUP_TDM_N_POS
5 1187:
#define
AG903_SSC_TDM3_SETUP_TDM_N_MSK
(0x3UL <<
AG903_SSC_TDM3_SETUP_TDM_N_POS
) 1188:
#define
AG903_SSC_TDM3_SETUP_DIR_TX_POS
7 1189:
#define
AG903_SSC_TDM3_SETUP_DIR_TX_MSK
(0x1UL <<
AG903_SSC_TDM3_SETUP_DIR_TX_POS
) 1190:
#define
AG903_SSC_TDM3_SETUP_FS_RXERR_POS
8 1191:
#define
AG903_SSC_TDM3_SETUP_FS_RXERR_MSK
(0x1UL <<
AG903_SSC_TDM3_SETUP_FS_RXERR_POS
) 1192:
#define
AG903_SSC_TDM3_SETUP_FS_DIST_POS
9 1193:
#define
AG903_SSC_TDM3_SETUP_FS_DIST_MSK
(0x1UL <<
AG903_SSC_TDM3_SETUP_FS_DIST_POS
) 1194:
#define
AG903_SSC_TDM3_SETUP_FS_TXPW_POS
10 1195:
#define
AG903_SSC_TDM3_SETUP_FS_TXPW_MSK
(0x1UL <<
AG903_SSC_TDM3_SETUP_FS_TXPW_POS
) 1196:
#define
AG903_SSC_TDM3_SETUP_FS_POL_POS
11 1197:
#define
AG903_SSC_TDM3_SETUP_FS_POL_MSK
(0x1UL <<
AG903_SSC_TDM3_SETUP_FS_POL_POS
) 1198:
#define
AG903_SSC_TDM3_SETUP_SCLK_POL_POS
12 1199:
#define
AG903_SSC_TDM3_SETUP_SCLK_POL_MSK
(0x1UL <<
AG903_SSC_TDM3_SETUP_SCLK_POL_POS
) 1200:
#define
AG903_SSC_TDM3_SETUP_TDM_EN_POS
13 1201:
#define
AG903_SSC_TDM3_SETUP_TDM_EN_MSK
(0x1UL <<
AG903_SSC_TDM3_SETUP_TDM_EN_POS
) 1202: 1203:
#define
AG903_SSC_USB_POWER_SETUP_PWR_PROT_EN_POS
0 1204:
#define
AG903_SSC_USB_POWER_SETUP_PWR_PROT_EN_MSK
(0x1UL <<
AG903_SSC_USB_POWER_SETUP_PWR_PROT_EN_POS
) 1205:
#define
AG903_SSC_USB_POWER_SETUP_PWR_INT_EN_POS
1 1206:
#define
AG903_SSC_USB_POWER_SETUP_PWR_INT_EN_MSK
(0x1UL <<
AG903_SSC_USB_POWER_SETUP_PWR_INT_EN_POS
) 1207:
#define
AG903_SSC_USB_POWER_SETUP_PWR_MODE_POS
2 1208:
#define
AG903_SSC_USB_POWER_SETUP_PWR_MODE_MSK
(0x1UL <<
AG903_SSC_USB_POWER_SETUP_PWR_MODE_POS
) 1209: 1210:
#define
AG903_SSC_USB_POWER_STATUS_PWR_PROT_STATE_POS
0 1211:
#define
AG903_SSC_USB_POWER_STATUS_PWR_PROT_STATE_MSK
(0x1UL <<
AG903_SSC_USB_POWER_STATUS_PWR_PROT_STATE_POS
) 1212:
#define
AG903_SSC_USB_POWER_STATUS_PWR_PROT_PIN_POS
1 1213:
#define
AG903_SSC_USB_POWER_STATUS_PWR_PROT_PIN_MSK
(0x1UL <<
AG903_SSC_USB_POWER_STATUS_PWR_PROT_PIN_POS
) 1214:
#define
AG903_SSC_USB_POWER_STATUS_VBUS_PIN_POS
2 1215:
#define
AG903_SSC_USB_POWER_STATUS_VBUS_PIN_MSK
(0x1UL <<
AG903_SSC_USB_POWER_STATUS_VBUS_PIN_POS
) 1216: 1217:
#define
AG903_SSC_USB_POWER_CLEAR_PWR_PROT_CLR_POS
0 1218:
#define
AG903_SSC_USB_POWER_CLEAR_PWR_PROT_CLR_MSK
(0x1UL <<
AG903_SSC_USB_POWER_CLEAR_PWR_PROT_CLR_POS
) 1219: 1220:
#define
AG903_SSC_SD_POWER_SETUP_PWR_PROT_EN_POS
0 1221:
#define
AG903_SSC_SD_POWER_SETUP_PWR_PROT_EN_MSK
(0x1UL <<
AG903_SSC_SD_POWER_SETUP_PWR_PROT_EN_POS
) 1222:
#define
AG903_SSC_SD_POWER_SETUP_PWR_INT_EN_POS
1 1223:
#define
AG903_SSC_SD_POWER_SETUP_PWR_INT_EN_MSK
(0x1UL <<
AG903_SSC_SD_POWER_SETUP_PWR_INT_EN_POS
) 1224: 1225:
#define
AG903_SSC_SD_POWER_STATUS_PWR_PROT_STATE_POS
0 1226:
#define
AG903_SSC_SD_POWER_STATUS_PWR_PROT_STATE_MSK
(0x1UL <<
AG903_SSC_SD_POWER_STATUS_PWR_PROT_STATE_POS
) 1227:
#define
AG903_SSC_SD_POWER_STATUS_PWR_PROT_PIN_POS
1 1228:
#define
AG903_SSC_SD_POWER_STATUS_PWR_PROT_PIN_MSK
(0x1UL <<
AG903_SSC_SD_POWER_STATUS_PWR_PROT_PIN_POS
) 1229: 1230:
#define
AG903_SSC_SD_POWER_CLEAR_PWR_PROT_CLR_POS
0 1231:
#define
AG903_SSC_SD_POWER_CLEAR_PWR_PROT_CLR_MSK
(0x1UL <<
AG903_SSC_SD_POWER_CLEAR_PWR_PROT_CLR_POS
) 1232: 1233:
#define
AG903_SSC_VIDEOADC_SETUP_GHO_POS
0 1234:
#define
AG903_SSC_VIDEOADC_SETUP_GHO_MSK
(0xfUL <<
AG903_SSC_VIDEOADC_SETUP_GHO_POS
) 1235:
#define
AG903_SSC_VIDEOADC_SETUP_CLHO_POS
4 1236:
#define
AG903_SSC_VIDEOADC_SETUP_CLHO_MSK
(0xfUL <<
AG903_SSC_VIDEOADC_SETUP_CLHO_POS
) 1237:
#define
AG903_SSC_VIDEOADC_SETUP_CTHO_POS
8 1238:
#define
AG903_SSC_VIDEOADC_SETUP_CTHO_MSK
(0xfUL <<
AG903_SSC_VIDEOADC_SETUP_CTHO_POS
) 1239:
#define
AG903_SSC_VIDEOADC_SETUP_DATEN_POS
12 1240:
#define
AG903_SSC_VIDEOADC_SETUP_DATEN_MSK
(0xfUL <<
AG903_SSC_VIDEOADC_SETUP_DATEN_POS
) 1241:
#define
AG903_SSC_VIDEOADC_SETUP_ACQEN_POS
16 1242:
#define
AG903_SSC_VIDEOADC_SETUP_ACQEN_MSK
(0xfUL <<
AG903_SSC_VIDEOADC_SETUP_ACQEN_POS
) 1243:
#define
AG903_SSC_VIDEOADC_SETUP_ACQCLR_POS
20 1244:
#define
AG903_SSC_VIDEOADC_SETUP_ACQCLR_MSK
(0xfUL <<
AG903_SSC_VIDEOADC_SETUP_ACQCLR_POS
) 1245: 1246:
#define
AG903_SSC_CVBSDEC_ADDR_ADDR_POS
0 1247:
#define
AG903_SSC_CVBSDEC_ADDR_ADDR_MSK
(0xfffUL <<
AG903_SSC_CVBSDEC_ADDR_ADDR_POS
) 1248:
#define
AG903_SSC_CVBSDEC_ADDR_CH_POS
16 1249:
#define
AG903_SSC_CVBSDEC_ADDR_CH_MSK
(0x3UL <<
AG903_SSC_CVBSDEC_ADDR_CH_POS
) 1250: 1251:
#define
AG903_SSC_CVBSDEC_DATA_DATA_POS
0 1252:
#define
AG903_SSC_CVBSDEC_DATA_DATA_MSK
(0xffffUL <<
AG903_SSC_CVBSDEC_DATA_DATA_POS
) 1253: 1254:
#define
AG903_SSC_VIDEOADC_MAXMIN_MIN_POS
0 1255:
#define
AG903_SSC_VIDEOADC_MAXMIN_MIN_MSK
(0x3ffUL <<
AG903_SSC_VIDEOADC_MAXMIN_MIN_POS
) 1256:
#define
AG903_SSC_VIDEOADC_MAXMIN_MAX_POS
16 1257:
#define
AG903_SSC_VIDEOADC_MAXMIN_MAX_MSK
(0x3ffUL <<
AG903_SSC_VIDEOADC_MAXMIN_MAX_POS
) 1258: 1259:
#define
AG903_SSC_SGI_STATUS_SGI_STATUS_POS
0 1260:
#define
AG903_SSC_SGI_STATUS_SGI_STATUS_MSK
(0xffffffffUL <<
AG903_SSC_SGI_STATUS_SGI_STATUS_POS
) 1261: 1262:
#define
AG903_SSC_SGI_SET_SGI_SET_POS
0 1263:
#define
AG903_SSC_SGI_SET_SGI_SET_MSK
(0xffffffffUL <<
AG903_SSC_SGI_SET_SGI_SET_POS
) 1264: 1265:
#define
AG903_SSC_SGI_CLEAR_SGI_CLEAR_POS
0 1266:
#define
AG903_SSC_SGI_CLEAR_SGI_CLEAR_MSK
(0xffffffffUL <<
AG903_SSC_SGI_CLEAR_SGI_CLEAR_POS
) 1267: 1268:
#define
AG903_SSC_CA5_JUMPADDR_JUMPADDR_POS
0 1269:
#define
AG903_SSC_CA5_JUMPADDR_JUMPADDR_MSK
(0xffffffffUL <<
AG903_SSC_CA5_JUMPADDR_JUMPADDR_POS
) 1270: 1271:
#define
AG903_SSC_COUNT64_LOWER_COUNT64_LOWER_POS
0 1272:
#define
AG903_SSC_COUNT64_LOWER_COUNT64_LOWER_MSK
(0xffffffffUL <<
AG903_SSC_COUNT64_LOWER_COUNT64_LOWER_POS
) 1273: 1274:
#define
AG903_SSC_COUNT64_UPPER_COUNT64_UPPER_POS
0 1275:
#define
AG903_SSC_COUNT64_UPPER_COUNT64_UPPER_MSK
(0xffffffffUL <<
AG903_SSC_COUNT64_UPPER_COUNT64_UPPER_POS
) 1276: 1277:
#endif
1278:
Copyright (c) 2017-2025 Axell Corporation. All rights reserved.
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