AG903ライブラリリファレンス
Body Source
spcdef.h
本文ソース
コピコード
1: 9: 10: 14: 15:
#ifndef
_SPCDEF_H_ 16:
#define
_SPCDEF_H_ 17: 18: 19: 20:
#define
AG903_SPC_AHB_CLK_CTRL_ATA_POS
25 21:
#define
AG903_SPC_AHB_CLK_CTRL_ATA_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_ATA_POS
) 22:
#define
AG903_SPC_AHB_CLK_CTRL_SMC_POS
24 23:
#define
AG903_SPC_AHB_CLK_CTRL_SMC_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_SMC_POS
) 24:
#define
AG903_SPC_AHB_CLK_CTRL_H2P_POS
23 25:
#define
AG903_SPC_AHB_CLK_CTRL_H2P_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_H2P_POS
) 26:
#define
AG903_SPC_AHB_CLK_CTRL_SPI_POS
22 27:
#define
AG903_SPC_AHB_CLK_CTRL_SPI_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_SPI_POS
) 28:
#define
AG903_SPC_AHB_CLK_CTRL_EBI_POS
21 29:
#define
AG903_SPC_AHB_CLK_CTRL_EBI_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_EBI_POS
) 30:
#define
AG903_SPC_AHB_CLK_CTRL_BSC_POS
20 31:
#define
AG903_SPC_AHB_CLK_CTRL_BSC_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_BSC_POS
) 32:
#define
AG903_SPC_AHB_CLK_CTRL_X2H3_POS
19 33:
#define
AG903_SPC_AHB_CLK_CTRL_X2H3_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_X2H3_POS
) 34:
#define
AG903_SPC_AHB_CLK_CTRL_X2H1_POS
18 35:
#define
AG903_SPC_AHB_CLK_CTRL_X2H1_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_X2H1_POS
) 36:
#define
AG903_SPC_AHB_CLK_CTRL_HBCB_POS
17 37:
#define
AG903_SPC_AHB_CLK_CTRL_HBCB_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_HBCB_POS
) 38:
#define
AG903_SPC_AHB_CLK_CTRL_HBCP_POS
16 39:
#define
AG903_SPC_AHB_CLK_CTRL_HBCP_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_HBCP_POS
) 40:
#define
AG903_SPC_AHB_CLK_CTRL_USBP_POS
12 41:
#define
AG903_SPC_AHB_CLK_CTRL_USBP_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_USBP_POS
) 42:
#define
AG903_SPC_AHB_CLK_CTRL_DDR7_POS
11 43:
#define
AG903_SPC_AHB_CLK_CTRL_DDR7_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_DDR7_POS
) 44:
#define
AG903_SPC_AHB_CLK_CTRL_USBC_POS
10 45:
#define
AG903_SPC_AHB_CLK_CTRL_USBC_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_USBC_POS
) 46:
#define
AG903_SPC_AHB_CLK_CTRL_SDC_POS
9 47:
#define
AG903_SPC_AHB_CLK_CTRL_SDC_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_SDC_POS
) 48:
#define
AG903_SPC_AHB_CLK_CTRL_ETH_POS
8 49:
#define
AG903_SPC_AHB_CLK_CTRL_ETH_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_ETH_POS
) 50:
#define
AG903_SPC_AHB_CLK_CTRL_H2X_POS
6 51:
#define
AG903_SPC_AHB_CLK_CTRL_H2X_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_H2X_POS
) 52:
#define
AG903_SPC_AHB_CLK_CTRL_X2H0_POS
5 53:
#define
AG903_SPC_AHB_CLK_CTRL_X2H0_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_X2H0_POS
) 54:
#define
AG903_SPC_AHB_CLK_CTRL_ALS_POS
3 55:
#define
AG903_SPC_AHB_CLK_CTRL_ALS_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_ALS_POS
) 56:
#define
AG903_SPC_AHB_CLK_CTRL_HBCM_POS
1 57:
#define
AG903_SPC_AHB_CLK_CTRL_HBCM_MSK
(1<<
AG903_SPC_AHB_CLK_CTRL_HBCM_POS
) 58: 59:
#define
AG903_SPC_APB_CLK_CTRL_UART3_POS
27 60:
#define
AG903_SPC_APB_CLK_CTRL_UART3_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_UART3_POS
) 61:
#define
AG903_SPC_APB_CLK_CTRL_UART2_POS
26 62:
#define
AG903_SPC_APB_CLK_CTRL_UART2_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_UART2_POS
) 63:
#define
AG903_SPC_APB_CLK_CTRL_UART1_POS
25 64:
#define
AG903_SPC_APB_CLK_CTRL_UART1_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_UART1_POS
) 65:
#define
AG903_SPC_APB_CLK_CTRL_UART0_POS
24 66:
#define
AG903_SPC_APB_CLK_CTRL_UART0_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_UART0_POS
) 67:
#define
AG903_SPC_APB_CLK_CTRL_CA5_POS
19 68:
#define
AG903_SPC_APB_CLK_CTRL_CA5_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_CA5_POS
) 69:
#define
AG903_SPC_APB_CLK_CTRL_H2X_POS
18 70:
#define
AG903_SPC_APB_CLK_CTRL_H2X_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_H2X_POS
) 71:
#define
AG903_SPC_APB_CLK_CTRL_IFW_POS
17 72:
#define
AG903_SPC_APB_CLK_CTRL_IFW_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_IFW_POS
) 73:
#define
AG903_SPC_APB_CLK_CTRL_IWM_POS
16 74:
#define
AG903_SPC_APB_CLK_CTRL_IWM_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_IWM_POS
) 75:
#define
AG903_SPC_APB_CLK_CTRL_X2H4_POS
15 76:
#define
AG903_SPC_APB_CLK_CTRL_X2H4_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_X2H4_POS
) 77:
#define
AG903_SPC_APB_CLK_CTRL_X2H3_POS
14 78:
#define
AG903_SPC_APB_CLK_CTRL_X2H3_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_X2H3_POS
) 79:
#define
AG903_SPC_APB_CLK_CTRL_X2H2_POS
13 80:
#define
AG903_SPC_APB_CLK_CTRL_X2H2_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_X2H2_POS
) 81:
#define
AG903_SPC_APB_CLK_CTRL_X2H1_POS
12 82:
#define
AG903_SPC_APB_CLK_CTRL_X2H1_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_X2H1_POS
) 83:
#define
AG903_SPC_APB_CLK_CTRL_X2H0_POS
11 84:
#define
AG903_SPC_APB_CLK_CTRL_X2H0_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_X2H0_POS
) 85:
#define
AG903_SPC_APB_CLK_CTRL_AXIC_POS
10 86:
#define
AG903_SPC_APB_CLK_CTRL_AXIC_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_AXIC_POS
) 87:
#define
AG903_SPC_APB_CLK_CTRL_DDR_POS
9 88:
#define
AG903_SPC_APB_CLK_CTRL_DDR_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_DDR_POS
) 89:
#define
AG903_SPC_APB_CLK_CTRL_DMAC_POS
8 90:
#define
AG903_SPC_APB_CLK_CTRL_DMAC_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_DMAC_POS
) 91:
#define
AG903_SPC_APB_CLK_CTRL_WDT_POS
7 92:
#define
AG903_SPC_APB_CLK_CTRL_WDT_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_WDT_POS
) 93:
#define
AG903_SPC_APB_CLK_CTRL_SSP3_POS
6 94:
#define
AG903_SPC_APB_CLK_CTRL_SSP3_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_SSP3_POS
) 95:
#define
AG903_SPC_APB_CLK_CTRL_SSP2_POS
5 96:
#define
AG903_SPC_APB_CLK_CTRL_SSP2_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_SSP2_POS
) 97:
#define
AG903_SPC_APB_CLK_CTRL_SSP1_POS
4 98:
#define
AG903_SPC_APB_CLK_CTRL_SSP1_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_SSP1_POS
) 99:
#define
AG903_SPC_APB_CLK_CTRL_SSP0_POS
3 100:
#define
AG903_SPC_APB_CLK_CTRL_SSP0_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_SSP0_POS
) 101:
#define
AG903_SPC_APB_CLK_CTRL_IIC1_POS
2 102:
#define
AG903_SPC_APB_CLK_CTRL_IIC1_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_IIC1_POS
) 103:
#define
AG903_SPC_APB_CLK_CTRL_IIC0_POS
1 104:
#define
AG903_SPC_APB_CLK_CTRL_IIC0_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_IIC0_POS
) 105:
#define
AG903_SPC_APB_CLK_CTRL_X2PP_POS
0 106:
#define
AG903_SPC_APB_CLK_CTRL_X2PP_MSK
(1<<
AG903_SPC_APB_CLK_CTRL_X2PP_POS
) 107: 108:
#define
AG903_SPC_AXI_CLK_CTRL1_OSP_POS
20 109:
#define
AG903_SPC_AXI_CLK_CTRL1_OSP_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_OSP_POS
) 110:
#define
AG903_SPC_AXI_CLK_CTRL1_ACP_POS
19 111:
#define
AG903_SPC_AXI_CLK_CTRL1_ACP_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_ACP_POS
) 112:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR6_POS
18 113:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR6_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_DDR6_POS
) 114:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR5_POS
17 115:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR5_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_DDR5_POS
) 116:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR4_POS
16 117:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR4_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_DDR4_POS
) 118:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR3_POS
15 119:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR3_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_DDR3_POS
) 120:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR2_POS
14 121:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR2_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_DDR2_POS
) 122:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR1_POS
13 123:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR1_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_DDR1_POS
) 124:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR0_POS
12 125:
#define
AG903_SPC_AXI_CLK_CTRL1_DDR0_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_DDR0_POS
) 126:
#define
AG903_SPC_AXI_CLK_CTRL1_PBD_POS
11 127:
#define
AG903_SPC_AXI_CLK_CTRL1_PBD_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_PBD_POS
) 128:
#define
AG903_SPC_AXI_CLK_CTRL1_X2PM_POS
10 129:
#define
AG903_SPC_AXI_CLK_CTRL1_X2PM_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_X2PM_POS
) 130:
#define
AG903_SPC_AXI_CLK_CTRL1_X2PP_POS
9 131:
#define
AG903_SPC_AXI_CLK_CTRL1_X2PP_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_X2PP_POS
) 132:
#define
AG903_SPC_AXI_CLK_CTRL1_X2H4_POS
8 133:
#define
AG903_SPC_AXI_CLK_CTRL1_X2H4_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_X2H4_POS
) 134:
#define
AG903_SPC_AXI_CLK_CTRL1_X2H3_POS
7 135:
#define
AG903_SPC_AXI_CLK_CTRL1_X2H3_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_X2H3_POS
) 136:
#define
AG903_SPC_AXI_CLK_CTRL1_X2H2_POS
6 137:
#define
AG903_SPC_AXI_CLK_CTRL1_X2H2_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_X2H2_POS
) 138:
#define
AG903_SPC_AXI_CLK_CTRL1_X2H1_POS
5 139:
#define
AG903_SPC_AXI_CLK_CTRL1_X2H1_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_X2H1_POS
) 140:
#define
AG903_SPC_AXI_CLK_CTRL1_X2H0_POS
4 141:
#define
AG903_SPC_AXI_CLK_CTRL1_X2H0_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_X2H0_POS
) 142:
#define
AG903_SPC_AXI_CLK_CTRL1_H2X_POS
3 143:
#define
AG903_SPC_AXI_CLK_CTRL1_H2X_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_H2X_POS
) 144:
#define
AG903_SPC_AXI_CLK_CTRL1_DMAC_POS
2 145:
#define
AG903_SPC_AXI_CLK_CTRL1_DMAC_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_DMAC_POS
) 146:
#define
AG903_SPC_AXI_CLK_CTRL1_IFW_POS
1 147:
#define
AG903_SPC_AXI_CLK_CTRL1_IFW_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_IFW_POS
) 148:
#define
AG903_SPC_AXI_CLK_CTRL1_IWM_POS
0 149:
#define
AG903_SPC_AXI_CLK_CTRL1_IWM_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL1_IWM_POS
) 150: 151:
#define
AG903_SPC_AXI_CLK_CTRL2_GFXC3_POS
12 152:
#define
AG903_SPC_AXI_CLK_CTRL2_GFXC3_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_GFXC3_POS
) 153:
#define
AG903_SPC_AXI_CLK_CTRL2_GFXC2_POS
11 154:
#define
AG903_SPC_AXI_CLK_CTRL2_GFXC2_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_GFXC2_POS
) 155:
#define
AG903_SPC_AXI_CLK_CTRL2_GFXC1_POS
10 156:
#define
AG903_SPC_AXI_CLK_CTRL2_GFXC1_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_GFXC1_POS
) 157:
#define
AG903_SPC_AXI_CLK_CTRL2_GVDC_POS
9 158:
#define
AG903_SPC_AXI_CLK_CTRL2_GVDC_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_GVDC_POS
) 159:
#define
AG903_SPC_AXI_CLK_CTRL2_VID_POS
8 160:
#define
AG903_SPC_AXI_CLK_CTRL2_VID_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_VID_POS
) 161:
#define
AG903_SPC_AXI_CLK_CTRL2_PGP_POS
7 162:
#define
AG903_SPC_AXI_CLK_CTRL2_PGP_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_PGP_POS
) 163:
#define
AG903_SPC_AXI_CLK_CTRL2_GVDB_POS
6 164:
#define
AG903_SPC_AXI_CLK_CTRL2_GVDB_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_GVDB_POS
) 165:
#define
AG903_SPC_AXI_CLK_CTRL2_HDA_POS
5 166:
#define
AG903_SPC_AXI_CLK_CTRL2_HDA_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_HDA_POS
) 167:
#define
AG903_SPC_AXI_CLK_CTRL2_JPG_POS
4 168:
#define
AG903_SPC_AXI_CLK_CTRL2_JPG_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_JPG_POS
) 169:
#define
AG903_SPC_AXI_CLK_CTRL2_GFX_POS
3 170:
#define
AG903_SPC_AXI_CLK_CTRL2_GFX_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_GFX_POS
) 171:
#define
AG903_SPC_AXI_CLK_CTRL2_EQS_POS
2 172:
#define
AG903_SPC_AXI_CLK_CTRL2_EQS_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_EQS_POS
) 173:
#define
AG903_SPC_AXI_CLK_CTRL2_DSP_POS
1 174:
#define
AG903_SPC_AXI_CLK_CTRL2_DSP_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_DSP_POS
) 175:
#define
AG903_SPC_AXI_CLK_CTRL2_DTA_POS
0 176:
#define
AG903_SPC_AXI_CLK_CTRL2_DTA_MSK
(1<<
AG903_SPC_AXI_CLK_CTRL2_DTA_POS
) 177: 178:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_X2H4_POS
2 179:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_X2H4_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_X2H4_POS
) 180:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_X2H2_POS
1 181:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_X2H2_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_X2H2_POS
) 182:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_SDMC_POS
0 183:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_SDMC_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_SDMC_POS
) 184: 185:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_CFC_POS
17 186:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_CFC_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_CFC_POS
) 187:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_H2P_POS
16 188:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_H2P_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_H2P_POS
) 189:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GFXC_POS
14 190:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GFXC_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_GFXC_POS
) 191:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GVD_POS
12 192:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GVD_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_GVD_POS
) 193:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_PGP_POS
11 194:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_PGP_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_PGP_POS
) 195:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_VID_POS
10 196:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_VID_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_VID_POS
) 197:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_TIM_POS
9 198:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_TIM_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_TIM_POS
) 199:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GPIO3_POS
8 200:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GPIO3_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_GPIO3_POS
) 201:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GPIO2_POS
7 202:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GPIO2_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_GPIO2_POS
) 203:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GPIO1_POS
6 204:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GPIO1_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_GPIO1_POS
) 205:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GPIO0_POS
5 206:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GPIO0_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_GPIO0_POS
) 207:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_BMU_POS
3 208:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_BMU_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_BMU_POS
) 209:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_SSC_POS
2 210:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_SSC_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_SSC_POS
) 211:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GFXR_POS
1 212:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_GFXR_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_GFXR_POS
) 213:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_X2PM_POS
0 214:
#define
AG903_SPC_APB_SDMC_CLK_CTRL_X2PM_MSK
(1<<
AG903_SPC_APB_SDMC_CLK_CTRL_X2PM_POS
) 215: 216:
#define
AG903_SPC_MISC_CLK_CTRL_HDA_POS
28 217:
#define
AG903_SPC_MISC_CLK_CTRL_HDA_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_HDA_POS
) 218:
#define
AG903_SPC_MISC_CLK_CTRL_SSP3_POS
27 219:
#define
AG903_SPC_MISC_CLK_CTRL_SSP3_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_SSP3_POS
) 220:
#define
AG903_SPC_MISC_CLK_CTRL_SSP2_POS
26 221:
#define
AG903_SPC_MISC_CLK_CTRL_SSP2_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_SSP2_POS
) 222:
#define
AG903_SPC_MISC_CLK_CTRL_SSP1_POS
25 223:
#define
AG903_SPC_MISC_CLK_CTRL_SSP1_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_SSP1_POS
) 224:
#define
AG903_SPC_MISC_CLK_CTRL_SSP0_POS
24 225:
#define
AG903_SPC_MISC_CLK_CTRL_SSP0_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_SSP0_POS
) 226:
#define
AG903_SPC_MISC_CLK_CTRL_PGPA3_POS
23 227:
#define
AG903_SPC_MISC_CLK_CTRL_PGPA3_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_PGPA3_POS
) 228:
#define
AG903_SPC_MISC_CLK_CTRL_PGPA2_POS
22 229:
#define
AG903_SPC_MISC_CLK_CTRL_PGPA2_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_PGPA2_POS
) 230:
#define
AG903_SPC_MISC_CLK_CTRL_PGPA1_POS
21 231:
#define
AG903_SPC_MISC_CLK_CTRL_PGPA1_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_PGPA1_POS
) 232:
#define
AG903_SPC_MISC_CLK_CTRL_PGPA0_POS
20 233:
#define
AG903_SPC_MISC_CLK_CTRL_PGPA0_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_PGPA0_POS
) 234:
#define
AG903_SPC_MISC_CLK_CTRL_PGPD1_POS
19 235:
#define
AG903_SPC_MISC_CLK_CTRL_PGPD1_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_PGPD1_POS
) 236:
#define
AG903_SPC_MISC_CLK_CTRL_PGPD0_POS
18 237:
#define
AG903_SPC_MISC_CLK_CTRL_PGPD0_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_PGPD0_POS
) 238:
#define
AG903_SPC_MISC_CLK_CTRL_VID1_POS
17 239:
#define
AG903_SPC_MISC_CLK_CTRL_VID1_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_VID1_POS
) 240:
#define
AG903_SPC_MISC_CLK_CTRL_VID0_POS
16 241:
#define
AG903_SPC_MISC_CLK_CTRL_VID0_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_VID0_POS
) 242:
#define
AG903_SPC_MISC_CLK_CTRL_ATA_POS
12 243:
#define
AG903_SPC_MISC_CLK_CTRL_ATA_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_ATA_POS
) 244:
#define
AG903_SPC_MISC_CLK_CTRL_VIA3_POS
7 245:
#define
AG903_SPC_MISC_CLK_CTRL_VIA3_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_VIA3_POS
) 246:
#define
AG903_SPC_MISC_CLK_CTRL_VIA2_POS
6 247:
#define
AG903_SPC_MISC_CLK_CTRL_VIA2_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_VIA2_POS
) 248:
#define
AG903_SPC_MISC_CLK_CTRL_VIA1_POS
5 249:
#define
AG903_SPC_MISC_CLK_CTRL_VIA1_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_VIA1_POS
) 250:
#define
AG903_SPC_MISC_CLK_CTRL_VIA0_POS
4 251:
#define
AG903_SPC_MISC_CLK_CTRL_VIA0_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_VIA0_POS
) 252:
#define
AG903_SPC_MISC_CLK_CTRL_TICK1_POS
3 253:
#define
AG903_SPC_MISC_CLK_CTRL_TICK1_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_TICK1_POS
) 254:
#define
AG903_SPC_MISC_CLK_CTRL_TICK0_POS
2 255:
#define
AG903_SPC_MISC_CLK_CTRL_TICK0_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_TICK0_POS
) 256:
#define
AG903_SPC_MISC_CLK_CTRL_SPI_POS
1 257:
#define
AG903_SPC_MISC_CLK_CTRL_SPI_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_SPI_POS
) 258:
#define
AG903_SPC_MISC_CLK_CTRL_SDC_POS
0 259:
#define
AG903_SPC_MISC_CLK_CTRL_SDC_MSK
(1<<
AG903_SPC_MISC_CLK_CTRL_SDC_POS
) 260: 261: 262:
#define
AG903_SPC_SOFTRESET_MASK1_DDR6_POS
30 263:
#define
AG903_SPC_SOFTRESET_MASK1_DDR6_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_DDR6_POS
) 264:
#define
AG903_SPC_SOFTRESET_MASK1_DDR5_POS
29 265:
#define
AG903_SPC_SOFTRESET_MASK1_DDR5_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_DDR5_POS
) 266:
#define
AG903_SPC_SOFTRESET_MASK1_DDR4_POS
28 267:
#define
AG903_SPC_SOFTRESET_MASK1_DDR4_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_DDR4_POS
) 268:
#define
AG903_SPC_SOFTRESET_MASK1_DDR3_POS
27 269:
#define
AG903_SPC_SOFTRESET_MASK1_DDR3_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_DDR3_POS
) 270:
#define
AG903_SPC_SOFTRESET_MASK1_DDR2_POS
26 271:
#define
AG903_SPC_SOFTRESET_MASK1_DDR2_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_DDR2_POS
) 272:
#define
AG903_SPC_SOFTRESET_MASK1_DDR1_POS
25 273:
#define
AG903_SPC_SOFTRESET_MASK1_DDR1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_DDR1_POS
) 274:
#define
AG903_SPC_SOFTRESET_MASK1_DDR0_POS
24 275:
#define
AG903_SPC_SOFTRESET_MASK1_DDR0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_DDR0_POS
) 276:
#define
AG903_SPC_SOFTRESET_MASK1_AXIC_POS
23 277:
#define
AG903_SPC_SOFTRESET_MASK1_AXIC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_AXIC_POS
) 278:
#define
AG903_SPC_SOFTRESET_MASK1_VID_POS
22 279:
#define
AG903_SPC_SOFTRESET_MASK1_VID_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_VID_POS
) 280:
#define
AG903_SPC_SOFTRESET_MASK1_GVD_POS
21 281:
#define
AG903_SPC_SOFTRESET_MASK1_GVD_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_GVD_POS
) 282:
#define
AG903_SPC_SOFTRESET_MASK1_ACP_POS
20 283:
#define
AG903_SPC_SOFTRESET_MASK1_ACP_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_ACP_POS
) 284:
#define
AG903_SPC_SOFTRESET_MASK1_PGP_POS
19 285:
#define
AG903_SPC_SOFTRESET_MASK1_PGP_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_PGP_POS
) 286:
#define
AG903_SPC_SOFTRESET_MASK1_HDA_POS
18 287:
#define
AG903_SPC_SOFTRESET_MASK1_HDA_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_HDA_POS
) 288:
#define
AG903_SPC_SOFTRESET_MASK1_JPG_POS
17 289:
#define
AG903_SPC_SOFTRESET_MASK1_JPG_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_JPG_POS
) 290:
#define
AG903_SPC_SOFTRESET_MASK1_PBD_POS
16 291:
#define
AG903_SPC_SOFTRESET_MASK1_PBD_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_PBD_POS
) 292:
#define
AG903_SPC_SOFTRESET_MASK1_GFX_POS
15 293:
#define
AG903_SPC_SOFTRESET_MASK1_GFX_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_GFX_POS
) 294:
#define
AG903_SPC_SOFTRESET_MASK1_EQS_POS
14 295:
#define
AG903_SPC_SOFTRESET_MASK1_EQS_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_EQS_POS
) 296:
#define
AG903_SPC_SOFTRESET_MASK1_DSP_POS
13 297:
#define
AG903_SPC_SOFTRESET_MASK1_DSP_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_DSP_POS
) 298:
#define
AG903_SPC_SOFTRESET_MASK1_DTA_POS
12 299:
#define
AG903_SPC_SOFTRESET_MASK1_DTA_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_DTA_POS
) 300:
#define
AG903_SPC_SOFTRESET_MASK1_SPC_POS
11 301:
#define
AG903_SPC_SOFTRESET_MASK1_SPC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_SPC_POS
) 302:
#define
AG903_SPC_SOFTRESET_MASK1_X2PM_POS
10 303:
#define
AG903_SPC_SOFTRESET_MASK1_X2PM_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_X2PM_POS
) 304:
#define
AG903_SPC_SOFTRESET_MASK1_X2PP_POS
9 305:
#define
AG903_SPC_SOFTRESET_MASK1_X2PP_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_X2PP_POS
) 306:
#define
AG903_SPC_SOFTRESET_MASK1_X2H4_POS
8 307:
#define
AG903_SPC_SOFTRESET_MASK1_X2H4_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_X2H4_POS
) 308:
#define
AG903_SPC_SOFTRESET_MASK1_X2H3_POS
7 309:
#define
AG903_SPC_SOFTRESET_MASK1_X2H3_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_X2H3_POS
) 310:
#define
AG903_SPC_SOFTRESET_MASK1_X2H2_POS
6 311:
#define
AG903_SPC_SOFTRESET_MASK1_X2H2_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_X2H2_POS
) 312:
#define
AG903_SPC_SOFTRESET_MASK1_X2H1_POS
5 313:
#define
AG903_SPC_SOFTRESET_MASK1_X2H1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_X2H1_POS
) 314:
#define
AG903_SPC_SOFTRESET_MASK1_X2H0_POS
4 315:
#define
AG903_SPC_SOFTRESET_MASK1_X2H0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_X2H0_POS
) 316:
#define
AG903_SPC_SOFTRESET_MASK1_H2X_POS
3 317:
#define
AG903_SPC_SOFTRESET_MASK1_H2X_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_H2X_POS
) 318:
#define
AG903_SPC_SOFTRESET_MASK1_DMAC_POS
2 319:
#define
AG903_SPC_SOFTRESET_MASK1_DMAC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_DMAC_POS
) 320:
#define
AG903_SPC_SOFTRESET_MASK1_IFW_POS
1 321:
#define
AG903_SPC_SOFTRESET_MASK1_IFW_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_IFW_POS
) 322:
#define
AG903_SPC_SOFTRESET_MASK1_IWM_POS
0 323:
#define
AG903_SPC_SOFTRESET_MASK1_IWM_MSK
(1<<
AG903_SPC_SOFTRESET_MASK1_IWM_POS
) 324: 325:
#define
AG903_SPC_SOFTRESET_MASK2_ATA_POS
25 326:
#define
AG903_SPC_SOFTRESET_MASK2_ATA_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_ATA_POS
) 327:
#define
AG903_SPC_SOFTRESET_MASK2_SMC_POS
24 328:
#define
AG903_SPC_SOFTRESET_MASK2_SMC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_SMC_POS
) 329:
#define
AG903_SPC_SOFTRESET_MASK2_H2P_POS
23 330:
#define
AG903_SPC_SOFTRESET_MASK2_H2P_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_H2P_POS
) 331:
#define
AG903_SPC_SOFTRESET_MASK2_SPI_POS
22 332:
#define
AG903_SPC_SOFTRESET_MASK2_SPI_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_SPI_POS
) 333:
#define
AG903_SPC_SOFTRESET_MASK2_EBI_POS
21 334:
#define
AG903_SPC_SOFTRESET_MASK2_EBI_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_EBI_POS
) 335:
#define
AG903_SPC_SOFTRESET_MASK2_BSC_POS
20 336:
#define
AG903_SPC_SOFTRESET_MASK2_BSC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_BSC_POS
) 337:
#define
AG903_SPC_SOFTRESET_MASK2_X2H3_POS
19 338:
#define
AG903_SPC_SOFTRESET_MASK2_X2H3_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_X2H3_POS
) 339:
#define
AG903_SPC_SOFTRESET_MASK2_X2H1_POS
18 340:
#define
AG903_SPC_SOFTRESET_MASK2_X2H1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_X2H1_POS
) 341:
#define
AG903_SPC_SOFTRESET_MASK2_HBCB_POS
17 342:
#define
AG903_SPC_SOFTRESET_MASK2_HBCB_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_HBCB_POS
) 343:
#define
AG903_SPC_SOFTRESET_MASK2_HBCP_POS
16 344:
#define
AG903_SPC_SOFTRESET_MASK2_HBCP_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_HBCP_POS
) 345:
#define
AG903_SPC_SOFTRESET_MASK2_USBP_POS
13 346:
#define
AG903_SPC_SOFTRESET_MASK2_USBP_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_USBP_POS
) 347:
#define
AG903_SPC_SOFTRESET_MASK2_SPC_POS
12 348:
#define
AG903_SPC_SOFTRESET_MASK2_SPC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_SPC_POS
) 349:
#define
AG903_SPC_SOFTRESET_MASK2_DDR7_POS
11 350:
#define
AG903_SPC_SOFTRESET_MASK2_DDR7_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_DDR7_POS
) 351:
#define
AG903_SPC_SOFTRESET_MASK2_USBC_POS
10 352:
#define
AG903_SPC_SOFTRESET_MASK2_USBC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_USBC_POS
) 353:
#define
AG903_SPC_SOFTRESET_MASK2_SDC_POS
9 354:
#define
AG903_SPC_SOFTRESET_MASK2_SDC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_SDC_POS
) 355:
#define
AG903_SPC_SOFTRESET_MASK2_ETH_POS
8 356:
#define
AG903_SPC_SOFTRESET_MASK2_ETH_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_ETH_POS
) 357:
#define
AG903_SPC_SOFTRESET_MASK2_H2X_POS
6 358:
#define
AG903_SPC_SOFTRESET_MASK2_H2X_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_H2X_POS
) 359:
#define
AG903_SPC_SOFTRESET_MASK2_X2H0_POS
5 360:
#define
AG903_SPC_SOFTRESET_MASK2_X2H0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_X2H0_POS
) 361:
#define
AG903_SPC_SOFTRESET_MASK2_ALS_POS
4 362:
#define
AG903_SPC_SOFTRESET_MASK2_ALS_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_ALS_POS
) 363:
#define
AG903_SPC_SOFTRESET_MASK2_CA5H_POS
3 364:
#define
AG903_SPC_SOFTRESET_MASK2_CA5H_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_CA5H_POS
) 365:
#define
AG903_SPC_SOFTRESET_MASK2_HBCM_POS
1 366:
#define
AG903_SPC_SOFTRESET_MASK2_HBCM_MSK
(1<<
AG903_SPC_SOFTRESET_MASK2_HBCM_POS
) 367: 368:
#define
AG903_SPC_SOFTRESET_MASK3_CA5PORT_POS
31 369:
#define
AG903_SPC_SOFTRESET_MASK3_CA5PORT_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_CA5PORT_POS
) 370:
#define
AG903_SPC_SOFTRESET_MASK3_CA5T_POS
30 371:
#define
AG903_SPC_SOFTRESET_MASK3_CA5T_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_CA5T_POS
) 372:
#define
AG903_SPC_SOFTRESET_MASK3_CA5PERI_POS
29 373:
#define
AG903_SPC_SOFTRESET_MASK3_CA5PERI_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_CA5PERI_POS
) 374:
#define
AG903_SPC_SOFTRESET_MASK3_CA5SOCD_POS
28 375:
#define
AG903_SPC_SOFTRESET_MASK3_CA5SOCD_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_CA5SOCD_POS
) 376:
#define
AG903_SPC_SOFTRESET_MASK3_CA5SCU_POS
27 377:
#define
AG903_SPC_SOFTRESET_MASK3_CA5SCU_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_CA5SCU_POS
) 378:
#define
AG903_SPC_SOFTRESET_MASK3_CA5DBG_POS
26 379:
#define
AG903_SPC_SOFTRESET_MASK3_CA5DBG_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_CA5DBG_POS
) 380:
#define
AG903_SPC_SOFTRESET_MASK3_CA5CPU_POS
25 381:
#define
AG903_SPC_SOFTRESET_MASK3_CA5CPU_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_CA5CPU_POS
) 382:
#define
AG903_SPC_SOFTRESET_MASK3_CA5ETM_POS
24 383:
#define
AG903_SPC_SOFTRESET_MASK3_CA5ETM_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_CA5ETM_POS
) 384:
#define
AG903_SPC_SOFTRESET_MASK3_CA5PSYS_POS
23 385:
#define
AG903_SPC_SOFTRESET_MASK3_CA5PSYS_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_CA5PSYS_POS
) 386:
#define
AG903_SPC_SOFTRESET_MASK3_H2X_POS
22 387:
#define
AG903_SPC_SOFTRESET_MASK3_H2X_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_H2X_POS
) 388:
#define
AG903_SPC_SOFTRESET_MASK3_IFW_POS
21 389:
#define
AG903_SPC_SOFTRESET_MASK3_IFW_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_IFW_POS
) 390:
#define
AG903_SPC_SOFTRESET_MASK3_IWM_POS
20 391:
#define
AG903_SPC_SOFTRESET_MASK3_IWM_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_IWM_POS
) 392:
#define
AG903_SPC_SOFTRESET_MASK3_X2H4_POS
19 393:
#define
AG903_SPC_SOFTRESET_MASK3_X2H4_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_X2H4_POS
) 394:
#define
AG903_SPC_SOFTRESET_MASK3_X2H3_POS
18 395:
#define
AG903_SPC_SOFTRESET_MASK3_X2H3_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_X2H3_POS
) 396:
#define
AG903_SPC_SOFTRESET_MASK3_X2H2_POS
17 397:
#define
AG903_SPC_SOFTRESET_MASK3_X2H2_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_X2H2_POS
) 398:
#define
AG903_SPC_SOFTRESET_MASK3_X2H1_POS
16 399:
#define
AG903_SPC_SOFTRESET_MASK3_X2H1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_X2H1_POS
) 400:
#define
AG903_SPC_SOFTRESET_MASK3_X2H0_POS
15 401:
#define
AG903_SPC_SOFTRESET_MASK3_X2H0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_X2H0_POS
) 402:
#define
AG903_SPC_SOFTRESET_MASK3_AXIC_POS
14 403:
#define
AG903_SPC_SOFTRESET_MASK3_AXIC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_AXIC_POS
) 404:
#define
AG903_SPC_SOFTRESET_MASK3_DDR_POS
13 405:
#define
AG903_SPC_SOFTRESET_MASK3_DDR_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_DDR_POS
) 406:
#define
AG903_SPC_SOFTRESET_MASK3_DMAC_POS
12 407:
#define
AG903_SPC_SOFTRESET_MASK3_DMAC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_DMAC_POS
) 408:
#define
AG903_SPC_SOFTRESET_MASK3_WDT_POS
11 409:
#define
AG903_SPC_SOFTRESET_MASK3_WDT_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_WDT_POS
) 410:
#define
AG903_SPC_SOFTRESET_MASK3_SSP3_POS
10 411:
#define
AG903_SPC_SOFTRESET_MASK3_SSP3_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_SSP3_POS
) 412:
#define
AG903_SPC_SOFTRESET_MASK3_SSP2_POS
9 413:
#define
AG903_SPC_SOFTRESET_MASK3_SSP2_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_SSP2_POS
) 414:
#define
AG903_SPC_SOFTRESET_MASK3_SSP1_POS
8 415:
#define
AG903_SPC_SOFTRESET_MASK3_SSP1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_SSP1_POS
) 416:
#define
AG903_SPC_SOFTRESET_MASK3_SSP0_POS
7 417:
#define
AG903_SPC_SOFTRESET_MASK3_SSP0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_SSP0_POS
) 418:
#define
AG903_SPC_SOFTRESET_MASK3_UART3_POS
6 419:
#define
AG903_SPC_SOFTRESET_MASK3_UART3_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_UART3_POS
) 420:
#define
AG903_SPC_SOFTRESET_MASK3_UART2_POS
5 421:
#define
AG903_SPC_SOFTRESET_MASK3_UART2_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_UART2_POS
) 422:
#define
AG903_SPC_SOFTRESET_MASK3_UART1_POS
4 423:
#define
AG903_SPC_SOFTRESET_MASK3_UART1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_UART1_POS
) 424:
#define
AG903_SPC_SOFTRESET_MASK3_UART0_POS
3 425:
#define
AG903_SPC_SOFTRESET_MASK3_UART0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_UART0_POS
) 426:
#define
AG903_SPC_SOFTRESET_MASK3_IIC1_POS
2 427:
#define
AG903_SPC_SOFTRESET_MASK3_IIC1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_IIC1_POS
) 428:
#define
AG903_SPC_SOFTRESET_MASK3_IIC0_POS
1 429:
#define
AG903_SPC_SOFTRESET_MASK3_IIC0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_IIC0_POS
) 430:
#define
AG903_SPC_SOFTRESET_MASK3_X2PP_POS
0 431:
#define
AG903_SPC_SOFTRESET_MASK3_X2PP_MSK
(1<<
AG903_SPC_SOFTRESET_MASK3_X2PP_POS
) 432: 433:
#define
AG903_SPC_SOFTRESET_MASK4_CFC_POS
25 434:
#define
AG903_SPC_SOFTRESET_MASK4_CFC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_CFC_POS
) 435:
#define
AG903_SPC_SOFTRESET_MASK4_H2P_POS
24 436:
#define
AG903_SPC_SOFTRESET_MASK4_H2P_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_H2P_POS
) 437:
#define
AG903_SPC_SOFTRESET_MASK4_X2H4_POS
18 438:
#define
AG903_SPC_SOFTRESET_MASK4_X2H4_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_X2H4_POS
) 439:
#define
AG903_SPC_SOFTRESET_MASK4_X2H2_POS
17 440:
#define
AG903_SPC_SOFTRESET_MASK4_X2H2_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_X2H2_POS
) 441:
#define
AG903_SPC_SOFTRESET_MASK4_SDMC_POS
16 442:
#define
AG903_SPC_SOFTRESET_MASK4_SDMC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_SDMC_POS
) 443:
#define
AG903_SPC_SOFTRESET_MASK4_BMU_POS
12 444:
#define
AG903_SPC_SOFTRESET_MASK4_BMU_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_BMU_POS
) 445:
#define
AG903_SPC_SOFTRESET_MASK4_GVD_POS
11 446:
#define
AG903_SPC_SOFTRESET_MASK4_GVD_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_GVD_POS
) 447:
#define
AG903_SPC_SOFTRESET_MASK4_PGP_POS
10 448:
#define
AG903_SPC_SOFTRESET_MASK4_PGP_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_PGP_POS
) 449:
#define
AG903_SPC_SOFTRESET_MASK4_SSC_POS
9 450:
#define
AG903_SPC_SOFTRESET_MASK4_SSC_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_SSC_POS
) 451:
#define
AG903_SPC_SOFTRESET_MASK4_VID_POS
8 452:
#define
AG903_SPC_SOFTRESET_MASK4_VID_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_VID_POS
) 453:
#define
AG903_SPC_SOFTRESET_MASK4_TIM_POS
7 454:
#define
AG903_SPC_SOFTRESET_MASK4_TIM_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_TIM_POS
) 455:
#define
AG903_SPC_SOFTRESET_MASK4_GPIO3_POS
6 456:
#define
AG903_SPC_SOFTRESET_MASK4_GPIO3_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_GPIO3_POS
) 457:
#define
AG903_SPC_SOFTRESET_MASK4_GPIO2_POS
5 458:
#define
AG903_SPC_SOFTRESET_MASK4_GPIO2_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_GPIO2_POS
) 459:
#define
AG903_SPC_SOFTRESET_MASK4_GPIO1_POS
4 460:
#define
AG903_SPC_SOFTRESET_MASK4_GPIO1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_GPIO1_POS
) 461:
#define
AG903_SPC_SOFTRESET_MASK4_GPIO0_POS
3 462:
#define
AG903_SPC_SOFTRESET_MASK4_GPIO0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_GPIO0_POS
) 463:
#define
AG903_SPC_SOFTRESET_MASK4_GFX_POS
2 464:
#define
AG903_SPC_SOFTRESET_MASK4_GFX_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_GFX_POS
) 465:
#define
AG903_SPC_SOFTRESET_MASK4_X2PM_POS
0 466:
#define
AG903_SPC_SOFTRESET_MASK4_X2PM_MSK
(1<<
AG903_SPC_SOFTRESET_MASK4_X2PM_POS
) 467: 468:
#define
AG903_SPC_SOFTRESET_MASK5_VIA3_POS
28 469:
#define
AG903_SPC_SOFTRESET_MASK5_VIA3_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_VIA3_POS
) 470:
#define
AG903_SPC_SOFTRESET_MASK5_VIA2_POS
27 471:
#define
AG903_SPC_SOFTRESET_MASK5_VIA2_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_VIA2_POS
) 472:
#define
AG903_SPC_SOFTRESET_MASK5_VIA1_POS
26 473:
#define
AG903_SPC_SOFTRESET_MASK5_VIA1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_VIA1_POS
) 474:
#define
AG903_SPC_SOFTRESET_MASK5_VIA0_POS
25 475:
#define
AG903_SPC_SOFTRESET_MASK5_VIA0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_VIA0_POS
) 476:
#define
AG903_SPC_SOFTRESET_MASK5_TICK1_POS
24 477:
#define
AG903_SPC_SOFTRESET_MASK5_TICK1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_TICK1_POS
) 478:
#define
AG903_SPC_SOFTRESET_MASK5_TICK0_POS
23 479:
#define
AG903_SPC_SOFTRESET_MASK5_TICK0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_TICK0_POS
) 480:
#define
AG903_SPC_SOFTRESET_MASK5_DSPC1_POS
22 481:
#define
AG903_SPC_SOFTRESET_MASK5_DSPC1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_DSPC1_POS
) 482:
#define
AG903_SPC_SOFTRESET_MASK5_DSPC0_POS
21 483:
#define
AG903_SPC_SOFTRESET_MASK5_DSPC0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_DSPC0_POS
) 484:
#define
AG903_SPC_SOFTRESET_MASK5_TDM3_POS
20 485:
#define
AG903_SPC_SOFTRESET_MASK5_TDM3_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_TDM3_POS
) 486:
#define
AG903_SPC_SOFTRESET_MASK5_TDM2_POS
19 487:
#define
AG903_SPC_SOFTRESET_MASK5_TDM2_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_TDM2_POS
) 488:
#define
AG903_SPC_SOFTRESET_MASK5_TDM1_POS
18 489:
#define
AG903_SPC_SOFTRESET_MASK5_TDM1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_TDM1_POS
) 490:
#define
AG903_SPC_SOFTRESET_MASK5_TDM0_POS
17 491:
#define
AG903_SPC_SOFTRESET_MASK5_TDM0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_TDM0_POS
) 492:
#define
AG903_SPC_SOFTRESET_MASK5_VIDC1_POS
16 493:
#define
AG903_SPC_SOFTRESET_MASK5_VIDC1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_VIDC1_POS
) 494:
#define
AG903_SPC_SOFTRESET_MASK5_VIDC0_POS
15 495:
#define
AG903_SPC_SOFTRESET_MASK5_VIDC0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_VIDC0_POS
) 496:
#define
AG903_SPC_SOFTRESET_MASK5_PGPC1_POS
14 497:
#define
AG903_SPC_SOFTRESET_MASK5_PGPC1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_PGPC1_POS
) 498:
#define
AG903_SPC_SOFTRESET_MASK5_PGPC0_POS
13 499:
#define
AG903_SPC_SOFTRESET_MASK5_PGPC0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_PGPC0_POS
) 500:
#define
AG903_SPC_SOFTRESET_MASK5_PGPA3_POS
12 501:
#define
AG903_SPC_SOFTRESET_MASK5_PGPA3_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_PGPA3_POS
) 502:
#define
AG903_SPC_SOFTRESET_MASK5_PGPA2_POS
11 503:
#define
AG903_SPC_SOFTRESET_MASK5_PGPA2_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_PGPA2_POS
) 504:
#define
AG903_SPC_SOFTRESET_MASK5_PGPA1_POS
10 505:
#define
AG903_SPC_SOFTRESET_MASK5_PGPA1_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_PGPA1_POS
) 506:
#define
AG903_SPC_SOFTRESET_MASK5_PGPA0_POS
9 507:
#define
AG903_SPC_SOFTRESET_MASK5_PGPA0_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_PGPA0_POS
) 508:
#define
AG903_SPC_SOFTRESET_MASK5_HDA_POS
8 509:
#define
AG903_SPC_SOFTRESET_MASK5_HDA_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_HDA_POS
) 510:
#define
AG903_SPC_SOFTRESET_MASK5_USBPPOR_POS
7 511:
#define
AG903_SPC_SOFTRESET_MASK5_USBPPOR_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_USBPPOR_POS
) 512:
#define
AG903_SPC_SOFTRESET_MASK5_USBPHY_POS
6 513:
#define
AG903_SPC_SOFTRESET_MASK5_USBPHY_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_USBPHY_POS
) 514:
#define
AG903_SPC_SOFTRESET_MASK5_DDRPPLL_POS
4 515:
#define
AG903_SPC_SOFTRESET_MASK5_DDRPPLL_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_DDRPPLL_POS
) 516:
#define
AG903_SPC_SOFTRESET_MASK5_DDRPUB_POS
3 517:
#define
AG903_SPC_SOFTRESET_MASK5_DDRPUB_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_DDRPUB_POS
) 518:
#define
AG903_SPC_SOFTRESET_MASK5_DDRPLB_POS
2 519:
#define
AG903_SPC_SOFTRESET_MASK5_DDRPLB_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_DDRPLB_POS
) 520:
#define
AG903_SPC_SOFTRESET_MASK5_DDRPCA_POS
1 521:
#define
AG903_SPC_SOFTRESET_MASK5_DDRPCA_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_DDRPCA_POS
) 522:
#define
AG903_SPC_SOFTRESET_MASK5_DDRPCMP_POS
0 523:
#define
AG903_SPC_SOFTRESET_MASK5_DDRPCMP_MSK
(1<<
AG903_SPC_SOFTRESET_MASK5_DDRPCMP_POS
) 524: 525:
#endif
Copyright (c) 2017-2025 Axell Corporation. All rights reserved.
内容
|
インデックス
|
ホーム