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AG903_bmureg.h

BMU Register Definition

BMU Register Definition

none

AXELL CORPORATION

2017_10_20 Auto-generated.

1: 8: 9: 13: 14: #ifndef _AG903_BMU_REGMAP_H_ 15: #define _AG903_BMU_REGMAP_H_ 16: 17: 18: #include "AG903_regmap.h" 19: 20: #ifndef __I 21: 22: #define __I volatile const 23: #endif 24: #ifndef __O 25: 26: #define __O volatile 27: #endif 28: #ifndef __IO 29: 30: #define __IO volatile 31: #endif 32: 33: 34: typedef struct { 35: 36: union { 37: __IO uint32_t CTRL; 38: 39: struct { 40: __IO uint32_t EN : 1; 41: } CTRL_bits; 42: }; 43: 44: union { 45: __IO uint32_t MOD; 46: 47: struct { 48: __IO uint32_t SRC : 5; 49: uint32_t : 11; 50: __IO uint32_t MGR : 2; 51: __IO uint32_t INI : 1; 52: } MOD_bits; 53: }; 54: 55: union { 56: __IO uint32_t SINKMODULE; 57: 58: struct { 59: __IO uint32_t SINK0 : 1; 60: __IO uint32_t SINK1 : 1; 61: __IO uint32_t SINK2 : 1; 62: __IO uint32_t SINK3 : 1; 63: __IO uint32_t SINK4 : 1; 64: __IO uint32_t SINK5 : 1; 65: __IO uint32_t SINK6 : 1; 66: __IO uint32_t SINK7 : 1; 67: __IO uint32_t SINK8 : 1; 68: __IO uint32_t SINK9 : 1; 69: __IO uint32_t SINK10 : 1; 70: __IO uint32_t SINK11 : 1; 71: __IO uint32_t SINK12 : 1; 72: __IO uint32_t SINK13 : 1; 73: __IO uint32_t SINK14 : 1; 74: __IO uint32_t SINK15 : 1; 75: } SINKMODULE_bits; 76: }; 77: 78: union { 79: __I uint32_t SINKSTAT; 80: 81: struct { 82: __I uint32_t SINK0 : 1; 83: __I uint32_t SINK1 : 1; 84: __I uint32_t SINK2 : 1; 85: __I uint32_t SINK3 : 1; 86: __I uint32_t SINK4 : 1; 87: __I uint32_t SINK5 : 1; 88: __I uint32_t SINK6 : 1; 89: __I uint32_t SINK7 : 1; 90: __I uint32_t SINK8 : 1; 91: __I uint32_t SINK9 : 1; 92: __I uint32_t SINK10 : 1; 93: __I uint32_t SINK11 : 1; 94: __I uint32_t SINK12 : 1; 95: __I uint32_t SINK13 : 1; 96: __I uint32_t SINK14 : 1; 97: __I uint32_t SINK15 : 1; 98: } SINKSTAT_bits; 99: }; 100: 101: union { 102: __IO uint32_t BASEADR; 103: 104: struct { 105: uint32_t : 7; 106: __IO uint32_t ADR : 22; 107: } BASEADR_bits; 108: }; 109: 110: union { 111: __IO uint32_t STRIDE; 112: 113: struct { 114: uint32_t : 7; 115: __IO uint32_t STRIDE : 18; 116: } STRIDE_bits; 117: }; 118: 119: union { 120: __IO uint32_t BUFNUM; 121: 122: struct { 123: __IO uint32_t NUM : 3; 124: } BUFNUM_bits; 125: }; 126: 127: union { 128: __I uint32_t STAT; 129: 130: struct { 131: __I uint32_t WNUM : 3; 132: uint32_t : 5; 133: __I uint32_t WBSY : 1; 134: __I uint32_t WWA : 1; 135: __I uint32_t FULL : 1; 136: uint32_t : 5; 137: __I uint32_t RNUM : 3; 138: uint32_t : 5; 139: __I uint32_t RBSY : 1; 140: __I uint32_t RWA : 1; 141: __I uint32_t EMPTY : 1; 142: __I uint32_t VAL : 1; 143: } STAT_bits; 144: }; 145: 146: 147: }AG903_BMUn_Type; 148: 149: #define AG903_BMUn(ch) ((volatile AG903_BMUn_Type *)(AG903_BMU0_BASE + 0x40 * ch)) 150: #define AG903_BMUn_CTRL(ch) AG903_BMUn(ch)->CTRL 151: #define AG903_BMUn_MOD(ch) AG903_BMUn(ch)->MOD 152: #define AG903_BMUn_SINKMODULE(ch) AG903_BMUn(ch)->SINKMODULE 153: #define AG903_BMUn_SINKSTAT(ch) AG903_BMUn(ch)->SINKSTAT 154: #define AG903_BMUn_BASEADR(ch) AG903_BMUn(ch)->BASEADR 155: #define AG903_BMUn_STRIDE(ch) AG903_BMUn(ch)->STRIDE 156: #define AG903_BMUn_BUFNUM(ch) AG903_BMUn(ch)->BUFNUM 157: #define AG903_BMUn_STAT(ch) AG903_BMUn(ch)->STAT 158: 159: #define AG903_BMU0 ((volatile AG903_BMUn_Type *) AG903_BMU0_BASE) 160: #define AG903_BMU1 ((volatile AG903_BMUn_Type *) AG903_BMU1_BASE) 161: #define AG903_BMU2 ((volatile AG903_BMUn_Type *) AG903_BMU2_BASE) 162: #define AG903_BMU3 ((volatile AG903_BMUn_Type *) AG903_BMU3_BASE) 163: #define AG903_BMU4 ((volatile AG903_BMUn_Type *) AG903_BMU4_BASE) 164: #define AG903_BMU5 ((volatile AG903_BMUn_Type *) AG903_BMU5_BASE) 165: #define AG903_BMU6 ((volatile AG903_BMUn_Type *) AG903_BMU6_BASE) 166: #define AG903_BMU7 ((volatile AG903_BMUn_Type *) AG903_BMU7_BASE) 167: #define AG903_BMU8 ((volatile AG903_BMUn_Type *) AG903_BMU8_BASE) 168: #define AG903_BMU9 ((volatile AG903_BMUn_Type *) AG903_BMU9_BASE) 169: #define AG903_BMU10 ((volatile AG903_BMUn_Type *) AG903_BMU10_BASE) 170: #define AG903_BMU11 ((volatile AG903_BMUn_Type *) AG903_BMU11_BASE) 171: #define AG903_BMU12 ((volatile AG903_BMUn_Type *) AG903_BMU12_BASE) 172: #define AG903_BMU13 ((volatile AG903_BMUn_Type *) AG903_BMU13_BASE) 173: #define AG903_BMU14 ((volatile AG903_BMUn_Type *) AG903_BMU14_BASE) 174: #define AG903_BMU15 ((volatile AG903_BMUn_Type *) AG903_BMU15_BASE) 175: 176: 177: #define AG903_BMUn_CTRL_EN_POS 0 178: #define AG903_BMUn_CTRL_EN_MSK (0x1UL << AG903_BMUn_CTRL_EN_POS) 179: 180: #define AG903_BMUn_MOD_SRC_POS 0 181: #define AG903_BMUn_MOD_SRC_MSK (0x1fUL << AG903_BMUn_MOD_SRC_POS) 182: #define AG903_BMUn_MOD_MGR_POS 16 183: #define AG903_BMUn_MOD_MGR_MSK (0x3UL << AG903_BMUn_MOD_MGR_POS) 184: #define AG903_BMUn_MOD_INI_POS 18 185: #define AG903_BMUn_MOD_INI_MSK (0x1UL << AG903_BMUn_MOD_INI_POS) 186: 187: #define AG903_BMUn_SINKMODULE_SINK0_POS 0 188: #define AG903_BMUn_SINKMODULE_SINK0_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK0_POS) 189: #define AG903_BMUn_SINKMODULE_SINK1_POS 1 190: #define AG903_BMUn_SINKMODULE_SINK1_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK1_POS) 191: #define AG903_BMUn_SINKMODULE_SINK2_POS 2 192: #define AG903_BMUn_SINKMODULE_SINK2_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK2_POS) 193: #define AG903_BMUn_SINKMODULE_SINK3_POS 3 194: #define AG903_BMUn_SINKMODULE_SINK3_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK3_POS) 195: #define AG903_BMUn_SINKMODULE_SINK4_POS 4 196: #define AG903_BMUn_SINKMODULE_SINK4_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK4_POS) 197: #define AG903_BMUn_SINKMODULE_SINK5_POS 5 198: #define AG903_BMUn_SINKMODULE_SINK5_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK5_POS) 199: #define AG903_BMUn_SINKMODULE_SINK6_POS 6 200: #define AG903_BMUn_SINKMODULE_SINK6_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK6_POS) 201: #define AG903_BMUn_SINKMODULE_SINK7_POS 7 202: #define AG903_BMUn_SINKMODULE_SINK7_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK7_POS) 203: #define AG903_BMUn_SINKMODULE_SINK8_POS 8 204: #define AG903_BMUn_SINKMODULE_SINK8_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK8_POS) 205: #define AG903_BMUn_SINKMODULE_SINK9_POS 9 206: #define AG903_BMUn_SINKMODULE_SINK9_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK9_POS) 207: #define AG903_BMUn_SINKMODULE_SINK10_POS 10 208: #define AG903_BMUn_SINKMODULE_SINK10_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK10_POS) 209: #define AG903_BMUn_SINKMODULE_SINK11_POS 11 210: #define AG903_BMUn_SINKMODULE_SINK11_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK11_POS) 211: #define AG903_BMUn_SINKMODULE_SINK12_POS 12 212: #define AG903_BMUn_SINKMODULE_SINK12_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK12_POS) 213: #define AG903_BMUn_SINKMODULE_SINK13_POS 13 214: #define AG903_BMUn_SINKMODULE_SINK13_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK13_POS) 215: #define AG903_BMUn_SINKMODULE_SINK14_POS 14 216: #define AG903_BMUn_SINKMODULE_SINK14_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK14_POS) 217: #define AG903_BMUn_SINKMODULE_SINK15_POS 15 218: #define AG903_BMUn_SINKMODULE_SINK15_MSK (0x1UL << AG903_BMUn_SINKMODULE_SINK15_POS) 219: 220: #define AG903_BMUn_SINKSTAT_SINK0_POS 0 221: #define AG903_BMUn_SINKSTAT_SINK0_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK0_POS) 222: #define AG903_BMUn_SINKSTAT_SINK1_POS 1 223: #define AG903_BMUn_SINKSTAT_SINK1_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK1_POS) 224: #define AG903_BMUn_SINKSTAT_SINK2_POS 2 225: #define AG903_BMUn_SINKSTAT_SINK2_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK2_POS) 226: #define AG903_BMUn_SINKSTAT_SINK3_POS 3 227: #define AG903_BMUn_SINKSTAT_SINK3_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK3_POS) 228: #define AG903_BMUn_SINKSTAT_SINK4_POS 4 229: #define AG903_BMUn_SINKSTAT_SINK4_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK4_POS) 230: #define AG903_BMUn_SINKSTAT_SINK5_POS 5 231: #define AG903_BMUn_SINKSTAT_SINK5_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK5_POS) 232: #define AG903_BMUn_SINKSTAT_SINK6_POS 6 233: #define AG903_BMUn_SINKSTAT_SINK6_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK6_POS) 234: #define AG903_BMUn_SINKSTAT_SINK7_POS 7 235: #define AG903_BMUn_SINKSTAT_SINK7_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK7_POS) 236: #define AG903_BMUn_SINKSTAT_SINK8_POS 8 237: #define AG903_BMUn_SINKSTAT_SINK8_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK8_POS) 238: #define AG903_BMUn_SINKSTAT_SINK9_POS 9 239: #define AG903_BMUn_SINKSTAT_SINK9_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK9_POS) 240: #define AG903_BMUn_SINKSTAT_SINK10_POS 10 241: #define AG903_BMUn_SINKSTAT_SINK10_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK10_POS) 242: #define AG903_BMUn_SINKSTAT_SINK11_POS 11 243: #define AG903_BMUn_SINKSTAT_SINK11_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK11_POS) 244: #define AG903_BMUn_SINKSTAT_SINK12_POS 12 245: #define AG903_BMUn_SINKSTAT_SINK12_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK12_POS) 246: #define AG903_BMUn_SINKSTAT_SINK13_POS 13 247: #define AG903_BMUn_SINKSTAT_SINK13_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK13_POS) 248: #define AG903_BMUn_SINKSTAT_SINK14_POS 14 249: #define AG903_BMUn_SINKSTAT_SINK14_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK14_POS) 250: #define AG903_BMUn_SINKSTAT_SINK15_POS 15 251: #define AG903_BMUn_SINKSTAT_SINK15_MSK (0x1UL << AG903_BMUn_SINKSTAT_SINK15_POS) 252: 253: #define AG903_BMUn_BASEADR_ADR_POS 7 254: #define AG903_BMUn_BASEADR_ADR_MSK (0x3fffffUL << AG903_BMUn_BASEADR_ADR_POS) 255: 256: #define AG903_BMUn_STRIDE_STRIDE_POS 7 257: #define AG903_BMUn_STRIDE_STRIDE_MSK (0x3ffffUL << AG903_BMUn_STRIDE_STRIDE_POS) 258: 259: #define AG903_BMUn_BUFNUM_NUM_POS 0 260: #define AG903_BMUn_BUFNUM_NUM_MSK (0x7UL << AG903_BMUn_BUFNUM_NUM_POS) 261: 262: #define AG903_BMUn_STAT_WNUM_POS 0 263: #define AG903_BMUn_STAT_WNUM_MSK (0x7UL << AG903_BMUn_STAT_WNUM_POS) 264: #define AG903_BMUn_STAT_WBSY_POS 8 265: #define AG903_BMUn_STAT_WBSY_MSK (0x1UL << AG903_BMUn_STAT_WBSY_POS) 266: #define AG903_BMUn_STAT_WWA_POS 9 267: #define AG903_BMUn_STAT_WWA_MSK (0x1UL << AG903_BMUn_STAT_WWA_POS) 268: #define AG903_BMUn_STAT_FULL_POS 10 269: #define AG903_BMUn_STAT_FULL_MSK (0x1UL << AG903_BMUn_STAT_FULL_POS) 270: #define AG903_BMUn_STAT_RNUM_POS 16 271: #define AG903_BMUn_STAT_RNUM_MSK (0x7UL << AG903_BMUn_STAT_RNUM_POS) 272: #define AG903_BMUn_STAT_RBSY_POS 24 273: #define AG903_BMUn_STAT_RBSY_MSK (0x1UL << AG903_BMUn_STAT_RBSY_POS) 274: #define AG903_BMUn_STAT_RWA_POS 25 275: #define AG903_BMUn_STAT_RWA_MSK (0x1UL << AG903_BMUn_STAT_RWA_POS) 276: #define AG903_BMUn_STAT_EMPTY_POS 26 277: #define AG903_BMUn_STAT_EMPTY_MSK (0x1UL << AG903_BMUn_STAT_EMPTY_POS) 278: #define AG903_BMUn_STAT_VAL_POS 27 279: #define AG903_BMUn_STAT_VAL_MSK (0x1UL << AG903_BMUn_STAT_VAL_POS) 280: 281: 282: #endif 283:
名前 
説明 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address 
BMUn Base Address (n=0..15) 
BMUnBASEADR Address (n=0..15) 
BMUnBASEADR ADR-bit mask 
BMUnBASEADR ADR-bit position 
BMUnBUFNUM Address (n=0..15) 
BMUnBUFNUM NUM-bit mask 
BMUnBUFNUM NUM-bit position 
BMUnCTRL Address (n=0..15) 
BMUnCTRL EN-bit mask 
BMUnCTRL EN-bit position 
BMUnMOD Address (n=0..15) 
BMUnMOD INI-bit mask 
BMUnMOD INI-bit position 
BMUnMOD MGR-bit mask 
BMUnMOD MGR-bit position 
BMUnMOD SRC-bit mask 
BMUnMOD SRC-bit position 
BMUnSINKMODULE Address (n=0..15) 
BMUnSINKMODULE SINK0-bit mask 
BMUnSINKMODULE SINK0-bit position 
BMUnSINKMODULE SINK1-bit mask 
BMUnSINKMODULE SINK1-bit position 
BMUnSINKMODULE SINK10-bit mask 
BMUnSINKMODULE SINK10-bit position 
BMUnSINKMODULE SINK11-bit mask 
BMUnSINKMODULE SINK11-bit position 
BMUnSINKMODULE SINK12-bit mask 
BMUnSINKMODULE SINK12-bit position 
BMUnSINKMODULE SINK13-bit mask 
BMUnSINKMODULE SINK13-bit position 
BMUnSINKMODULE SINK14-bit mask 
BMUnSINKMODULE SINK14-bit position 
BMUnSINKMODULE SINK15-bit mask 
BMUnSINKMODULE SINK15-bit position 
BMUnSINKMODULE SINK2-bit mask 
BMUnSINKMODULE SINK2-bit position 
BMUnSINKMODULE SINK3-bit mask 
BMUnSINKMODULE SINK3-bit position 
BMUnSINKMODULE SINK4-bit mask 
BMUnSINKMODULE SINK4-bit position 
BMUnSINKMODULE SINK5-bit mask 
BMUnSINKMODULE SINK5-bit position 
BMUnSINKMODULE SINK6-bit mask 
BMUnSINKMODULE SINK6-bit position 
BMUnSINKMODULE SINK7-bit mask 
BMUnSINKMODULE SINK7-bit position 
BMUnSINKMODULE SINK8-bit mask 
BMUnSINKMODULE SINK8-bit position 
BMUnSINKMODULE SINK9-bit mask 
BMUnSINKMODULE SINK9-bit position 
BMUnSINKSTAT Address (n=0..15) 
BMUnSINKSTAT SINK0-bit mask 
BMUnSINKSTAT SINK0-bit position 
BMUnSINKSTAT SINK1-bit mask 
BMUnSINKSTAT SINK1-bit position 
BMUnSINKSTAT SINK10-bit mask 
BMUnSINKSTAT SINK10-bit position 
BMUnSINKSTAT SINK11-bit mask 
BMUnSINKSTAT SINK11-bit position 
BMUnSINKSTAT SINK12-bit mask 
BMUnSINKSTAT SINK12-bit position 
BMUnSINKSTAT SINK13-bit mask 
BMUnSINKSTAT SINK13-bit position 
BMUnSINKSTAT SINK14-bit mask 
BMUnSINKSTAT SINK14-bit position 
BMUnSINKSTAT SINK15-bit mask 
BMUnSINKSTAT SINK15-bit position 
BMUnSINKSTAT SINK2-bit mask 
BMUnSINKSTAT SINK2-bit position 
BMUnSINKSTAT SINK3-bit mask 
BMUnSINKSTAT SINK3-bit position 
BMUnSINKSTAT SINK4-bit mask 
BMUnSINKSTAT SINK4-bit position 
BMUnSINKSTAT SINK5-bit mask 
BMUnSINKSTAT SINK5-bit position 
BMUnSINKSTAT SINK6-bit mask 
BMUnSINKSTAT SINK6-bit position 
BMUnSINKSTAT SINK7-bit mask 
BMUnSINKSTAT SINK7-bit position 
BMUnSINKSTAT SINK8-bit mask 
BMUnSINKSTAT SINK8-bit position 
BMUnSINKSTAT SINK9-bit mask 
BMUnSINKSTAT SINK9-bit position 
BMUnSTAT Address (n=0..15) 
BMUnSTAT EMPTY-bit mask 
BMUnSTAT EMPTY-bit position 
BMUnSTAT FULL-bit mask 
BMUnSTAT FULL-bit position 
BMUnSTAT RBSY-bit mask 
BMUnSTAT RBSY-bit position 
BMUnSTAT RNUM-bit mask 
BMUnSTAT RNUM-bit position 
BMUnSTAT RWA-bit mask 
BMUnSTAT RWA-bit position 
BMUnSTAT VAL-bit mask 
BMUnSTAT VAL-bit position 
BMUnSTAT WBSY-bit mask 
BMUnSTAT WBSY-bit position 
BMUnSTAT WNUM-bit mask 
BMUnSTAT WNUM-bit position 
BMUnSTAT WWA-bit mask 
BMUnSTAT WWA-bit position 
BMUnSTRIDE Address (n=0..15) 
BMUnSTRIDE STRIDE-bit mask 
BMUnSTRIDE STRIDE-bit position 
名前 
説明 
BMUn Type 
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