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AG903_i2creg.h

IIC Register Definition

IIC Register Definition

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AXELL CORPORATION

2017_10_20 Auto-generated.

1: 8: 9: 13: 14: #ifndef _AG903_IIC_REGMAP_H_ 15: #define _AG903_IIC_REGMAP_H_ 16: 17: 18: #include "AG903_regmap.h" 19: 20: #ifndef __I 21: 22: #define __I volatile const 23: #endif 24: #ifndef __O 25: 26: #define __O volatile 27: #endif 28: #ifndef __IO 29: 30: #define __IO volatile 31: #endif 32: 33: 34: typedef struct { 35: 36: union { 37: __IO uint32_t CR; 38: 39: struct { 40: __IO uint32_t I2C_RST : 1; 41: __IO uint32_t I2C_EN : 1; 42: __IO uint32_t SCL_EN : 1; 43: __IO uint32_t GC_EN : 1; 44: __IO uint32_t START : 1; 45: __IO uint32_t STOP : 1; 46: __IO uint32_t NACK : 1; 47: __IO uint32_t TB_EN : 1; 48: __IO uint32_t DTI_EN : 1; 49: __IO uint32_t DRI_EN : 1; 50: __IO uint32_t BERRI_EN : 1; 51: __IO uint32_t STOPI_EN : 1; 52: __IO uint32_t SAMI_EN : 1; 53: __IO uint32_t ALI_EN : 1; 54: __IO uint32_t STARTI_EN : 1; 55: __IO uint32_t SCL_LOW : 1; 56: __IO uint32_t SDA_LOW : 1; 57: __IO uint32_t Test_bit : 1; 58: } CR_bits; 59: }; 60: 61: union { 62: __I uint32_t SR; 63: 64: struct { 65: __I uint32_t RW : 1; 66: __I uint32_t ACK : 1; 67: __I uint32_t I2CB : 1; 68: __I uint32_t BB : 1; 69: __I uint32_t DT : 1; 70: __I uint32_t DR : 1; 71: __I uint32_t BERR : 1; 72: __I uint32_t STOP : 1; 73: __I uint32_t SAM : 1; 74: __I uint32_t GC : 1; 75: __I uint32_t AL : 1; 76: __I uint32_t START : 1; 77: __I uint32_t SEXT : 1; 78: __I uint32_t MEXT : 1; 79: __I uint32_t TOUTMin : 1; 80: __I uint32_t TOUTMax : 1; 81: __I uint32_t ALERT : 1; 82: __I uint32_t SUSPEND : 1; 83: __I uint32_t RESUME : 1; 84: __I uint32_t ARA : 1; 85: __I uint32_t DDA : 1; 86: __I uint32_t SAL : 1; 87: } SR_bits; 88: }; 89: 90: union { 91: __IO uint32_t CDR; 92: 93: struct { 94: __IO uint32_t COUNT : 18; 95: } CDR_bits; 96: }; 97: 98: union { 99: __IO uint32_t DR; 100: 101: struct { 102: __IO uint32_t DR : 8; 103: } DR_bits; 104: }; 105: 106: union { 107: __IO uint32_t SAR; 108: 109: struct { 110: __IO uint32_t SAR : 7; 111: __IO uint32_t SAR10 : 3; 112: uint32_t : 21; 113: __IO uint32_t EN10 : 1; 114: } SAR_bits; 115: }; 116: 117: union { 118: __IO uint32_t TGSR; 119: 120: struct { 121: __IO uint32_t TSR : 10; 122: __IO uint32_t GSR : 4; 123: } TGSR_bits; 124: }; 125: 126: union { 127: __I uint32_t BMR; 128: 129: struct { 130: __I uint32_t SDAin : 1; 131: __I uint32_t SCLin : 1; 132: } BMR_bits; 133: }; 134: 135: __I uint32_t RESERVED1[5]; 136: 137: union { 138: __I uint32_t Revision; 139: }; 140: 141: union { 142: __I uint32_t Feature; 143: 144: struct { 145: __I uint32_t SMBUS : 1; 146: } Feature_bits; 147: }; 148: 149: 150: }AG903_IICn_Type; 151: 152: #define AG903_IICn(ch) ((volatile AG903_IICn_Type *)(AG903_IIC0_BASE + 0x100000 * ch)) 153: #define AG903_IICn_CR(ch) AG903_IICn(ch)->CR 154: #define AG903_IICn_SR(ch) AG903_IICn(ch)->SR 155: #define AG903_IICn_CDR(ch) AG903_IICn(ch)->CDR 156: #define AG903_IICn_DR(ch) AG903_IICn(ch)->DR 157: #define AG903_IICn_SAR(ch) AG903_IICn(ch)->SAR 158: #define AG903_IICn_TGSR(ch) AG903_IICn(ch)->TGSR 159: #define AG903_IICn_BMR(ch) AG903_IICn(ch)->BMR 160: #define AG903_IICn_Revision(ch) AG903_IICn(ch)->Revision 161: #define AG903_IICn_Feature(ch) AG903_IICn(ch)->Feature 162: 163: #define AG903_IIC0 ((volatile AG903_IICn_Type *) AG903_IIC0_BASE) 164: #define AG903_IIC1 ((volatile AG903_IICn_Type *) AG903_IIC1_BASE) 165: 166: 167: #define AG903_IICn_CR_I2C_RST_POS 0 168: #define AG903_IICn_CR_I2C_RST_MSK (0x1UL << AG903_IICn_CR_I2C_RST_POS) 169: #define AG903_IICn_CR_I2C_EN_POS 1 170: #define AG903_IICn_CR_I2C_EN_MSK (0x1UL << AG903_IICn_CR_I2C_EN_POS) 171: #define AG903_IICn_CR_SCL_EN_POS 2 172: #define AG903_IICn_CR_SCL_EN_MSK (0x1UL << AG903_IICn_CR_SCL_EN_POS) 173: #define AG903_IICn_CR_GC_EN_POS 3 174: #define AG903_IICn_CR_GC_EN_MSK (0x1UL << AG903_IICn_CR_GC_EN_POS) 175: #define AG903_IICn_CR_START_POS 4 176: #define AG903_IICn_CR_START_MSK (0x1UL << AG903_IICn_CR_START_POS) 177: #define AG903_IICn_CR_STOP_POS 5 178: #define AG903_IICn_CR_STOP_MSK (0x1UL << AG903_IICn_CR_STOP_POS) 179: #define AG903_IICn_CR_NACK_POS 6 180: #define AG903_IICn_CR_NACK_MSK (0x1UL << AG903_IICn_CR_NACK_POS) 181: #define AG903_IICn_CR_TB_EN_POS 7 182: #define AG903_IICn_CR_TB_EN_MSK (0x1UL << AG903_IICn_CR_TB_EN_POS) 183: #define AG903_IICn_CR_DTI_EN_POS 8 184: #define AG903_IICn_CR_DTI_EN_MSK (0x1UL << AG903_IICn_CR_DTI_EN_POS) 185: #define AG903_IICn_CR_DRI_EN_POS 9 186: #define AG903_IICn_CR_DRI_EN_MSK (0x1UL << AG903_IICn_CR_DRI_EN_POS) 187: #define AG903_IICn_CR_BERRI_EN_POS 10 188: #define AG903_IICn_CR_BERRI_EN_MSK (0x1UL << AG903_IICn_CR_BERRI_EN_POS) 189: #define AG903_IICn_CR_STOPI_EN_POS 11 190: #define AG903_IICn_CR_STOPI_EN_MSK (0x1UL << AG903_IICn_CR_STOPI_EN_POS) 191: #define AG903_IICn_CR_SAMI_EN_POS 12 192: #define AG903_IICn_CR_SAMI_EN_MSK (0x1UL << AG903_IICn_CR_SAMI_EN_POS) 193: #define AG903_IICn_CR_ALI_EN_POS 13 194: #define AG903_IICn_CR_ALI_EN_MSK (0x1UL << AG903_IICn_CR_ALI_EN_POS) 195: #define AG903_IICn_CR_STARTI_EN_POS 14 196: #define AG903_IICn_CR_STARTI_EN_MSK (0x1UL << AG903_IICn_CR_STARTI_EN_POS) 197: #define AG903_IICn_CR_SCL_LOW_POS 15 198: #define AG903_IICn_CR_SCL_LOW_MSK (0x1UL << AG903_IICn_CR_SCL_LOW_POS) 199: #define AG903_IICn_CR_SDA_LOW_POS 16 200: #define AG903_IICn_CR_SDA_LOW_MSK (0x1UL << AG903_IICn_CR_SDA_LOW_POS) 201: #define AG903_IICn_CR_Test_bit_POS 17 202: #define AG903_IICn_CR_Test_bit_MSK (0x1UL << AG903_IICn_CR_Test_bit_POS) 203: 204: #define AG903_IICn_SR_RW_POS 0 205: #define AG903_IICn_SR_RW_MSK (0x1UL << AG903_IICn_SR_RW_POS) 206: #define AG903_IICn_SR_ACK_POS 1 207: #define AG903_IICn_SR_ACK_MSK (0x1UL << AG903_IICn_SR_ACK_POS) 208: #define AG903_IICn_SR_I2CB_POS 2 209: #define AG903_IICn_SR_I2CB_MSK (0x1UL << AG903_IICn_SR_I2CB_POS) 210: #define AG903_IICn_SR_BB_POS 3 211: #define AG903_IICn_SR_BB_MSK (0x1UL << AG903_IICn_SR_BB_POS) 212: #define AG903_IICn_SR_DT_POS 4 213: #define AG903_IICn_SR_DT_MSK (0x1UL << AG903_IICn_SR_DT_POS) 214: #define AG903_IICn_SR_DR_POS 5 215: #define AG903_IICn_SR_DR_MSK (0x1UL << AG903_IICn_SR_DR_POS) 216: #define AG903_IICn_SR_BERR_POS 6 217: #define AG903_IICn_SR_BERR_MSK (0x1UL << AG903_IICn_SR_BERR_POS) 218: #define AG903_IICn_SR_STOP_POS 7 219: #define AG903_IICn_SR_STOP_MSK (0x1UL << AG903_IICn_SR_STOP_POS) 220: #define AG903_IICn_SR_SAM_POS 8 221: #define AG903_IICn_SR_SAM_MSK (0x1UL << AG903_IICn_SR_SAM_POS) 222: #define AG903_IICn_SR_GC_POS 9 223: #define AG903_IICn_SR_GC_MSK (0x1UL << AG903_IICn_SR_GC_POS) 224: #define AG903_IICn_SR_AL_POS 10 225: #define AG903_IICn_SR_AL_MSK (0x1UL << AG903_IICn_SR_AL_POS) 226: #define AG903_IICn_SR_START_POS 11 227: #define AG903_IICn_SR_START_MSK (0x1UL << AG903_IICn_SR_START_POS) 228: #define AG903_IICn_SR_SEXT_POS 12 229: #define AG903_IICn_SR_SEXT_MSK (0x1UL << AG903_IICn_SR_SEXT_POS) 230: #define AG903_IICn_SR_MEXT_POS 13 231: #define AG903_IICn_SR_MEXT_MSK (0x1UL << AG903_IICn_SR_MEXT_POS) 232: #define AG903_IICn_SR_TOUTMin_POS 14 233: #define AG903_IICn_SR_TOUTMin_MSK (0x1UL << AG903_IICn_SR_TOUTMin_POS) 234: #define AG903_IICn_SR_TOUTMax_POS 15 235: #define AG903_IICn_SR_TOUTMax_MSK (0x1UL << AG903_IICn_SR_TOUTMax_POS) 236: #define AG903_IICn_SR_ALERT_POS 16 237: #define AG903_IICn_SR_ALERT_MSK (0x1UL << AG903_IICn_SR_ALERT_POS) 238: #define AG903_IICn_SR_SUSPEND_POS 17 239: #define AG903_IICn_SR_SUSPEND_MSK (0x1UL << AG903_IICn_SR_SUSPEND_POS) 240: #define AG903_IICn_SR_RESUME_POS 18 241: #define AG903_IICn_SR_RESUME_MSK (0x1UL << AG903_IICn_SR_RESUME_POS) 242: #define AG903_IICn_SR_ARA_POS 19 243: #define AG903_IICn_SR_ARA_MSK (0x1UL << AG903_IICn_SR_ARA_POS) 244: #define AG903_IICn_SR_DDA_POS 20 245: #define AG903_IICn_SR_DDA_MSK (0x1UL << AG903_IICn_SR_DDA_POS) 246: #define AG903_IICn_SR_SAL_POS 21 247: #define AG903_IICn_SR_SAL_MSK (0x1UL << AG903_IICn_SR_SAL_POS) 248: 249: #define AG903_IICn_CDR_COUNT_POS 0 250: #define AG903_IICn_CDR_COUNT_MSK (0x3ffffUL << AG903_IICn_CDR_COUNT_POS) 251: 252: #define AG903_IICn_DR_DR_POS 0 253: #define AG903_IICn_DR_DR_MSK (0xffUL << AG903_IICn_DR_DR_POS) 254: 255: #define AG903_IICn_SAR_SAR_POS 0 256: #define AG903_IICn_SAR_SAR_MSK (0x7fUL << AG903_IICn_SAR_SAR_POS) 257: #define AG903_IICn_SAR_SAR10_POS 7 258: #define AG903_IICn_SAR_SAR10_MSK (0x7UL << AG903_IICn_SAR_SAR10_POS) 259: #define AG903_IICn_SAR_EN10_POS 31 260: #define AG903_IICn_SAR_EN10_MSK (0x1UL << AG903_IICn_SAR_EN10_POS) 261: 262: #define AG903_IICn_TGSR_TSR_POS 0 263: #define AG903_IICn_TGSR_TSR_MSK (0x3ffUL << AG903_IICn_TGSR_TSR_POS) 264: #define AG903_IICn_TGSR_GSR_POS 10 265: #define AG903_IICn_TGSR_GSR_MSK (0xfUL << AG903_IICn_TGSR_GSR_POS) 266: 267: #define AG903_IICn_BMR_SDAin_POS 0 268: #define AG903_IICn_BMR_SDAin_MSK (0x1UL << AG903_IICn_BMR_SDAin_POS) 269: #define AG903_IICn_BMR_SCLin_POS 1 270: #define AG903_IICn_BMR_SCLin_MSK (0x1UL << AG903_IICn_BMR_SCLin_POS) 271: 272: #define AG903_IICn_Revision_REVISION_POS 0 273: #define AG903_IICn_Revision_REVISION_MSK (0xffffffffUL << AG903_IICn_Revision_REVISION_POS) 274: 275: #define AG903_IICn_Feature_SMBUS_POS 0 276: #define AG903_IICn_Feature_SMBUS_MSK (0x1UL << AG903_IICn_Feature_SMBUS_POS) 277: 278: #endif 279:
名前 
説明 
IICn Base Address 
IICn Base Address 
IICn Base Address (n=0..1) 
IICnBMR Address (n=0..1) 
IICnBMR SCLin-bit mask 
IICnBMR SCLin-bit position 
IICnBMR SDAin-bit mask 
IICnBMR SDAin-bit position 
IICnCDR Address (n=0..1) 
IICnCDR COUNT-bit mask 
IICnCDR COUNT-bit position 
IICnCR Address (n=0..1) 
IICnCR ALI_EN-bit mask 
IICnCR ALI_EN-bit position 
IICnCR BERRI_EN-bit mask 
IICnCR BERRI_EN-bit position 
IICnCR DRI_EN-bit mask 
IICnCR DRI_EN-bit position 
IICnCR DTI_EN-bit mask 
IICnCR DTI_EN-bit position 
IICnCR GC_EN-bit mask 
IICnCR GC_EN-bit position 
IICnCR I2C_EN-bit mask 
IICnCR I2C_EN-bit position 
IICnCR I2C_RST-bit mask 
IICnCR I2C_RST-bit position 
IICnCR NACK-bit mask 
IICnCR NACK-bit position 
IICnCR SAMI_EN-bit mask 
IICnCR SAMI_EN-bit position 
IICnCR SCL_EN-bit mask 
IICnCR SCL_EN-bit position 
IICnCR SCL_LOW-bit mask 
IICnCR SCL_LOW-bit position 
IICnCR SDA_LOW-bit mask 
IICnCR SDA_LOW-bit position 
IICnCR START-bit mask 
IICnCR START-bit position 
IICnCR STARTI_EN-bit mask 
IICnCR STARTI_EN-bit position 
IICnCR STOP-bit mask 
IICnCR STOP-bit position 
IICnCR STOPI_EN-bit mask 
IICnCR STOPI_EN-bit position 
IICnCR TB_EN-bit mask 
IICnCR TB_EN-bit position 
IICnCR Test_bit-bit mask 
IICnCR Test_bit-bit position 
IICnDR Address (n=0..1) 
IICnDR DR-bit mask 
IICnDR DR-bit position 
IICnFeature Address (n=0..1) 
IICnFeature SMBUS-bit mask 
IICnFeature SMBUS-bit position 
IICnRevision Address (n=0..1) 
IICnRevision REVISION-bit mask 
IICnRevision REVISION-bit position 
IICnSAR Address (n=0..1) 
IICnSAR EN10-bit mask 
IICnSAR EN10-bit position 
IICnSAR SAR-bit mask 
IICnSAR SAR-bit position 
IICnSAR SAR10-bit mask 
IICnSAR SAR10-bit position 
IICnSR Address (n=0..1) 
IICnSR ACK-bit mask 
IICnSR ACK-bit position 
IICnSR AL-bit mask 
IICnSR AL-bit position 
IICnSR ALERT-bit mask 
IICnSR ALERT-bit position 
IICnSR ARA-bit mask 
IICnSR ARA-bit position 
IICnSR BB-bit mask 
IICnSR BB-bit position 
IICnSR BERR-bit mask 
IICnSR BERR-bit position 
IICnSR DDA-bit mask 
IICnSR DDA-bit position 
IICnSR DR-bit mask 
IICnSR DR-bit position 
IICnSR DT-bit mask 
IICnSR DT-bit position 
IICnSR GC-bit mask 
IICnSR GC-bit position 
IICnSR I2CB-bit mask 
IICnSR I2CB-bit position 
IICnSR MEXT-bit mask 
IICnSR MEXT-bit position 
IICnSR RESUME-bit mask 
IICnSR RESUME-bit position 
IICnSR RW-bit mask 
IICnSR RW-bit position 
IICnSR SAL-bit mask 
IICnSR SAL-bit position 
IICnSR SAM-bit mask 
IICnSR SAM-bit position 
IICnSR SEXT-bit mask 
IICnSR SEXT-bit position 
IICnSR START-bit mask 
IICnSR START-bit position 
IICnSR STOP-bit mask 
IICnSR STOP-bit position 
IICnSR SUSPEND-bit mask 
IICnSR SUSPEND-bit position 
IICnSR TOUTMax-bit mask 
IICnSR TOUTMax-bit position 
IICnSR TOUTMin-bit mask 
IICnSR TOUTMin-bit position 
IICnTGSR Address (n=0..1) 
IICnTGSR GSR-bit mask 
IICnTGSR GSR-bit position 
IICnTGSR TSR-bit mask 
IICnTGSR TSR-bit position 
名前 
説明 
IICn Type 
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