AG903ライブラリリファレンス
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AG903_sscreg.h マクロ
マクロ
名前 
説明 
SSC Base Address 
SSCBMU_CONTROL CLR_SNK-bit mask 
SSCBMU_CONTROL CLR_SNK-bit position 
SSCBMU_CONTROL CLR_SRC-bit mask 
SSCBMU_CONTROL CLR_SRC-bit position 
SSCBMU_CONTROL SET_SNK-bit mask 
SSCBMU_CONTROL SET_SNK-bit position 
SSCBMU_CONTROL SET_SRC-bit mask 
SSCBMU_CONTROL SET_SRC-bit position 
SSCBMU_STATUS SNKRDY-bit mask 
SSCBMU_STATUS SNKRDY-bit position 
SSCBMU_STATUS SNKREQ-bit mask 
SSCBMU_STATUS SNKREQ-bit position 
SSCBMU_STATUS SRCRDY-bit mask 
SSCBMU_STATUS SRCRDY-bit position 
SSCBMU_STATUS SRCREQ-bit mask 
SSCBMU_STATUS SRCREQ-bit position 
SSCBMU_TRIG_CLEAR SNKRDY-bit mask 
SSCBMU_TRIG_CLEAR SNKRDY-bit position 
SSCBMU_TRIG_CLEAR SNKREQ-bit mask 
SSCBMU_TRIG_CLEAR SNKREQ-bit position 
SSCBMU_TRIG_CLEAR SRCRDY-bit mask 
SSCBMU_TRIG_CLEAR SRCRDY-bit position 
SSCBMU_TRIG_CLEAR SRCREQ-bit mask 
SSCBMU_TRIG_CLEAR SRCREQ-bit position 
SSCBMU_TRIG_STATUS SNKRDY-bit mask 
SSCBMU_TRIG_STATUS SNKRDY-bit position 
SSCBMU_TRIG_STATUS SNKREQ-bit mask 
SSCBMU_TRIG_STATUS SNKREQ-bit position 
SSCBMU_TRIG_STATUS SRCRDY-bit mask 
SSCBMU_TRIG_STATUS SRCRDY-bit position 
SSCBMU_TRIG_STATUS SRCREQ-bit mask 
SSCBMU_TRIG_STATUS SRCREQ-bit position 
SSCCA5_ACP_SETUP ACPADDR-bit mask 
SSCCA5_ACP_SETUP ACPADDR-bit position 
SSCCA5_JUMPADDR JUMPADDR-bit mask 
SSCCA5_JUMPADDR JUMPADDR-bit position 
SSCCA5_RUN_CTRL CLREV-bit mask 
SSCCA5_RUN_CTRL CLREV-bit position 
SSCCA5_RUN_SETUP GCLK-bit mask 
SSCCA5_RUN_SETUP GCLK-bit position 
SSCCA5_RUN_SETUP RESET-bit mask 
SSCCA5_RUN_SETUP RESET-bit position 
SSCCA5_RUN_SETUP VINITHI-bit mask 
SSCCA5_RUN_SETUP VINITHI-bit position 
SSCCA5_RUN_STATUS EVENTO-bit mask 
SSCCA5_RUN_STATUS EVENTO-bit position 
SSCCA5_RUN_STATUS GCLK-bit mask 
SSCCA5_RUN_STATUS GCLK-bit position 
SSCCA5_RUN_STATUS RESET-bit mask 
SSCCA5_RUN_STATUS RESET-bit position 
SSCCA5_RUN_STATUS WFE-bit mask 
SSCCA5_RUN_STATUS WFE-bit position 
SSCCA5_RUN_STATUS WFI-bit mask 
SSCCA5_RUN_STATUS WFI-bit position 
SSCCLKDUTY_GFX DUTY-bit mask 
SSCCLKDUTY_GFX DUTY-bit position 
SSCCLKDUTY_GFX VSON-bit mask 
SSCCLKDUTY_GFX VSON-bit position 
SSCCLKDUTY_GVD DUTY-bit mask 
SSCCLKDUTY_GVD DUTY-bit position 
SSCCOUNT64_LOWER COUNT64_LOWER-bit mask 
SSCCOUNT64_LOWER COUNT64_LOWER-bit position 
SSCCOUNT64_UPPER COUNT64_UPPER-bit mask 
SSCCOUNT64_UPPER COUNT64_UPPER-bit position 
SSCCVBSDEC_ADDR ADDR-bit mask 
SSCCVBSDEC_ADDR ADDR-bit position 
SSCCVBSDEC_ADDR CH-bit mask 
SSCCVBSDEC_ADDR CH-bit position 
SSCCVBSDEC_DATA DATA-bit mask 
SSCCVBSDEC_DATA DATA-bit position 
SSCDMA_SELECT_PBD DMASELECT-bit mask 
SSCDMA_SELECT_PBD DMASELECT-bit position 
SSCDMA_SELECT0 DMASELECT0-bit mask 
SSCDMA_SELECT0 DMASELECT0-bit position 
SSCDMA_SELECT0 DMASELECT1-bit mask 
SSCDMA_SELECT0 DMASELECT1-bit position 
SSCDMA_SELECT0 DMASELECT2-bit mask 
SSCDMA_SELECT0 DMASELECT2-bit position 
SSCDMA_SELECT0 DMASELECT3-bit mask 
SSCDMA_SELECT0 DMASELECT3-bit position 
SSCDMA_SELECT1 DMASELECT4-bit mask 
SSCDMA_SELECT1 DMASELECT4-bit position 
SSCDMA_SELECT1 DMASELECT5-bit mask 
SSCDMA_SELECT1 DMASELECT5-bit position 
SSCDMA_SELECT1 DMASELECT6-bit mask 
SSCDMA_SELECT1 DMASELECT6-bit position 
SSCDMA_SELECT1 DMASELECT7-bit mask 
SSCDMA_SELECT1 DMASELECT7-bit position 
SSCDMA_SELECT2 DMASELECT10-bit mask 
SSCDMA_SELECT2 DMASELECT10-bit position 
SSCDMA_SELECT2 DMASELECT11-bit mask 
SSCDMA_SELECT2 DMASELECT11-bit position 
SSCDMA_SELECT2 DMASELECT8-bit mask 
SSCDMA_SELECT2 DMASELECT8-bit position 
SSCDMA_SELECT2 DMASELECT9-bit mask 
SSCDMA_SELECT2 DMASELECT9-bit position 
SSCDMA_SELECT3 DMASELECT12-bit mask 
SSCDMA_SELECT3 DMASELECT12-bit position 
SSCDMA_SELECT3 DMASELECT13-bit mask 
SSCDMA_SELECT3 DMASELECT13-bit position 
SSCDMA_SELECT3 DMASELECT14-bit mask 
SSCDMA_SELECT3 DMASELECT14-bit position 
SSCDMA_SELECT3 DMASELECT15-bit mask 
SSCDMA_SELECT3 DMASELECT15-bit position 
SSCDSP_SETUP DOT0_DIR-bit mask 
SSCDSP_SETUP DOT0_DIR-bit position 
SSCDSP_SETUP DOT1_DIR-bit mask 
SSCDSP_SETUP DOT1_DIR-bit position 
SSCDSP_SETUP FIELD0_DIR-bit mask 
SSCDSP_SETUP FIELD0_DIR-bit position 
SSCDSP_SETUP FIELD1_DIR-bit mask 
SSCDSP_SETUP FIELD1_DIR-bit position 
SSCDSP_SETUP VSYNC0_DIR-bit mask 
SSCDSP_SETUP VSYNC0_DIR-bit position 
SSCDSP_SETUP VSYNC1_DIR-bit mask 
SSCDSP_SETUP VSYNC1_DIR-bit position 
SSCINT_STATUS_LOWER INTSTATUS-bit mask 
SSCINT_STATUS_LOWER INTSTATUS-bit position 
SSCINT_STATUS_MIDDLE INTSTATUS-bit mask 
SSCINT_STATUS_MIDDLE INTSTATUS-bit position 
SSCINT_STATUS_UPPER INTSTATUS-bit mask 
SSCINT_STATUS_UPPER INTSTATUS-bit position 
SSCINT0_ENABLE_LOWER INTENABLE-bit mask 
SSCINT0_ENABLE_LOWER INTENABLE-bit position 
SSCINT0_ENABLE_MIDDLE INTENABLE-bit mask 
SSCINT0_ENABLE_MIDDLE INTENABLE-bit position 
SSCINT0_ENABLE_UPPER INTENABLE-bit mask 
SSCINT0_ENABLE_UPPER INTENABLE-bit position 
SSCINT1_ENABLE_LOWER INTENABLE-bit mask 
SSCINT1_ENABLE_LOWER INTENABLE-bit position 
SSCINT1_ENABLE_MIDDLE INTENABLE-bit mask 
SSCINT1_ENABLE_MIDDLE INTENABLE-bit position 
SSCINT1_ENABLE_UPPER INTENABLE-bit mask 
SSCINT1_ENABLE_UPPER INTENABLE-bit position 
SSCINT2_ENABLE_LOWER INTENABLE-bit mask 
SSCINT2_ENABLE_LOWER INTENABLE-bit position 
SSCINT2_ENABLE_MIDDLE INTENABLE-bit mask 
SSCINT2_ENABLE_MIDDLE INTENABLE-bit position 
SSCINT2_ENABLE_UPPER INTENABLE-bit mask 
SSCINT2_ENABLE_UPPER INTENABLE-bit position 
SSCINT3_ENABLE_LOWER INTENABLE-bit mask 
SSCINT3_ENABLE_LOWER INTENABLE-bit position 
SSCINT3_ENABLE_MIDDLE INTENABLE-bit mask 
SSCINT3_ENABLE_MIDDLE INTENABLE-bit position 
SSCINT3_ENABLE_UPPER INTENABLE-bit mask 
SSCINT3_ENABLE_UPPER INTENABLE-bit position 
SSCIRQ_BUS_ENABLE IRQBUSENABLE-bit mask 
SSCIRQ_BUS_ENABLE IRQBUSENABLE-bit position 
SSCIRQ_BUS_STATUS IRQBUSSTATUS-bit mask 
SSCIRQ_BUS_STATUS IRQBUSSTATUS-bit position 
SSCIRQ_STATUS_LOWER IRQSTATUS-bit mask 
SSCIRQ_STATUS_LOWER IRQSTATUS-bit position 
SSCIRQ_STATUS_UPPER IRQSTATUS-bit mask 
SSCIRQ_STATUS_UPPER IRQSTATUS-bit position 
SSCMODE_STATUS BOOTMODE-bit mask 
SSCMODE_STATUS BOOTMODE-bit position 
SSCMODE_STATUS BOOTTEST-bit mask 
SSCMODE_STATUS BOOTTEST-bit position 
SSCMODE_STATUS INITPIN-bit mask 
SSCMODE_STATUS INITPIN-bit position 
SSCMODE_STATUS WDTCA5-bit mask 
SSCMODE_STATUS WDTCA5-bit position 
SSCMODE_STATUS WDTGPP-bit mask 
SSCMODE_STATUS WDTGPP-bit position 
SSCMODE_STATUS WDTPIN-bit mask 
SSCMODE_STATUS WDTPIN-bit position 
SSCPBD_ADDRCHECK_ENABLE ENABLE-bit mask 
SSCPBD_ADDRCHECK_ENABLE ENABLE-bit position 
SSCPBD_ADDRCHECK_END END_ADDR-bit mask 
SSCPBD_ADDRCHECK_END END_ADDR-bit position 
SSCPBD_ADDRCHECK_START START_ADDR-bit mask 
SSCPBD_ADDRCHECK_START START_ADDR-bit position 
SSCPBD_ADDRCHECK_STATUS STATUS-bit mask 
SSCPBD_ADDRCHECK_STATUS STATUS-bit position 
SSCPBH_MODE WAIT-bit mask 
SSCPBH_MODE WAIT-bit position 
SSCPIN_FUNC0 FUNC0-bit mask 
SSCPIN_FUNC0 FUNC0-bit position 
SSCPIN_FUNC0 FUNC1-bit mask 
SSCPIN_FUNC0 FUNC1-bit position 
SSCPIN_FUNC0 FUNC10-bit mask 
SSCPIN_FUNC0 FUNC10-bit position 
SSCPIN_FUNC0 FUNC11-bit mask 
SSCPIN_FUNC0 FUNC11-bit position 
SSCPIN_FUNC0 FUNC12-bit mask 
SSCPIN_FUNC0 FUNC12-bit position 
SSCPIN_FUNC0 FUNC13-bit mask 
SSCPIN_FUNC0 FUNC13-bit position 
SSCPIN_FUNC0 FUNC14-bit mask 
SSCPIN_FUNC0 FUNC14-bit position 
SSCPIN_FUNC0 FUNC15-bit mask 
SSCPIN_FUNC0 FUNC15-bit position 
SSCPIN_FUNC0 FUNC2-bit mask 
SSCPIN_FUNC0 FUNC2-bit position 
SSCPIN_FUNC0 FUNC3-bit mask 
SSCPIN_FUNC0 FUNC3-bit position 
SSCPIN_FUNC0 FUNC4-bit mask 
SSCPIN_FUNC0 FUNC4-bit position 
SSCPIN_FUNC0 FUNC5-bit mask 
SSCPIN_FUNC0 FUNC5-bit position 
SSCPIN_FUNC0 FUNC6-bit mask 
SSCPIN_FUNC0 FUNC6-bit position 
SSCPIN_FUNC0 FUNC7-bit mask 
SSCPIN_FUNC0 FUNC7-bit position 
SSCPIN_FUNC0 FUNC8-bit mask 
SSCPIN_FUNC0 FUNC8-bit position 
SSCPIN_FUNC0 FUNC9-bit mask 
SSCPIN_FUNC0 FUNC9-bit position 
SSCPIN_FUNC1 FUNC16-bit mask 
SSCPIN_FUNC1 FUNC16-bit position 
SSCPIN_FUNC1 FUNC17-bit mask 
SSCPIN_FUNC1 FUNC17-bit position 
SSCPIN_FUNC1 FUNC18-bit mask 
SSCPIN_FUNC1 FUNC18-bit position 
SSCPIN_FUNC1 FUNC19-bit mask 
SSCPIN_FUNC1 FUNC19-bit position 
SSCPIN_FUNC1 FUNC20-bit mask 
SSCPIN_FUNC1 FUNC20-bit position 
SSCPIN_FUNC1 FUNC21-bit mask 
SSCPIN_FUNC1 FUNC21-bit position 
SSCPIN_FUNC1 FUNC22-bit mask 
SSCPIN_FUNC1 FUNC22-bit position 
SSCPIN_FUNC1 FUNC23-bit mask 
SSCPIN_FUNC1 FUNC23-bit position 
SSCPIN_FUNC1 FUNC24-bit mask 
SSCPIN_FUNC1 FUNC24-bit position 
SSCPIN_FUNC1 FUNC25-bit mask 
SSCPIN_FUNC1 FUNC25-bit position 
SSCPIN_FUNC1 FUNC26-bit mask 
SSCPIN_FUNC1 FUNC26-bit position 
SSCPIN_FUNC1 FUNC27-bit mask 
SSCPIN_FUNC1 FUNC27-bit position 
SSCPIN_FUNC1 FUNC28-bit mask 
SSCPIN_FUNC1 FUNC28-bit position 
SSCPIN_FUNC1 FUNC29-bit mask 
SSCPIN_FUNC1 FUNC29-bit position 
SSCPIN_FUNC1 FUNC30-bit mask 
SSCPIN_FUNC1 FUNC30-bit position 
SSCPIN_FUNC1 FUNC31-bit mask 
SSCPIN_FUNC1 FUNC31-bit position 
SSCPIN_GPIO_ENABLE GPIOENABLE-bit mask 
SSCPIN_GPIO_ENABLE GPIOENABLE-bit position 
SSCPIN_GPIO_PIN_PD GPIOPINPD-bit mask 
SSCPIN_GPIO_PIN_PD GPIOPINPD-bit position 
SSCPIN_GPIO_PIN_PU GPIOPINPU-bit mask 
SSCPIN_GPIO_PIN_PU GPIOPINPU-bit position 
SSCPIN_SETUP_DATA SETUP-bit mask 
SSCPIN_SETUP_DATA SETUP-bit position 
SSCPIN_SETUP_INDEX INDEX-bit mask 
SSCPIN_SETUP_INDEX INDEX-bit position 
SSCPORT_WAIT CYCLE-bit mask 
SSCPORT_WAIT CYCLE-bit position 
SSCREADTEST READTEST-bit mask 
SSCREADTEST READTEST-bit position 
SSCREVISION REVISION-bit mask 
SSCREVISION REVISION-bit position 
SSCSD_POWER_CLEAR PWR_PROT_CLR-bit mask 
SSCSD_POWER_CLEAR PWR_PROT_CLR-bit position 
SSCSD_POWER_SETUP PWR_INT_EN-bit mask 
SSCSD_POWER_SETUP PWR_INT_EN-bit position 
SSCSD_POWER_SETUP PWR_PROT_EN-bit mask 
SSCSD_POWER_SETUP PWR_PROT_EN-bit position 
SSCSD_POWER_STATUS PWR_PROT_PIN-bit mask 
SSCSD_POWER_STATUS PWR_PROT_PIN-bit position 
SSCSD_POWER_STATUS PWR_PROT_STATE-bit mask 
SSCSD_POWER_STATUS PWR_PROT_STATE-bit position 
SSCSGI_CLEAR SGI_CLEAR-bit mask 
SSCSGI_CLEAR SGI_CLEAR-bit position 
SSCSGI_SET SGI_SET-bit mask 
SSCSGI_SET SGI_SET-bit position 
SSCSGI_STATUS SGI_STATUS-bit mask 
SSCSGI_STATUS SGI_STATUS-bit position 
SSCSSP_SETUP SSP0_DIR-bit mask 
SSCSSP_SETUP SSP0_DIR-bit position 
SSCSSP_SETUP SSP0_MCLK_DIR-bit mask 
SSCSSP_SETUP SSP0_MCLK_DIR-bit position 
SSCSSP_SETUP SSP0_MCLK_DIV-bit mask 
SSCSSP_SETUP SSP0_MCLK_DIV-bit position 
SSCSSP_SETUP SSP0_MODE-bit mask 
SSCSSP_SETUP SSP0_MODE-bit position 
SSCSSP_SETUP SSP1_DIR-bit mask 
SSCSSP_SETUP SSP1_DIR-bit position 
SSCSSP_SETUP SSP1_MCLK_DIR-bit mask 
SSCSSP_SETUP SSP1_MCLK_DIR-bit position 
SSCSSP_SETUP SSP1_MCLK_DIV-bit mask 
SSCSSP_SETUP SSP1_MCLK_DIV-bit position 
SSCSSP_SETUP SSP1_MODE-bit mask 
SSCSSP_SETUP SSP1_MODE-bit position 
SSCSSP_SETUP SSP2_DIR-bit mask 
SSCSSP_SETUP SSP2_DIR-bit position 
SSCSSP_SETUP SSP2_MCLK_DIR-bit mask 
SSCSSP_SETUP SSP2_MCLK_DIR-bit position 
SSCSSP_SETUP SSP2_MCLK_DIV-bit mask 
SSCSSP_SETUP SSP2_MCLK_DIV-bit position 
SSCSSP_SETUP SSP2_MODE-bit mask 
SSCSSP_SETUP SSP2_MODE-bit position 
SSCSSP_SETUP SSP3_DIR-bit mask 
SSCSSP_SETUP SSP3_DIR-bit position 
SSCSSP_SETUP SSP3_MCLK_DIR-bit mask 
SSCSSP_SETUP SSP3_MCLK_DIR-bit position 
SSCSSP_SETUP SSP3_MCLK_DIV-bit mask 
SSCSSP_SETUP SSP3_MCLK_DIV-bit position 
SSCSSP_SETUP SSP3_MODE-bit mask 
SSCSSP_SETUP SSP3_MODE-bit position 
SSCTDM0_SETUP DIR_TX-bit mask 
SSCTDM0_SETUP DIR_TX-bit position 
SSCTDM0_SETUP FS_DIST-bit mask 
SSCTDM0_SETUP FS_DIST-bit position 
SSCTDM0_SETUP FS_POL-bit mask 
SSCTDM0_SETUP FS_POL-bit position 
SSCTDM0_SETUP FS_RXERR-bit mask 
SSCTDM0_SETUP FS_RXERR-bit position 
SSCTDM0_SETUP FS_TXPW-bit mask 
SSCTDM0_SETUP FS_TXPW-bit position 
SSCTDM0_SETUP SCLK_N-bit mask 
SSCTDM0_SETUP SCLK_N-bit position 
SSCTDM0_SETUP SCLK_POL-bit mask 
SSCTDM0_SETUP SCLK_POL-bit position 
SSCTDM0_SETUP ST_RX-bit mask 
SSCTDM0_SETUP ST_RX-bit position 
SSCTDM0_SETUP ST_TX-bit mask 
SSCTDM0_SETUP ST_TX-bit position 
SSCTDM0_SETUP TDM_EN-bit mask 
SSCTDM0_SETUP TDM_EN-bit position 
SSCTDM0_SETUP TDM_N-bit mask 
SSCTDM0_SETUP TDM_N-bit position 
SSCTDM1_SETUP DIR_TX-bit mask 
SSCTDM1_SETUP DIR_TX-bit position 
SSCTDM1_SETUP FS_DIST-bit mask 
SSCTDM1_SETUP FS_DIST-bit position 
SSCTDM1_SETUP FS_POL-bit mask 
SSCTDM1_SETUP FS_POL-bit position 
SSCTDM1_SETUP FS_RXERR-bit mask 
SSCTDM1_SETUP FS_RXERR-bit position 
SSCTDM1_SETUP FS_TXPW-bit mask 
SSCTDM1_SETUP FS_TXPW-bit position 
SSCTDM1_SETUP SCLK_N-bit mask 
SSCTDM1_SETUP SCLK_N-bit position 
SSCTDM1_SETUP SCLK_POL-bit mask 
SSCTDM1_SETUP SCLK_POL-bit position 
SSCTDM1_SETUP ST_RX-bit mask 
SSCTDM1_SETUP ST_RX-bit position 
SSCTDM1_SETUP ST_TX-bit mask 
SSCTDM1_SETUP ST_TX-bit position 
SSCTDM1_SETUP TDM_EN-bit mask 
SSCTDM1_SETUP TDM_EN-bit position 
SSCTDM1_SETUP TDM_N-bit mask 
SSCTDM1_SETUP TDM_N-bit position 
SSCTDM2_SETUP DIR_TX-bit mask 
SSCTDM2_SETUP DIR_TX-bit position 
SSCTDM2_SETUP FS_DIST-bit mask 
SSCTDM2_SETUP FS_DIST-bit position 
SSCTDM2_SETUP FS_POL-bit mask 
SSCTDM2_SETUP FS_POL-bit position 
SSCTDM2_SETUP FS_RXERR-bit mask 
SSCTDM2_SETUP FS_RXERR-bit position 
SSCTDM2_SETUP FS_TXPW-bit mask 
SSCTDM2_SETUP FS_TXPW-bit position 
SSCTDM2_SETUP SCLK_N-bit mask 
SSCTDM2_SETUP SCLK_N-bit position 
SSCTDM2_SETUP SCLK_POL-bit mask 
SSCTDM2_SETUP SCLK_POL-bit position 
SSCTDM2_SETUP ST_RX-bit mask 
SSCTDM2_SETUP ST_RX-bit position 
SSCTDM2_SETUP ST_TX-bit mask 
SSCTDM2_SETUP ST_TX-bit position 
SSCTDM2_SETUP TDM_EN-bit mask 
SSCTDM2_SETUP TDM_EN-bit position 
SSCTDM2_SETUP TDM_N-bit mask 
SSCTDM2_SETUP TDM_N-bit position 
SSCTDM3_SETUP DIR_TX-bit mask 
SSCTDM3_SETUP DIR_TX-bit position 
SSCTDM3_SETUP FS_DIST-bit mask 
SSCTDM3_SETUP FS_DIST-bit position 
SSCTDM3_SETUP FS_POL-bit mask 
SSCTDM3_SETUP FS_POL-bit position 
SSCTDM3_SETUP FS_RXERR-bit mask 
SSCTDM3_SETUP FS_RXERR-bit position 
SSCTDM3_SETUP FS_TXPW-bit mask 
SSCTDM3_SETUP FS_TXPW-bit position 
SSCTDM3_SETUP SCLK_N-bit mask 
SSCTDM3_SETUP SCLK_N-bit position 
SSCTDM3_SETUP SCLK_POL-bit mask 
SSCTDM3_SETUP SCLK_POL-bit position 
SSCTDM3_SETUP ST_RX-bit mask 
SSCTDM3_SETUP ST_RX-bit position 
SSCTDM3_SETUP ST_TX-bit mask 
SSCTDM3_SETUP ST_TX-bit position 
SSCTDM3_SETUP TDM_EN-bit mask 
SSCTDM3_SETUP TDM_EN-bit position 
SSCTDM3_SETUP TDM_N-bit mask 
SSCTDM3_SETUP TDM_N-bit position 
SSCTICK0_SETUP CLKSEL-bit mask 
SSCTICK0_SETUP CLKSEL-bit position 
SSCTICK0_SETUP DIVNUM-bit mask 
SSCTICK0_SETUP DIVNUM-bit position 
SSCTICK1_SETUP CLKSEL-bit mask 
SSCTICK1_SETUP CLKSEL-bit position 
SSCTICK1_SETUP DIVNUM-bit mask 
SSCTICK1_SETUP DIVNUM-bit position 
SSCTIM_SETUP TIM_DIR-bit mask 
SSCTIM_SETUP TIM_DIR-bit position 
SSCUSB_POWER_CLEAR PWR_PROT_CLR-bit mask 
SSCUSB_POWER_CLEAR PWR_PROT_CLR-bit position 
SSCUSB_POWER_SETUP PWR_INT_EN-bit mask 
SSCUSB_POWER_SETUP PWR_INT_EN-bit position 
SSCUSB_POWER_SETUP PWR_MODE-bit mask 
SSCUSB_POWER_SETUP PWR_MODE-bit position 
SSCUSB_POWER_SETUP PWR_PROT_EN-bit mask 
SSCUSB_POWER_SETUP PWR_PROT_EN-bit position 
SSCUSB_POWER_STATUS PWR_PROT_PIN-bit mask 
SSCUSB_POWER_STATUS PWR_PROT_PIN-bit position 
SSCUSB_POWER_STATUS PWR_PROT_STATE-bit mask 
SSCUSB_POWER_STATUS PWR_PROT_STATE-bit position 
SSCUSB_POWER_STATUS VBUS_PIN-bit mask 
SSCUSB_POWER_STATUS VBUS_PIN-bit position 
SSCVIDEOADC_MAXMIN MAX-bit mask 
SSCVIDEOADC_MAXMIN MAX-bit position 
SSCVIDEOADC_MAXMIN MIN-bit mask 
SSCVIDEOADC_MAXMIN MIN-bit position 
SSCVIDEOADC_SETUP ACQCLR-bit mask 
SSCVIDEOADC_SETUP ACQCLR-bit position 
SSCVIDEOADC_SETUP ACQEN-bit mask 
SSCVIDEOADC_SETUP ACQEN-bit position 
SSCVIDEOADC_SETUP CLHO-bit mask 
SSCVIDEOADC_SETUP CLHO-bit position 
SSCVIDEOADC_SETUP CTHO-bit mask 
SSCVIDEOADC_SETUP CTHO-bit position 
SSCVIDEOADC_SETUP DATEN-bit mask 
SSCVIDEOADC_SETUP DATEN-bit position 
SSCVIDEOADC_SETUP GHO-bit mask 
SSCVIDEOADC_SETUP GHO-bit position 
SSCWDTOUT_INTCLEAR CLEAR-bit mask 
SSCWDTOUT_INTCLEAR CLEAR-bit position 
SSCWDTOUT_INTMODE LEVEL-bit mask 
SSCWDTOUT_INTMODE LEVEL-bit position 
SSCWDTOUT_SETUP INIT-bit mask 
SSCWDTOUT_SETUP INIT-bit position 
SSCWDTOUT_SETUP OD-bit mask 
SSCWDTOUT_SETUP OD-bit position 
SSCWDTOUT_SETUP OUT-bit mask 
SSCWDTOUT_SETUP OUT-bit position 
SSCWDTOUT_SETUP WDT-bit mask 
SSCWDTOUT_SETUP WDT-bit position 
SSCWRITETEST WRITETEST-bit mask 
SSCWRITETEST WRITETEST-bit position 
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