1:
9:
10:
14:
15:
#ifndef _SPCPRM_H_
16:
#define _SPCPRM_H_
17:
18:
19:
#include <stdint.h>
20:
#include "lib_common/AG903_common.h"
21:
22:
#ifdef __cplusplus
23:
extern "C" {
24:
#endif
25:
26:
#define AG903_SPC_SWRSTMSK_REG_NUM (5)
27:
#define AG903_SPC_CA5CTRL_REG_NUM (11)
28:
29:
#define AG903_SPC_ETHER_MII (0)
30:
#define AG903_SPC_ETHER_RMII (1)
31:
32:
#define AG903_SPC_IDECLK_PLL0DIV4 (0)
33:
#define AG903_SPC_IDECLK_PLL0DIV3 (1)
34:
35:
#define AG903_SPC_USBCTRL_CLKSEL_MIIRXCLK (0)
36:
#define AG903_SPC_USBCTRL_CLKSEL_XOUT (1)
37:
38:
#define AG903_SPC_USBCTRL_XTLSEL_12MHZ (0)
39:
#define AG903_SPC_USBCTRL_XTLSEL_30MHZ (1)
40:
41:
42:
43:
enum _AG903_SSC_PLL1_CLKSRC {
44: AG903_SPC_PLL1_CLKSRC_XOUT = 0,
45: AG903_SPC_PLL1_CLKSRC_MIIRXCLK,
46: AG903_SPC_PLL1_CLKSRC_DVOCLK,
47: };
48:
49:
50:
enum _AG903_SSC_PLL2_CLKSRC {
51: AG903_SPC_PLL2_CLKSRC_XOUT = 0,
52: AG903_SPC_PLL2_CLKSRC_MIITXCLK,
53: AG903_SPC_PLL2_CLKSRC_DVO,
54: };
55:
56:
57:
enum _AG903_SSC_PLL3_CLKSRC {
58: AG903_SPC_PLL3_CLKSRC_XOUT = 0,
59: AG903_SPC_PLL3_CLKSRC_DVOCLK,
60: AG903_SPC_PLL3_CLKSRC_DVO,
61: AG903_SPC_PLL3_CLKSRC_SSPSEL,
62: };
63:
64:
65:
enum _AG903_SSC_PLL3_CLKSRC_SSP {
66: AG903_SPC_PLL3_CLKSRC_SSP0 = 0,
67: AG903_SPC_PLL3_CLKSRC_SSP1,
68: AG903_SPC_PLL3_CLKSRC_SSP2,
69: AG903_SPC_PLL3_CLKSRC_SSP3,
70: };
71:
72:
73:
enum _AG903_SSC_PLLA_CLKSRC {
74: AG903_SPC_PLLA_CLKSRC_OSC = 0,
75: AG903_SPC_PLLA_CLKSRC_DVOCLK,
76: AG903_SPC_PLLA_CLKSRC_DVO,
77: };
78:
79:
80:
enum _AG903_SSC_CP0_CLKSRC {
81: AG903_SPC_CP0_CLKSRC_DVOCLK = 0,
82: AG903_SPC_CP0_CLKSRC_PLL1,
83: AG903_SPC_CP0_CLKSRC_PLL3,
84: };
85:
86:
87:
enum _AG903_SSC_CP1_CLKSRC {
88: AG903_SPC_CP1_CLKSRC_PLL3 = 0,
89: AG903_SPC_CP1_CLKSRC_PLL2,
90: AG903_SPC_CP1_CLKSRC_DVO,
91: };
92:
93:
94:
enum _AG903_SSC_LVDS_CLKSRC {
95: AG903_SPC_LVDS_CLKSRC_DSP0 = 0,
96: AG903_SPC_LVDS_CLKSRC_DSP1,
97: };
98:
99:
100:
enum _AG903_SSC_DT0_CLKSRC {
101: AG903_SPC_DT0_CLKSRC_PLL1 = 0,
102: AG903_SPC_DT0_CLKSRC_DVOCLK,
103: };
104:
105:
106:
enum _AG903_SSC_DT1_CLKSRC {
107: AG903_SPC_DT1_CLKSRC_DSP0 = 0,
108: AG903_SPC_DT1_CLKSRC_PLL2,
109: AG903_SPC_DT1_CLKSRC_DVO,
110: };
111:
112:
113:
enum _AG903_SSC_HDA_CLKSRC {
114: AG903_SPC_HDA_CLKSRC_XOUT = 0,
115: AG903_SPC_HDA_CLKSRC_USBPHY,
116: AG903_SPC_HDA_CLKSRC_PLL3,
117: };
118:
119:
120:
enum _AG903_SSC_SSP_CLKSRC {
121: AG903_SPC_SSP_CLKSRC_MCLK = 0,
122: AG903_SPC_SSP_CLKSRC_ALT,
123: AG903_SPC_SSP_CLKSRC_XOUT,
124: AG903_SPC_SSP_CLKSRC_PLL3,
125: AG903_SPC_SSP_CLKSRC_PLL0,
126: };
127:
128:
129:
enum AG903_SPC_PLL_FR_ENUM{
130: AG903_SPC_PLL_FR_20_40MHZ = 0,
131: AG903_SPC_PLL_FR_40_75MHZ,
132: AG903_SPC_PLL_FR_75_150MHZ,
133: AG903_SPC_PLL_FR_150_300MHZ,
134: };
135:
136:
137:
138:
typedef struct _AG903_SPCPrmPllnParam{
139: uint8_t src;
140: uint8_t ns;
141: uint8_t ms;
142: uint8_t div;
143: uint8_t frange;
144: uint8_t en;
145: uint8_t reserve[2];
146: }
AG903_SPCPrmPllnParam;
147:
148:
149:
typedef struct _AG903_SPCPrmPllaParam{
150: uint8_t src;
151: uint8_t ns;
152: uint8_t ms;
153: uint8_t fr;
154: uint8_t div;
155: uint8_t en;
156: uint8_t cc;
157: uint8_t reserve[2];
158: }
AG903_SPCPrmPllaParam;
159:
160:
161:
typedef struct _AG903_SPCPrmSdmcMiscParam{
162: uint8_t hclk_sel;
163: uint8_t rclk_sel;
164: uint8_t wclk_sel;
165: uint8_t sref_ack;
166: uint8_t sref_req;
167: uint8_t clk_sel;
168: uint8_t reserve[2];
169: }
AG903_SPCPrmSdmcMiscParam;
170:
171:
172:
typedef struct _AG903_SPCPrmClkSel{
173: uint8_t cp1;
174: uint8_t cp0;
175: uint8_t lvds;
176: uint8_t dt1;
177: uint8_t dt0;
178: uint8_t hda;
179: uint8_t reserve[2];
180: }
AG903_SPCPrmClkSel;
181:
182:
183:
typedef struct _AG903_SPCPrmSspClkSel{
184: uint8_t pll3;
185: uint8_t ssp3;
186: uint8_t ssp2;
187: uint8_t ssp1;
188: uint8_t ssp0;
189: uint8_t reserve[3];
190: }
AG903_SPCPrmSspClkSel;
191:
192:
193:
typedef struct _AG903_SPCPrmSspClkDiv{
194: uint8_t ssp3;
195: uint8_t ssp2;
196: uint8_t ssp1;
197: uint8_t ssp0;
198: }
AG903_SPCPrmSspClkDiv;
199:
200:
201:
typedef struct _AG903_SPCPrmVideoAdcParam{
202: uint8_t clmp_en3;
203: uint8_t clmp_en2;
204: uint8_t clmp_en1;
205: uint8_t clmp_en0;
206: uint8_t clmp_lv3;
207: uint8_t clmp_lv2;
208: uint8_t clmp_lv1;
209: uint8_t clmp_lv0;
210: uint8_t gain3;
211: uint8_t gain2;
212: uint8_t gain1;
213: uint8_t gain0;
214: uint8_t clmp_imp;
215: uint8_t aaf_ctrl;
216: uint8_t qntzr_bias_up;
217: uint8_t input_range;
218: uint8_t ref_bias_up;
219: uint8_t reserve[3];
220: }
AG903_SPCPrmVideoAdcParam;
221:
222:
223:
typedef struct _AG903_SPCPrmVideoAdcEnable{
224: uint8_t adc;
225: uint8_t ch3;
226: uint8_t ch2;
227: uint8_t ch1;
228: uint8_t ch0;
229: uint8_t reserve[3];
230: }
AG903_SPCPrmVideoAdcEnable;
231:
232:
233:
typedef struct _AG903_SPCPrmUsbMiscCtrl{
234: uint8_t suspend;
235: uint8_t wakeup;
236: uint8_t squelch;
237: uint8_t pll_aliv;
238: uint8_t xtl_sel;
239: uint8_t oscout;
240: uint8_t reserve[2];
241: }
AG903_SPCPrmUsbMiscCtrl;
242:
243:
244:
void AG903_SPCPrmGetBootupStatus(uint8_t* pwr, uint8_t* wdt_rst, uint8_t* hw_rst);
245:
void AG903_SPCPrmClrBootupStatus(uint8_t pwr, uint8_t wdt_rst, uint8_t hw_rst);
246:
void AG903_SPCPrmSetFcsCtrl(uint8_t slf_refresh, uint8_t pll0_rst, uint8_t cpu_msk, uint8_t enable);
247:
void AG903_SPCPrmGetFcsCtrl(uint8_t* slf_refresh, uint8_t* pll0_rst, uint8_t* cpu_msk, uint8_t* enable);
248:
void AG903_SPCPrmSwReset(
void);
249:
void AG903_SPCPrmGetFcsIntStatus(uint8_t* status);
250:
void AG903_SPCPrmClrFcsIntStatus(
void);
251:
void AG903_SPCPrmSetFcsIntEnable(uint8_t enable);
252:
void AG903_SPCPrmGetFcsIntEnable(uint8_t* enable);
253:
void AG903_SPCPrmSetSoftResetSetup(uint8_t wait, uint8_t active);
254:
void AG903_SPCPrmGetSoftResetSetup(uint8_t* wait, uint8_t* active);
255:
void AG903_SPCPrmSetPll0Ctrl(
AG903_SPCPrmPllnParam* param);
256:
void AG903_SPCPrmGetPll0Ctrl(
AG903_SPCPrmPllnParam* param, uint8_t* status);
257:
void AG903_SPCPrmSetDdrPhyPll(uint8_t enable);
258:
void AG903_SPCPrmGetDdrPhyPll(uint8_t* enable);
259:
void AG903_SPCPrmSetDdrPhyDll(uint8_t frange, uint8_t enable);
260:
void AG903_SPCPrmGetDdrPhyDll(uint8_t* frange, uint8_t* enable);
261:
void AG903_SPCPrmSetAhbClkCtrl(uint32_t clk_en);
262:
void AG903_SPCPrmGetAhbClkCtrl(uint32_t* clk_en);
263:
void AG903_SPCPrmSetApbClkCtrl(uint32_t clk_en);
264:
void AG903_SPCPrmGetApbClkCtrl(uint32_t* clk_en);
265:
void AG903_SPCPrmSetAxiClkCtrl1(uint32_t clk_en);
266:
void AG903_SPCPrmGetAxiClkCtrl1(uint32_t* clk_en);
267:
void AG903_SPCPrmSetAxiClkCtrl2(uint32_t clk_en);
268:
void AG903_SPCPrmGetAxiClkCtrl2(uint32_t* clk_en);
269:
void AG903_SPCPrmSetPll1Ctrl(
AG903_SPCPrmPllnParam* param);
270:
void AG903_SPCPrmGetPll1Ctrl(
AG903_SPCPrmPllnParam* param);
271:
void AG903_SPCPrmSetPll2Ctrl(
AG903_SPCPrmPllnParam* param);
272:
void AG903_SPCPrmGetPll2Ctrl(
AG903_SPCPrmPllnParam* param);
273:
void AG903_SPCPrmSetPll3Ctrl(
AG903_SPCPrmPllnParam* param);
274:
void AG903_SPCPrmGetPll3Ctrl(
AG903_SPCPrmPllnParam* param);
275:
void AG903_SPCPrmSetPllACtrl(
AG903_SPCPrmPllaParam* param);
276:
void AG903_SPCPrmGetPllACtrl(
AG903_SPCPrmPllaParam* param);
277:
void AG903_SPCPrmSetSwResetMask(uint8_t reg_no, uint32_t msk);
278:
void AG903_SPCPrmGetSwResetMask(uint8_t reg_no, uint32_t* msk);
279:
void AG903_SPCPrmSetApbSdmcClkCtrl(uint8_t sdmclk, uint32_t pclk);
280:
void AG903_SPCPrmGetApbSdmcClkCtrl(uint8_t* sdmclk, uint32_t* pclk);
281:
void AG903_SPCPrmSetMiscClkCtrl(uint32_t sclk);
282:
void AG903_SPCPrmGetMiscClkCtrl(uint32_t* sclk);
283:
void AG903_SPCPrmGetPinStatus(uint8_t* test, uint8_t* mode);
284:
void AG903_SPCPrmSetSdmcMiscCtrl(
AG903_SPCPrmSdmcMiscParam* param);
285:
void AG903_SPCPrmGetSdmcMiscCtrl(
AG903_SPCPrmSdmcMiscParam* param);
286:
void AG903_SPCPrmSetDdrMiscCtrl(uint8_t refresh);
287:
void AG903_SPCPrmGetDdrMiscCtrl(uint8_t* init, uint8_t* refresh);
288:
void AG903_SPCPrmSetSpiromMiscCtrl(uint8_t addr_cyc);
289:
void AG903_SPCPrmGetSpiromMiscCtrl(uint8_t* addr_cyc);
290:
void AG903_SPCPrmSetClkSrc(
AG903_SPCPrmClkSel* clk_src);
291:
void AG903_SPCPrmGetClkSrc(
AG903_SPCPrmClkSel* clk_src);
292:
void AG903_SPCPrmSetSspClkSrc(
AG903_SPCPrmSspClkSel* clk_src);
293:
void AG903_SPCPrmGetSspClkSrc(
AG903_SPCPrmSspClkSel* clk_src);
294:
void AG903_SPCPrmSetSspClkDiv(
AG903_SPCPrmSspClkDiv* clk_div);
295:
void AG903_SPCPrmGetSspClkDiv(
AG903_SPCPrmSspClkDiv* clk_div);
296:
void AG903_SPCPrmSetEtherPhy(uint8_t phy);
297:
void AG903_SPCPrmGetEtherPhy(uint8_t* phy);
298:
void AG903_SPCPrmSetCpuMiscCtrl(uint8_t reg_no, uint32_t val);
299:
void AG903_SPCPrmGetCpuMiscCtrl(uint8_t reg_no, uint32_t* val);
300:
void AG903_SPCPrmSetVideoAdcCtrl(
AG903_SPCPrmVideoAdcParam* param,
AG903_SPCPrmVideoAdcEnable* enable);
301:
void AG903_SPCPrmGetVideoAdcCtrl(
AG903_SPCPrmVideoAdcParam* param,
AG903_SPCPrmVideoAdcEnable* enable);
302:
void AG903_SPCPrmSetLvdsTx(uint8_t rf_ch0, uint8_t rf_ch1);
303:
void AG903_SPCPrmGetLvdsTx(uint8_t* rf_ch0, uint8_t* rf_ch1);
304:
void AG903_SPCPrmSetUsbMiscCtrl1(uint8_t clk_div, uint8_t clk_sel);
305:
void AG903_SPCPrmGetUsbMiscCtrl1(uint8_t* clk_div, uint8_t* clk_sel, uint8_t* vbus, uint8_t* vprtct);
306:
void AG903_SPCPrmSetUsbMiscCtrl2(
AG903_SPCPrmUsbMiscCtrl* param);
307:
void AG903_SPCPrmGetUsbMiscCtrl2(
AG903_SPCPrmUsbMiscCtrl* param);
308:
void AG903_SPCPrmSetDdrPhySetup(uint8_t pd_gain, uint8_t afl_gain);
309:
void AG903_SPCPrmGetDdrPhySetup(uint8_t* pd_gain, uint8_t* afl_gain);
310:
void AG903_SPCPrmSetBootSwapCtrl(uint8_t swap);
311:
void AG903_SPCPrmGetBootSwapCtrl(uint8_t* swap);
312:
void AG903_SPCPrmSetIdeClk(uint8_t clk_sel);
313:
void AG903_SPCPrmGetIdeClk(uint8_t* clk_sel);
314:
315:
316:
#ifdef __cplusplus
317: }
318:
#endif
319:
#endif