AG903ライブラリリファレンス
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1: 8: 9: 13: 14: #ifndef _AG903_SPI_REGMAP_H_ 15: #define _AG903_SPI_REGMAP_H_ 16: 17: 18: #include "AG903_regmap.h" 19: 20: #ifndef __I 21: 22: #define __I volatile const 23: #endif 24: #ifndef __O 25: 26: #define __O volatile 27: #endif 28: #ifndef __IO 29: 30: #define __IO volatile 31: #endif 32: 33: 34: typedef struct { 35: 36: union { 37: __IO uint32_t CMDW0; 38: }; 39: 40: union { 41: __IO uint32_t CMDW1; 42: 43: struct { 44: __IO uint32_t ADDR_LEN : 3; 45: uint32_t : 13; 46: __IO uint32_t DUM2_CYC : 8; 47: __IO uint32_t INST_LEN : 2; 48: uint32_t : 2; 49: __IO uint32_t CONT_READ : 1; 50: } CMDW1_bits; 51: }; 52: 53: union { 54: __IO uint32_t CMDW2; 55: }; 56: 57: union { 58: __IO uint32_t CMDW3; 59: 60: struct { 61: uint32_t : 1; 62: __IO uint32_t WE_EN : 1; 63: __IO uint32_t RD_STAT_EN : 1; 64: __IO uint32_t RD_STAT : 1; 65: __IO uint32_t DTR_MODE : 1; 66: __IO uint32_t SPI_MODE : 3; 67: __IO uint32_t START_CS : 2; 68: uint32_t : 6; 69: __IO uint32_t CONT_CODE : 8; 70: __IO uint32_t INST_CODE : 8; 71: } CMDW3_bits; 72: }; 73: 74: union { 75: __IO uint32_t CTRL; 76: 77: struct { 78: __IO uint32_t CLK_DIV : 2; 79: uint32_t : 2; 80: __IO uint32_t CLK_MODE : 1; 81: uint32_t : 3; 82: __IO uint32_t ABORT : 1; 83: uint32_t : 7; 84: __IO uint32_t RDY_LOC : 3; 85: uint32_t : 1; 86: __IO uint32_t DAMR : 1; 87: } CTRL_bits; 88: }; 89: 90: union { 91: __IO uint32_t TIMING; 92: 93: struct { 94: __IO uint32_t CS_DLY : 4; 95: } TIMING_bits; 96: }; 97: 98: union { 99: __I uint32_t FIFOSTAT; 100: 101: struct { 102: __I uint32_t TX_RDY : 1; 103: __I uint32_t RX_RDY : 1; 104: } FIFOSTAT_bits; 105: }; 106: 107: __I uint32_t RESERVED1[1]; 108: 109: union { 110: __IO uint32_t INTCTRL; 111: 112: struct { 113: __IO uint32_t DMA_EN : 1; 114: __IO uint32_t COMP_EN : 1; 115: uint32_t : 6; 116: __IO uint32_t TX_TH : 2; 117: uint32_t : 2; 118: __IO uint32_t RX_TH : 2; 119: } INTCTRL_bits; 120: }; 121: 122: union { 123: __IO uint32_t INTSTAT; 124: 125: struct { 126: __IO uint32_t COMP : 1; 127: } INTSTAT_bits; 128: }; 129: 130: union { 131: __I uint32_t READSTAT; 132: 133: struct { 134: __I uint32_t READ : 8; 135: } READSTAT_bits; 136: }; 137: 138: union { 139: __IO uint32_t ADDRMASK; 140: }; 141: 142: __I uint32_t RESERVED2[8]; 143: 144: union { 145: __I uint32_t REVISION; 146: }; 147: 148: union { 149: __I uint32_t FEATURE; 150: 151: struct { 152: __I uint32_t TX_DEPTH : 8; 153: __I uint32_t RX_DEPTH : 8; 154: uint32_t : 3; 155: __I uint32_t AXI_ID_DW : 5; 156: __I uint32_t DTR_MODE : 1; 157: __I uint32_t CLK_MODE : 1; 158: uint32_t : 3; 159: __I uint32_t DAMR_PORT : 1; 160: __I uint32_t HOST_IF_DW : 1; 161: __I uint32_t HOST_IF : 1; 162: } FEATURE_bits; 163: }; 164: 165: __I uint32_t RESERVED3[42]; 166: 167: union { 168: __IO uint32_t DATAPORT; 169: }; 170: 171: 172: }AG903_SPI_Type; 173: 174: #define AG903_SPI ((volatile AG903_SPI_Type *) AG903_SPI_BASE) 175: 176: 177: #define AG903_SPI_CMDW0_ADDRESS_POS 0 178: #define AG903_SPI_CMDW0_ADDRESS_MSK (0xffffffffUL << AG903_SPI_CMDW0_ADDRESS_POS) 179: 180: #define AG903_SPI_CMDW1_ADDR_LEN_POS 0 181: #define AG903_SPI_CMDW1_ADDR_LEN_MSK (0x7UL << AG903_SPI_CMDW1_ADDR_LEN_POS) 182: #define AG903_SPI_CMDW1_DUM2_CYC_POS 16 183: #define AG903_SPI_CMDW1_DUM2_CYC_MSK (0xffUL << AG903_SPI_CMDW1_DUM2_CYC_POS) 184: #define AG903_SPI_CMDW1_INST_LEN_POS 24 185: #define AG903_SPI_CMDW1_INST_LEN_MSK (0x3UL << AG903_SPI_CMDW1_INST_LEN_POS) 186: #define AG903_SPI_CMDW1_CONT_READ_POS 28 187: #define AG903_SPI_CMDW1_CONT_READ_MSK (0x1UL << AG903_SPI_CMDW1_CONT_READ_POS) 188: 189: #define AG903_SPI_CMDW2_DAT_CNT_POS 0 190: #define AG903_SPI_CMDW2_DAT_CNT_MSK (0xffffffffUL << AG903_SPI_CMDW2_DAT_CNT_POS) 191: 192: #define AG903_SPI_CMDW3_WE_EN_POS 1 193: #define AG903_SPI_CMDW3_WE_EN_MSK (0x1UL << AG903_SPI_CMDW3_WE_EN_POS) 194: #define AG903_SPI_CMDW3_RD_STAT_EN_POS 2 195: #define AG903_SPI_CMDW3_RD_STAT_EN_MSK (0x1UL << AG903_SPI_CMDW3_RD_STAT_EN_POS) 196: #define AG903_SPI_CMDW3_RD_STAT_POS 3 197: #define AG903_SPI_CMDW3_RD_STAT_MSK (0x1UL << AG903_SPI_CMDW3_RD_STAT_POS) 198: #define AG903_SPI_CMDW3_DTR_MODE_POS 4 199: #define AG903_SPI_CMDW3_DTR_MODE_MSK (0x1UL << AG903_SPI_CMDW3_DTR_MODE_POS) 200: #define AG903_SPI_CMDW3_SPI_MODE_POS 5 201: #define AG903_SPI_CMDW3_SPI_MODE_MSK (0x7UL << AG903_SPI_CMDW3_SPI_MODE_POS) 202: #define AG903_SPI_CMDW3_START_CS_POS 8 203: #define AG903_SPI_CMDW3_START_CS_MSK (0x3UL << AG903_SPI_CMDW3_START_CS_POS) 204: #define AG903_SPI_CMDW3_CONT_CODE_POS 16 205: #define AG903_SPI_CMDW3_CONT_CODE_MSK (0xffUL << AG903_SPI_CMDW3_CONT_CODE_POS) 206: #define AG903_SPI_CMDW3_INST_CODE_POS 24 207: #define AG903_SPI_CMDW3_INST_CODE_MSK (0xffUL << AG903_SPI_CMDW3_INST_CODE_POS) 208: 209: #define AG903_SPI_CTRL_CLK_DIV_POS 0 210: #define AG903_SPI_CTRL_CLK_DIV_MSK (0x3UL << AG903_SPI_CTRL_CLK_DIV_POS) 211: #define AG903_SPI_CTRL_CLK_MODE_POS 4 212: #define AG903_SPI_CTRL_CLK_MODE_MSK (0x1UL << AG903_SPI_CTRL_CLK_MODE_POS) 213: #define AG903_SPI_CTRL_ABORT_POS 8 214: #define AG903_SPI_CTRL_ABORT_MSK (0x1UL << AG903_SPI_CTRL_ABORT_POS) 215: #define AG903_SPI_CTRL_RDY_LOC_POS 16 216: #define AG903_SPI_CTRL_RDY_LOC_MSK (0x7UL << AG903_SPI_CTRL_RDY_LOC_POS) 217: #define AG903_SPI_CTRL_DAMR_POS 20 218: #define AG903_SPI_CTRL_DAMR_MSK (0x1UL << AG903_SPI_CTRL_DAMR_POS) 219: 220: #define AG903_SPI_TIMING_CS_DLY_POS 0 221: #define AG903_SPI_TIMING_CS_DLY_MSK (0xfUL << AG903_SPI_TIMING_CS_DLY_POS) 222: 223: #define AG903_SPI_FIFOSTAT_TX_RDY_POS 0 224: #define AG903_SPI_FIFOSTAT_TX_RDY_MSK (0x1UL << AG903_SPI_FIFOSTAT_TX_RDY_POS) 225: #define AG903_SPI_FIFOSTAT_RX_RDY_POS 1 226: #define AG903_SPI_FIFOSTAT_RX_RDY_MSK (0x1UL << AG903_SPI_FIFOSTAT_RX_RDY_POS) 227: 228: #define AG903_SPI_INTCTRL_DMA_EN_POS 0 229: #define AG903_SPI_INTCTRL_DMA_EN_MSK (0x1UL << AG903_SPI_INTCTRL_DMA_EN_POS) 230: #define AG903_SPI_INTCTRL_COMP_EN_POS 1 231: #define AG903_SPI_INTCTRL_COMP_EN_MSK (0x1UL << AG903_SPI_INTCTRL_COMP_EN_POS) 232: #define AG903_SPI_INTCTRL_TX_TH_POS 8 233: #define AG903_SPI_INTCTRL_TX_TH_MSK (0x3UL << AG903_SPI_INTCTRL_TX_TH_POS) 234: #define AG903_SPI_INTCTRL_RX_TH_POS 12 235: #define AG903_SPI_INTCTRL_RX_TH_MSK (0x3UL << AG903_SPI_INTCTRL_RX_TH_POS) 236: 237: #define AG903_SPI_INTSTAT_COMP_POS 0 238: #define AG903_SPI_INTSTAT_COMP_MSK (0x1UL << AG903_SPI_INTSTAT_COMP_POS) 239: 240: #define AG903_SPI_READSTAT_READ_POS 0 241: #define AG903_SPI_READSTAT_READ_MSK (0xffUL << AG903_SPI_READSTAT_READ_POS) 242: 243: #define AG903_SPI_ADDRMASK_ADDR_MASK_POS 0 244: #define AG903_SPI_ADDRMASK_ADDR_MASK_MSK (0xffffffffUL << AG903_SPI_ADDRMASK_ADDR_MASK_POS) 245: 246: #define AG903_SPI_REVISION_REVISION_POS 0 247: #define AG903_SPI_REVISION_REVISION_MSK (0xffffffffUL << AG903_SPI_REVISION_REVISION_POS) 248: 249: #define AG903_SPI_FEATURE_TX_DEPTH_POS 0 250: #define AG903_SPI_FEATURE_TX_DEPTH_MSK (0xffUL << AG903_SPI_FEATURE_TX_DEPTH_POS) 251: #define AG903_SPI_FEATURE_RX_DEPTH_POS 8 252: #define AG903_SPI_FEATURE_RX_DEPTH_MSK (0xffUL << AG903_SPI_FEATURE_RX_DEPTH_POS) 253: #define AG903_SPI_FEATURE_AXI_ID_DW_POS 19 254: #define AG903_SPI_FEATURE_AXI_ID_DW_MSK (0x1fUL << AG903_SPI_FEATURE_AXI_ID_DW_POS) 255: #define AG903_SPI_FEATURE_DTR_MODE_POS 24 256: #define AG903_SPI_FEATURE_DTR_MODE_MSK (0x1UL << AG903_SPI_FEATURE_DTR_MODE_POS) 257: #define AG903_SPI_FEATURE_CLK_MODE_POS 25 258: #define AG903_SPI_FEATURE_CLK_MODE_MSK (0x1UL << AG903_SPI_FEATURE_CLK_MODE_POS) 259: #define AG903_SPI_FEATURE_DAMR_PORT_POS 29 260: #define AG903_SPI_FEATURE_DAMR_PORT_MSK (0x1UL << AG903_SPI_FEATURE_DAMR_PORT_POS) 261: #define AG903_SPI_FEATURE_HOST_IF_DW_POS 30 262: #define AG903_SPI_FEATURE_HOST_IF_DW_MSK (0x1UL << AG903_SPI_FEATURE_HOST_IF_DW_POS) 263: #define AG903_SPI_FEATURE_HOST_IF_POS 31 264: #define AG903_SPI_FEATURE_HOST_IF_MSK (0x1UL << AG903_SPI_FEATURE_HOST_IF_POS) 265: 266: #define AG903_SPI_DATAPORT_DATAPORT_POS 0 267: #define AG903_SPI_DATAPORT_DATAPORT_MSK (0xffffffffUL << AG903_SPI_DATAPORT_DATAPORT_POS) 268: 269: #endif 270:
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