AG903ライブラリリファレンス
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1: 10: 11: 15: 16: 17: #include "AG903_errno.h" 18: #include "AG903_common.h" 19: #include "timr/timrprm.h" 20: #include "register/AG903_timreg.h" 21: 22: 23: #define AG903_TIMR_READ_REGn(CH,REG) (AG903_TIMn(CH)->REG) 24: #define AG903_TIMR_READ_FLDn(CH,REG,POS,MSK) ( ( (AG903_TIMn(CH)->REG) & MSK ) >> POS ) 25: #define AG903_TIMR_WRITE_REGn(CH,REG,VAL) (AG903_TIMn(CH)->REG = (uint32_t)(VAL)) 26: #define AG903_TIMR_CLR_REGn(CH,REG,VAL) (AG903_TIMn(CH)->REG &= (uint32_t)(~VAL)) 27: #define AG903_TIMR_SET_REGn(CH,REG,VAL) (AG903_TIMn(CH)->REG |= (uint32_t)(VAL)) 28: #define AG903_TIMR_WRITE_REG(REG,VAL) (AG903_TIM->REG = (uint32_t)(VAL)) 29: 30: 31: 38: void AG903_TIMRPrmSetInMode(uint8_t ch, AG903_TIMRPrmInModeParam* param) 39: { 40: uint32_t val=0; 41: 42: ASSERT(AG903_TIMR_CH_NUM > ch); 43: ASSERT(NULL != param); 44: 45: val |= (param->eve&0x3F); 46: val <<= 6; 47: val |= (param->lo&0x01); 48: val <<= 2; 49: val |= (param->ch&0x03); 50: val <<= 8; 51: val |= (param->pol&0x01); 52: val <<= 8; 53: val |= (param->res&0x03); 54: 55: AG903_TIMR_WRITE_REGn(ch,INMOD,val); 56: 57: return; 58: } 59: 60: 67: void AG903_TIMRPrmSetOutMode(uint8_t ch, AG903_TIMRPrmOutModeParam* param) 68: { 69: uint32_t val=0; 70: 71: ASSERT(AG903_TIMR_CH_NUM > ch); 72: ASSERT(NULL != param); 73: 74: val |= (param->cm&0x01); 75: val <<= 1; 76: val |= (param->ovf&0x01); 77: val <<= 8; 78: val |= (param->ch&0x03); 79: val <<= 8; 80: val |= (param->pol&0x01); 81: val <<= 8; 82: val |= (param->mod&0x03); 83: 84: AG903_TIMR_WRITE_REGn(ch,OUTMOD,val); 85: 86: return; 87: } 88: 89: 96: void AG903_TIMRPrmSetResetTrigger(uint8_t ch, AG903_TIMRPrmResetTriggerParam* param) 97: { 98: uint32_t val=0; 99: 100: ASSERT(AG903_TIMR_CH_NUM > ch); 101: ASSERT(NULL != param); 102: 103: val |= (param->eve&0x3F); 104: val <<= 6; 105: val |= (param->lo&0x01); 106: val <<= 2; 107: val |= (param->ch&0x03); 108: val <<= 8; 109: val |= (param->pol&0x01); 110: val <<= 4; 111: val |= (param->res&0x03); 112: val <<= 2; 113: val |= (param->boot&0x03); 114: val <<= 2; 115: val |= (param->en&0x03); 116: 117: AG903_TIMR_WRITE_REGn(ch,RSTTRG,val); 118: 119: return; 120: } 121: 122: 129: void AG903_TIMRPrmEnableOneshot(uint8_t ch) 130: { 131: ASSERT(AG903_TIMR_CH_NUM > ch); 132: AG903_TIMR_SET_REGn(ch,CTRL,(1<<AG903_TIMn_CTRL_OS_POS)); 133: return; 134: } 135: 136: 143: void AG903_TIMRPrmDisableOneshot(uint8_t ch) 144: { 145: ASSERT(AG903_TIMR_CH_NUM > ch); 146: AG903_TIMR_CLR_REGn(ch,CTRL,(1<<AG903_TIMn_CTRL_OS_POS)); 147: return; 148: } 149: 150: 158: void AG903_TIMRPrmSetCntMode(uint8_t ch, uint8_t mode) 159: { 160: ASSERT(AG903_TIMR_CH_NUM > ch); 161: AG903_TIMR_CLR_REGn(ch,CTRL,AG903_TIMn_CTRL_MOD_MSK); 162: AG903_TIMR_SET_REGn(ch,CTRL,(mode<<AG903_TIMn_CTRL_MOD_POS)); 163: return; 164: } 165: 166: 173: void AG903_TIMRPrmGetCntMode(uint8_t ch, uint8_t* mode) 174: { 175: ASSERT(AG903_TIMR_CH_NUM > ch); 176: ASSERT(NULL != mode); 177: (*mode) = AG903_TIMR_READ_FLDn(ch,CTRL,AG903_TIMn_CTRL_MOD_POS,AG903_TIMn_CTRL_MOD_MSK); 178: return; 179: } 180: 181: 189: void AG903_TIMRPrmSetCount(uint8_t ch, uint32_t count) 190: { 191: ASSERT(AG903_TIMR_CH_NUM > ch); 192: AG903_TIMR_WRITE_REGn(ch,CNT,count); 193: return; 194: } 195: 196: 203: void AG903_TIMRPrmGetCount(uint8_t ch, uint32_t* count) 204: { 205: ASSERT(AG903_TIMR_CH_NUM > ch); 206: ASSERT(NULL != count); 207: (*count) = AG903_TIMR_READ_REGn(ch,CNT); 208: return; 209: } 210: 211: 218: void AG903_TIMRPrmSetPeriod(uint8_t ch, uint32_t period) 219: { 220: ASSERT(AG903_TIMR_CH_NUM > ch); 221: AG903_TIMR_WRITE_REGn(ch,PERIOD,period); 222: return; 223: } 224: 225: 232: void AG903_TIMRPrmGetPeriod(uint8_t ch, uint32_t* period) 233: { 234: ASSERT(AG903_TIMR_CH_NUM > ch); 235: ASSERT(NULL != period); 236: (*period) = AG903_TIMR_READ_REGn(ch,PERIOD); 237: return; 238: } 239: 240: 247: void AG903_TIMRPrmSetMatch(uint8_t ch, uint32_t match) 248: { 249: ASSERT(AG903_TIMR_CH_NUM > ch); 250: AG903_TIMR_WRITE_REGn(ch,MATCH,match); 251: return; 252: } 253: 254: 261: void AG903_TIMRPrmGetMatch(uint8_t ch, uint32_t* match) 262: { 263: ASSERT(AG903_TIMR_CH_NUM > ch); 264: ASSERT(NULL != match); 265: (*match) = AG903_TIMR_READ_REGn(ch,MATCH); 266: return; 267: } 268: 269: 276: void AG903_TIMRPrmSetPluseWidth(uint8_t ch, uint32_t width) 277: { 278: ASSERT(AG903_TIMR_CH_NUM > ch); 279: AG903_TIMR_WRITE_REGn(ch,PULWID,(width&AG903_TIMn_PULWID_VAL_MSK)); 280: return; 281: } 282: 283: 290: void AG903_TIMRPrmGetPluseWidth(uint8_t ch, uint32_t* width) 291: { 292: ASSERT(AG903_TIMR_CH_NUM > ch); 293: ASSERT(NULL != width); 294: (*width) = AG903_TIMR_READ_FLDn(ch,PULWID,AG903_TIMn_PULWID_VAL_POS,AG903_TIMn_PULWID_VAL_MSK); 295: return; 296: } 297: 298: 307: void AG903_TIMRPrmEnableMask(uint8_t ch, uint32_t setbit) 308: { 309: ASSERT(AG903_TIMR_CH_NUM > ch); 310: AG903_TIMR_SET_REGn(ch,INTMASK,setbit); 311: return; 312: } 313: 314: 323: void AG903_TIMRPrmDisableMask(uint8_t ch, uint32_t clrbit) 324: { 325: ASSERT(AG903_TIMR_CH_NUM > ch); 326: AG903_TIMR_CLR_REGn(ch,INTMASK,clrbit); 327: return; 328: } 329: 330: 339: void AG903_TIMRPrmEnableEventTrigger(uint8_t ch, uint32_t setbit) 340: { 341: ASSERT(AG903_TIMR_CH_NUM > ch); 342: AG903_TIMR_SET_REGn(ch,TRIGGER,setbit); 343: return; 344: } 345: 346: 355: void AG903_TIMRPrmDisableEventTrigger(uint8_t ch, uint32_t clrbit) 356: { 357: ASSERT(AG903_TIMR_CH_NUM > ch); 358: AG903_TIMR_CLR_REGn(ch,TRIGGER,clrbit); 359: return; 360: } 361: 362: 371: void AG903_TIMRPrmEnableDmaRequest(uint8_t ch, uint32_t setbit) 372: { 373: ASSERT(AG903_TIMR_CH_NUM > ch); 374: AG903_TIMR_SET_REGn(ch,DMAREQ,setbit); 375: return; 376: } 377: 378: 387: void AG903_TIMRPrmDisableDmaRequest(uint8_t ch, uint32_t clrbit) 388: { 389: ASSERT(AG903_TIMR_CH_NUM > ch); 390: AG903_TIMR_CLR_REGn(ch,DMAREQ,clrbit); 391: return; 392: } 393: 394: 401: void AG903_TIMRPrmGetStatus(uint8_t ch, uint32_t* status) 402: { 403: ASSERT(AG903_TIMR_CH_NUM > ch); 404: ASSERT(NULL != status); 405: (*status) = AG903_TIMR_READ_REGn(ch,STAT); 406: return; 407: } 408: 409: 419: void AG903_TIMRPrmClearStatus(uint8_t ch, uint32_t setbit) 420: { 421: ASSERT(AG903_TIMR_CH_NUM > ch); 422: AG903_TIMR_WRITE_REGn(ch,CLR,setbit); 423: return; 424: } 425: 426: 436: void AG903_TIMRPrmSetBootTrigger(uint8_t chbit) 437: { 438: AG903_TIMR_WRITE_REG(BOOTTRG,chbit); 439: return; 440: }
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