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AG903_sdmcreg.h

SDMC Register Definition

SDMC Register Definition

none

AXELL CORPORATION

2017_10_20 Auto-generated.

1: 8: 9: 13: 14: #ifndef _AG903_SDMC_REGMAP_H_ 15: #define _AG903_SDMC_REGMAP_H_ 16: 17: 18: #include "AG903_regmap.h" 19: 20: #ifndef __I 21: 22: #define __I volatile const 23: #endif 24: #ifndef __O 25: 26: #define __O volatile 27: #endif 28: #ifndef __IO 29: 30: #define __IO volatile 31: #endif 32: 33: 34: typedef struct { 35: 36: union { 37: __IO uint32_t SDRAM_Timing_1; 38: 39: struct { 40: __IO uint32_t TCL : 2; 41: uint32_t : 2; 42: __IO uint32_t TWR : 2; 43: uint32_t : 2; 44: __IO uint32_t TRF : 4; 45: __IO uint32_t TRCD : 3; 46: uint32_t : 1; 47: __IO uint32_t TRP : 4; 48: __IO uint32_t TRAS : 4; 49: } SDRAM_Timing_1_bits; 50: }; 51: 52: union { 53: __IO uint32_t SDRAM_Timing_2; 54: 55: struct { 56: __IO uint32_t REF_INTV : 16; 57: __IO uint32_t INI_REFT : 4; 58: __IO uint32_t INI_PREC : 4; 59: } SDRAM_Timing_2_bits; 60: }; 61: 62: union { 63: __IO uint32_t SDRAM_Configuration_1; 64: 65: struct { 66: __IO uint32_t BNKSIZE : 4; 67: __IO uint32_t MBW : 2; 68: uint32_t : 2; 69: __IO uint32_t DSZ : 3; 70: uint32_t : 1; 71: __IO uint32_t DDW : 2; 72: } SDRAM_Configuration_1_bits; 73: }; 74: 75: union { 76: __IO uint32_t SDRAM_Configuration_2; 77: 78: struct { 79: __IO uint32_t SREF : 1; 80: __I uint32_t PWDN : 1; 81: __IO uint32_t ISMR : 1; 82: __IO uint32_t IREF : 1; 83: __IO uint32_t IPREC : 1; 84: __IO uint32_t AMTSEL : 1; 85: uint32_t : 2; 86: __IO uint32_t T_PDSR : 10; 87: uint32_t : 2; 88: __I uint32_t SREF_MODE : 1; 89: } SDRAM_Configuration_2_bits; 90: }; 91: 92: union { 93: __IO uint32_t External_Bank; 94: 95: struct { 96: __IO uint32_t BASE : 12; 97: __IO uint32_t EN : 1; 98: } External_Bank_bits; 99: }; 100: 101: __I uint32_t RESERVED1[7]; 102: 103: union { 104: __IO uint32_t Read_Arbitration; 105: 106: struct { 107: __IO uint32_t CH1GW : 4; 108: __IO uint32_t CH2GW : 4; 109: __IO uint32_t CH3GW : 4; 110: __IO uint32_t CH4GW : 4; 111: __IO uint32_t CH5GW : 4; 112: __IO uint32_t CH6GW : 4; 113: __IO uint32_t CH7GW : 4; 114: __IO uint32_t CH8GW : 4; 115: } Read_Arbitration_bits; 116: }; 117: 118: union { 119: __IO uint32_t Flush_Request; 120: 121: struct { 122: __IO uint32_t FLUSHCHN : 3; 123: __IO uint32_t FLUSHCMPLT : 1; 124: } Flush_Request_bits; 125: }; 126: 127: __I uint32_t RESERVED2[1]; 128: 129: union { 130: __IO uint32_t Mobile_SDRAM_Support; 131: 132: struct { 133: __IO uint32_t DS : 2; 134: uint32_t : 2; 135: __IO uint32_t PASR : 3; 136: uint32_t : 1; 137: __IO uint32_t MOBILE : 1; 138: } Mobile_SDRAM_Support_bits; 139: }; 140: 141: __I uint32_t RESERVED3[48]; 142: 143: union { 144: __I uint32_t Controller_Revision; 145: 146: struct { 147: __I uint32_t REV_VER : 8; 148: __I uint32_t MINOR_VER : 8; 149: __I uint32_t MAJOR_VER : 8; 150: } Controller_Revision_bits; 151: }; 152: 153: union { 154: __I uint32_t Controller_Feature; 155: 156: struct { 157: __I uint32_t EBNK : 8; 158: __I uint32_t CHN : 8; 159: __I uint32_t EBI : 1; 160: uint32_t : 7; 161: __I uint32_t CH1_FDEPTH : 1; 162: __I uint32_t CH2_FDEPTH : 1; 163: __I uint32_t CH3_FDEPTH : 1; 164: __I uint32_t CH4_FDEPTH : 1; 165: __I uint32_t CH5_FDEPTH : 1; 166: __I uint32_t CH6_FDEPTH : 1; 167: __I uint32_t CH7_FDEPTH : 1; 168: __I uint32_t CH8_FDEPTH : 1; 169: } Controller_Feature_bits; 170: }; 171: 172: 173: }AG903_SDMC_Type; 174: 175: #define AG903_SDMC ((volatile AG903_SDMC_Type *) AG903_SDMC_BASE) 176: 177: 178: #define AG903_SDMC_SDRAM_Timing_1_TCL_POS 0 179: #define AG903_SDMC_SDRAM_Timing_1_TCL_MSK (0x3UL << AG903_SDMC_SDRAM_Timing_1_TCL_POS) 180: #define AG903_SDMC_SDRAM_Timing_1_TWR_POS 4 181: #define AG903_SDMC_SDRAM_Timing_1_TWR_MSK (0x3UL << AG903_SDMC_SDRAM_Timing_1_TWR_POS) 182: #define AG903_SDMC_SDRAM_Timing_1_TRF_POS 8 183: #define AG903_SDMC_SDRAM_Timing_1_TRF_MSK (0xfUL << AG903_SDMC_SDRAM_Timing_1_TRF_POS) 184: #define AG903_SDMC_SDRAM_Timing_1_TRCD_POS 12 185: #define AG903_SDMC_SDRAM_Timing_1_TRCD_MSK (0x7UL << AG903_SDMC_SDRAM_Timing_1_TRCD_POS) 186: #define AG903_SDMC_SDRAM_Timing_1_TRP_POS 16 187: #define AG903_SDMC_SDRAM_Timing_1_TRP_MSK (0xfUL << AG903_SDMC_SDRAM_Timing_1_TRP_POS) 188: #define AG903_SDMC_SDRAM_Timing_1_TRAS_POS 20 189: #define AG903_SDMC_SDRAM_Timing_1_TRAS_MSK (0xfUL << AG903_SDMC_SDRAM_Timing_1_TRAS_POS) 190: 191: #define AG903_SDMC_SDRAM_Timing_2_REF_INTV_POS 0 192: #define AG903_SDMC_SDRAM_Timing_2_REF_INTV_MSK (0xffffUL << AG903_SDMC_SDRAM_Timing_2_REF_INTV_POS) 193: #define AG903_SDMC_SDRAM_Timing_2_INI_REFT_POS 16 194: #define AG903_SDMC_SDRAM_Timing_2_INI_REFT_MSK (0xfUL << AG903_SDMC_SDRAM_Timing_2_INI_REFT_POS) 195: #define AG903_SDMC_SDRAM_Timing_2_INI_PREC_POS 20 196: #define AG903_SDMC_SDRAM_Timing_2_INI_PREC_MSK (0xfUL << AG903_SDMC_SDRAM_Timing_2_INI_PREC_POS) 197: 198: #define AG903_SDMC_SDRAM_Configuration_1_BNKSIZE_POS 0 199: #define AG903_SDMC_SDRAM_Configuration_1_BNKSIZE_MSK (0xfUL << AG903_SDMC_SDRAM_Configuration_1_BNKSIZE_POS) 200: #define AG903_SDMC_SDRAM_Configuration_1_MBW_POS 4 201: #define AG903_SDMC_SDRAM_Configuration_1_MBW_MSK (0x3UL << AG903_SDMC_SDRAM_Configuration_1_MBW_POS) 202: #define AG903_SDMC_SDRAM_Configuration_1_DSZ_POS 8 203: #define AG903_SDMC_SDRAM_Configuration_1_DSZ_MSK (0x7UL << AG903_SDMC_SDRAM_Configuration_1_DSZ_POS) 204: #define AG903_SDMC_SDRAM_Configuration_1_DDW_POS 12 205: #define AG903_SDMC_SDRAM_Configuration_1_DDW_MSK (0x3UL << AG903_SDMC_SDRAM_Configuration_1_DDW_POS) 206: 207: #define AG903_SDMC_SDRAM_Configuration_2_SREF_POS 0 208: #define AG903_SDMC_SDRAM_Configuration_2_SREF_MSK (0x1UL << AG903_SDMC_SDRAM_Configuration_2_SREF_POS) 209: #define AG903_SDMC_SDRAM_Configuration_2_PWDN_POS 1 210: #define AG903_SDMC_SDRAM_Configuration_2_PWDN_MSK (0x1UL << AG903_SDMC_SDRAM_Configuration_2_PWDN_POS) 211: #define AG903_SDMC_SDRAM_Configuration_2_ISMR_POS 2 212: #define AG903_SDMC_SDRAM_Configuration_2_ISMR_MSK (0x1UL << AG903_SDMC_SDRAM_Configuration_2_ISMR_POS) 213: #define AG903_SDMC_SDRAM_Configuration_2_IREF_POS 3 214: #define AG903_SDMC_SDRAM_Configuration_2_IREF_MSK (0x1UL << AG903_SDMC_SDRAM_Configuration_2_IREF_POS) 215: #define AG903_SDMC_SDRAM_Configuration_2_IPREC_POS 4 216: #define AG903_SDMC_SDRAM_Configuration_2_IPREC_MSK (0x1UL << AG903_SDMC_SDRAM_Configuration_2_IPREC_POS) 217: #define AG903_SDMC_SDRAM_Configuration_2_AMTSEL_POS 5 218: #define AG903_SDMC_SDRAM_Configuration_2_AMTSEL_MSK (0x1UL << AG903_SDMC_SDRAM_Configuration_2_AMTSEL_POS) 219: #define AG903_SDMC_SDRAM_Configuration_2_T_PDSR_POS 8 220: #define AG903_SDMC_SDRAM_Configuration_2_T_PDSR_MSK (0x3ffUL << AG903_SDMC_SDRAM_Configuration_2_T_PDSR_POS) 221: #define AG903_SDMC_SDRAM_Configuration_2_SREF_MODE_POS 20 222: #define AG903_SDMC_SDRAM_Configuration_2_SREF_MODE_MSK (0x1UL << AG903_SDMC_SDRAM_Configuration_2_SREF_MODE_POS) 223: 224: #define AG903_SDMC_External_Bank_BASE_POS 0 225: #define AG903_SDMC_External_Bank_BASE_MSK (0xfffUL << AG903_SDMC_External_Bank_BASE_POS) 226: #define AG903_SDMC_External_Bank_EN_POS 12 227: #define AG903_SDMC_External_Bank_EN_MSK (0x1UL << AG903_SDMC_External_Bank_EN_POS) 228: 229: #define AG903_SDMC_Read_Arbitration_CH1GW_POS 0 230: #define AG903_SDMC_Read_Arbitration_CH1GW_MSK (0xfUL << AG903_SDMC_Read_Arbitration_CH1GW_POS) 231: #define AG903_SDMC_Read_Arbitration_CH2GW_POS 4 232: #define AG903_SDMC_Read_Arbitration_CH2GW_MSK (0xfUL << AG903_SDMC_Read_Arbitration_CH2GW_POS) 233: #define AG903_SDMC_Read_Arbitration_CH3GW_POS 8 234: #define AG903_SDMC_Read_Arbitration_CH3GW_MSK (0xfUL << AG903_SDMC_Read_Arbitration_CH3GW_POS) 235: #define AG903_SDMC_Read_Arbitration_CH4GW_POS 12 236: #define AG903_SDMC_Read_Arbitration_CH4GW_MSK (0xfUL << AG903_SDMC_Read_Arbitration_CH4GW_POS) 237: #define AG903_SDMC_Read_Arbitration_CH5GW_POS 16 238: #define AG903_SDMC_Read_Arbitration_CH5GW_MSK (0xfUL << AG903_SDMC_Read_Arbitration_CH5GW_POS) 239: #define AG903_SDMC_Read_Arbitration_CH6GW_POS 20 240: #define AG903_SDMC_Read_Arbitration_CH6GW_MSK (0xfUL << AG903_SDMC_Read_Arbitration_CH6GW_POS) 241: #define AG903_SDMC_Read_Arbitration_CH7GW_POS 24 242: #define AG903_SDMC_Read_Arbitration_CH7GW_MSK (0xfUL << AG903_SDMC_Read_Arbitration_CH7GW_POS) 243: #define AG903_SDMC_Read_Arbitration_CH8GW_POS 28 244: #define AG903_SDMC_Read_Arbitration_CH8GW_MSK (0xfUL << AG903_SDMC_Read_Arbitration_CH8GW_POS) 245: 246: #define AG903_SDMC_Flush_Request_FLUSHCHN_POS 0 247: #define AG903_SDMC_Flush_Request_FLUSHCHN_MSK (0x7UL << AG903_SDMC_Flush_Request_FLUSHCHN_POS) 248: #define AG903_SDMC_Flush_Request_FLUSHCMPLT_POS 3 249: #define AG903_SDMC_Flush_Request_FLUSHCMPLT_MSK (0x1UL << AG903_SDMC_Flush_Request_FLUSHCMPLT_POS) 250: 251: #define AG903_SDMC_Mobile_SDRAM_Support_DS_POS 0 252: #define AG903_SDMC_Mobile_SDRAM_Support_DS_MSK (0x3UL << AG903_SDMC_Mobile_SDRAM_Support_DS_POS) 253: #define AG903_SDMC_Mobile_SDRAM_Support_PASR_POS 4 254: #define AG903_SDMC_Mobile_SDRAM_Support_PASR_MSK (0x7UL << AG903_SDMC_Mobile_SDRAM_Support_PASR_POS) 255: #define AG903_SDMC_Mobile_SDRAM_Support_MOBILE_POS 8 256: #define AG903_SDMC_Mobile_SDRAM_Support_MOBILE_MSK (0x1UL << AG903_SDMC_Mobile_SDRAM_Support_MOBILE_POS) 257: 258: #define AG903_SDMC_Controller_Revision_REV_VER_POS 0 259: #define AG903_SDMC_Controller_Revision_REV_VER_MSK (0xffUL << AG903_SDMC_Controller_Revision_REV_VER_POS) 260: #define AG903_SDMC_Controller_Revision_MINOR_VER_POS 8 261: #define AG903_SDMC_Controller_Revision_MINOR_VER_MSK (0xffUL << AG903_SDMC_Controller_Revision_MINOR_VER_POS) 262: #define AG903_SDMC_Controller_Revision_MAJOR_VER_POS 16 263: #define AG903_SDMC_Controller_Revision_MAJOR_VER_MSK (0xffUL << AG903_SDMC_Controller_Revision_MAJOR_VER_POS) 264: 265: #define AG903_SDMC_Controller_Feature_EBNK_POS 0 266: #define AG903_SDMC_Controller_Feature_EBNK_MSK (0xffUL << AG903_SDMC_Controller_Feature_EBNK_POS) 267: #define AG903_SDMC_Controller_Feature_CHN_POS 8 268: #define AG903_SDMC_Controller_Feature_CHN_MSK (0xffUL << AG903_SDMC_Controller_Feature_CHN_POS) 269: #define AG903_SDMC_Controller_Feature_EBI_POS 16 270: #define AG903_SDMC_Controller_Feature_EBI_MSK (0x1UL << AG903_SDMC_Controller_Feature_EBI_POS) 271: #define AG903_SDMC_Controller_Feature_CH1_FDEPTH_POS 24 272: #define AG903_SDMC_Controller_Feature_CH1_FDEPTH_MSK (0x1UL << AG903_SDMC_Controller_Feature_CH1_FDEPTH_POS) 273: #define AG903_SDMC_Controller_Feature_CH2_FDEPTH_POS 25 274: #define AG903_SDMC_Controller_Feature_CH2_FDEPTH_MSK (0x1UL << AG903_SDMC_Controller_Feature_CH2_FDEPTH_POS) 275: #define AG903_SDMC_Controller_Feature_CH3_FDEPTH_POS 26 276: #define AG903_SDMC_Controller_Feature_CH3_FDEPTH_MSK (0x1UL << AG903_SDMC_Controller_Feature_CH3_FDEPTH_POS) 277: #define AG903_SDMC_Controller_Feature_CH4_FDEPTH_POS 27 278: #define AG903_SDMC_Controller_Feature_CH4_FDEPTH_MSK (0x1UL << AG903_SDMC_Controller_Feature_CH4_FDEPTH_POS) 279: #define AG903_SDMC_Controller_Feature_CH5_FDEPTH_POS 28 280: #define AG903_SDMC_Controller_Feature_CH5_FDEPTH_MSK (0x1UL << AG903_SDMC_Controller_Feature_CH5_FDEPTH_POS) 281: #define AG903_SDMC_Controller_Feature_CH6_FDEPTH_POS 29 282: #define AG903_SDMC_Controller_Feature_CH6_FDEPTH_MSK (0x1UL << AG903_SDMC_Controller_Feature_CH6_FDEPTH_POS) 283: #define AG903_SDMC_Controller_Feature_CH7_FDEPTH_POS 30 284: #define AG903_SDMC_Controller_Feature_CH7_FDEPTH_MSK (0x1UL << AG903_SDMC_Controller_Feature_CH7_FDEPTH_POS) 285: #define AG903_SDMC_Controller_Feature_CH8_FDEPTH_POS 31 286: #define AG903_SDMC_Controller_Feature_CH8_FDEPTH_MSK (0x1UL << AG903_SDMC_Controller_Feature_CH8_FDEPTH_POS) 287: 288: #endif 289:
名前 
説明 
SDMC Base Address 
SDMCController_Feature CH1_FDEPTH-bit mask 
SDMCController_Feature CH1_FDEPTH-bit position 
SDMCController_Feature CH2_FDEPTH-bit mask 
SDMCController_Feature CH2_FDEPTH-bit position 
SDMCController_Feature CH3_FDEPTH-bit mask 
SDMCController_Feature CH3_FDEPTH-bit position 
SDMCController_Feature CH4_FDEPTH-bit mask 
SDMCController_Feature CH4_FDEPTH-bit position 
SDMCController_Feature CH5_FDEPTH-bit mask 
SDMCController_Feature CH5_FDEPTH-bit position 
SDMCController_Feature CH6_FDEPTH-bit mask 
SDMCController_Feature CH6_FDEPTH-bit position 
SDMCController_Feature CH7_FDEPTH-bit mask 
SDMCController_Feature CH7_FDEPTH-bit position 
SDMCController_Feature CH8_FDEPTH-bit mask 
SDMCController_Feature CH8_FDEPTH-bit position 
SDMCController_Feature CHN-bit mask 
SDMCController_Feature CHN-bit position 
SDMCController_Feature EBI-bit position 
SDMCController_Feature EBNK-bit mask 
SDMCController_Feature EBNK-bit position 
SDMCController_Revision MAJOR_VER-bit mask 
SDMCController_Revision MAJOR_VER-bit position 
SDMCController_Revision MINOR_VER-bit mask 
SDMCController_Revision MINOR_VER-bit position 
SDMCController_Revision REV_VER-bit mask 
SDMCController_Revision REV_VER-bit position 
SDMCExternal_Bank BASE-bit mask 
SDMCExternal_Bank BASE-bit position 
SDMCExternal_Bank EN-bit mask 
SDMCExternal_Bank EN-bit position 
SDMCFlush_Request FLUSHCHN-bit mask 
SDMCFlush_Request FLUSHCHN-bit position 
SDMCFlush_Request FLUSHCMPLT-bit mask 
SDMCFlush_Request FLUSHCMPLT-bit position 
SDMCMobile_SDRAM_Support DS-bit position 
SDMCMobile_SDRAM_Support MOBILE-bit mask 
SDMCMobile_SDRAM_Support MOBILE-bit position 
SDMCMobile_SDRAM_Support PASR-bit mask 
SDMCMobile_SDRAM_Support PASR-bit position 
SDMCRead_Arbitration CH1GW-bit mask 
SDMCRead_Arbitration CH1GW-bit position 
SDMCRead_Arbitration CH2GW-bit mask 
SDMCRead_Arbitration CH2GW-bit position 
SDMCRead_Arbitration CH3GW-bit mask 
SDMCRead_Arbitration CH3GW-bit position 
SDMCRead_Arbitration CH4GW-bit mask 
SDMCRead_Arbitration CH4GW-bit position 
SDMCRead_Arbitration CH5GW-bit mask 
SDMCRead_Arbitration CH5GW-bit position 
SDMCRead_Arbitration CH6GW-bit mask 
SDMCRead_Arbitration CH6GW-bit position 
SDMCRead_Arbitration CH7GW-bit mask 
SDMCRead_Arbitration CH7GW-bit position 
SDMCRead_Arbitration CH8GW-bit mask 
SDMCRead_Arbitration CH8GW-bit position 
SDMCSDRAM_Configuration_1 BNKSIZE-bit mask 
SDMCSDRAM_Configuration_1 BNKSIZE-bit position 
SDMCSDRAM_Configuration_1 DDW-bit position 
SDMCSDRAM_Configuration_1 DSZ-bit position 
SDMCSDRAM_Configuration_1 MBW-bit position 
SDMCSDRAM_Configuration_2 AMTSEL-bit mask 
SDMCSDRAM_Configuration_2 AMTSEL-bit position 
SDMCSDRAM_Configuration_2 IPREC-bit mask 
SDMCSDRAM_Configuration_2 IPREC-bit position 
SDMCSDRAM_Configuration_2 IREF-bit mask 
SDMCSDRAM_Configuration_2 IREF-bit position 
SDMCSDRAM_Configuration_2 ISMR-bit mask 
SDMCSDRAM_Configuration_2 ISMR-bit position 
SDMCSDRAM_Configuration_2 PWDN-bit mask 
SDMCSDRAM_Configuration_2 PWDN-bit position 
SDMCSDRAM_Configuration_2 SREF_MODE-bit mask 
SDMCSDRAM_Configuration_2 SREF_MODE-bit position 
SDMCSDRAM_Configuration_2 SREF-bit mask 
SDMCSDRAM_Configuration_2 SREF-bit position 
SDMCSDRAM_Configuration_2 T_PDSR-bit mask 
SDMCSDRAM_Configuration_2 T_PDSR-bit position 
SDMCSDRAM_Timing_1 TCL-bit mask 
SDMCSDRAM_Timing_1 TCL-bit position 
SDMCSDRAM_Timing_1 TRAS-bit mask 
SDMCSDRAM_Timing_1 TRAS-bit position 
SDMCSDRAM_Timing_1 TRCD-bit mask 
SDMCSDRAM_Timing_1 TRCD-bit position 
SDMCSDRAM_Timing_1 TRF-bit mask 
SDMCSDRAM_Timing_1 TRF-bit position 
SDMCSDRAM_Timing_1 TRP-bit mask 
SDMCSDRAM_Timing_1 TRP-bit position 
SDMCSDRAM_Timing_1 TWR-bit mask 
SDMCSDRAM_Timing_1 TWR-bit position 
SDMCSDRAM_Timing_2 INI_PREC-bit mask 
SDMCSDRAM_Timing_2 INI_PREC-bit position 
SDMCSDRAM_Timing_2 INI_REFT-bit mask 
SDMCSDRAM_Timing_2 INI_REFT-bit position 
SDMCSDRAM_Timing_2 REF_INTV-bit mask 
SDMCSDRAM_Timing_2 REF_INTV-bit position 
名前 
説明 
SDMC Type 
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