AG903ライブラリリファレンス
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AG903_sdcreg.h
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1: 8: 9: 13: 14:
#ifndef
_AG903_SDC_REGMAP_H_ 15:
#define
_AG903_SDC_REGMAP_H_ 16: 17: 18:
#include
"AG903_regmap.h" 19: 20:
#ifndef
__I
21: 22:
#define
__I
volatile
const
23:
#endif
24:
#ifndef
__O
25: 26:
#define
__O
volatile
27:
#endif
28:
#ifndef
__IO
29: 30:
#define
__IO
volatile
31:
#endif
32: 33: 34:
typedef
struct
{ 35: 36:
union
{ 37:
__IO
uint32_t SDMA_System_Address; 38:
__IO
uint32_t Argument_2; 39: }; 40: 41:
union
{ 42:
__IO
uint16_t Block_Size; 43: 44:
struct
{ 45:
__IO
uint16_t Transfer_Block_Size : 12; 46:
__IO
uint16_t Host_SDMA_Buffer_Boundary : 3; 47: } Block_Size_bits; 48: }; 49: 50:
union
{ 51:
__IO
uint16_t Block_Count; 52: }; 53: 54:
union
{ 55:
__IO
uint32_t Argument_1; 56: }; 57: 58:
union
{ 59:
__IO
uint16_t Transfer_Mode; 60: 61:
struct
{ 62:
__IO
uint16_t DMA_Enable : 1; 63:
__IO
uint16_t Block_Count_Enable : 1; 64:
__IO
uint16_t Auto_CMD_Enable : 2; 65:
__IO
uint16_t Data_Transfer_Direction_Select : 1; 66:
__IO
uint16_t Multi_Single_Block_Select : 1; 67: } Transfer_Mode_bits; 68: }; 69: 70:
union
{ 71:
__IO
uint16_t Command; 72: 73:
struct
{ 74:
__IO
uint16_t Response_Type_Select : 2; 75: uint16_t : 1; 76:
__IO
uint16_t Command_CRC_Check_Enable : 1; 77:
__IO
uint16_t Command_Index_Check_Enable : 1; 78:
__IO
uint16_t Data_Present_Select : 1; 79:
__IO
uint16_t Command_Type : 2; 80:
__IO
uint16_t Command_Index : 6; 81: } Command_bits; 82: }; 83: 84:
union
{ 85:
__I
uint32_t Response[4]; 86: }; 87: 88:
union
{ 89:
__IO
uint32_t Buffer_Data_Port; 90: }; 91: 92:
union
{ 93:
__I
uint32_t Present_State; 94: 95:
struct
{ 96:
__I
uint32_t Command_Inhibit_CMD : 1; 97:
__I
uint32_t Command_Inhibit_LINE : 1; 98:
__I
uint32_t DAT_Line_Active : 1; 99: uint32_t : 5; 100:
__I
uint32_t Write_Transfer_Active : 1; 101:
__I
uint32_t Read_Transfer_Active : 1; 102:
__I
uint32_t Buffer_Write_Enable : 1; 103:
__I
uint32_t Buffer_Read_Enable : 1; 104: uint32_t : 4; 105:
__I
uint32_t Card_Inserted : 1; 106:
__I
uint32_t Card_State_Stable : 1; 107:
__I
uint32_t Card_Detect_Pin_Level : 1; 108:
__I
uint32_t Write_Protect_Switch_Pin_Level : 1; 109:
__I
uint32_t DAT_Line_Signal_Level : 4; 110:
__I
uint32_t CMD_Line_Signal_Level : 1; 111: } Present_State_bits; 112: }; 113: 114:
union
{ 115:
__IO
uint8_t Host_Control_1; 116: 117:
struct
{ 118:
__IO
uint8_t LED_Control : 1; 119:
__IO
uint8_t Data_Transfer_Width : 1; 120:
__IO
uint8_t High_Speed_Enable : 1; 121:
__IO
uint8_t DMA_Select : 2; 122:
__IO
uint8_t Extended_Sata_Transfer_Width : 1; 123:
__IO
uint8_t Card_Detect_Test_Level : 1; 124:
__IO
uint8_t Card_Detect_Signal_Selection : 1; 125: } Host_Control_1_bits; 126: }; 127: 128:
union
{ 129:
__IO
uint8_t Power_Control_Register; 130: 131:
struct
{ 132:
__IO
uint8_t SD_Bus_Power : 1; 133:
__IO
uint8_t SD_Bus_Voltage_Select : 3; 134: } Power_Control_Register_bits; 135: }; 136: 137:
union
{ 138:
__IO
uint8_t Block_Gap_Control; 139: 140:
struct
{ 141:
__IO
uint8_t Stop_At_Block_Gap_Request : 1; 142:
__IO
uint8_t Continue_Request : 1; 143:
__IO
uint8_t Read_Wait_Control : 1; 144:
__IO
uint8_t Interrupt_At_Block_Gap : 1; 145: } Block_Gap_Control_bits; 146: }; 147: 148:
__I
uint8_t RESERVED1[1]; 149: 150:
union
{ 151:
__IO
uint16_t Clock_control; 152: 153:
struct
{ 154:
__IO
uint16_t Internal_Clock_Enable : 1; 155:
__I
uint16_t Internal_Clock_Stable : 1; 156:
__IO
uint16_t SD_Clock_Enable : 1; 157: uint16_t : 2; 158:
__I
uint16_t Clock_Generator_Select : 1; 159:
__IO
uint16_t Upper_Bits_of_SDCLK_Frequency_Select : 2; 160:
__IO
uint16_t SDCLK_Frequency_Select : 8; 161: } Clock_control_bits; 162: }; 163: 164:
union
{ 165:
__IO
uint8_t Timeout_Control; 166: 167:
struct
{ 168:
__IO
uint8_t Data_Timeout_Counter_Value : 4; 169: } Timeout_Control_bits; 170: }; 171: 172:
union
{ 173:
__IO
uint8_t Software_Reset; 174: 175:
struct
{ 176:
__IO
uint8_t Software_Reset_For_All : 1; 177:
__IO
uint8_t Software_Reset_For_CMD_Line : 1; 178:
__IO
uint8_t Software_Reset_For_DAT_Line : 1; 179: } Software_Reset_bits; 180: }; 181: 182:
union
{ 183:
__IO
uint16_t Normal_Interrupt_Status; 184: 185:
struct
{ 186:
__IO
uint16_t Command_Complete : 1; 187:
__IO
uint16_t Transfer_Complete : 1; 188:
__IO
uint16_t Block_Gap_Event : 1; 189:
__IO
uint16_t DMA_Interrupt : 1; 190:
__IO
uint16_t Butter_Write_Ready : 1; 191:
__IO
uint16_t Buffer_Read_Ready : 1; 192:
__IO
uint16_t Card_Insertion : 1; 193:
__IO
uint16_t Card_Removal : 1; 194:
__I
uint16_t Card_Interrupt : 1; 195:
__I
uint16_t INT_A : 1; 196:
__I
uint16_t INT_B : 1; 197:
__I
uint16_t INT_C : 1; 198:
__I
uint16_t ReTuning_Event : 1; 199: uint16_t : 2; 200:
__I
uint16_t Error_Interrupt : 1; 201: } Normal_Interrupt_Status_bits; 202: }; 203: 204:
union
{ 205:
__IO
uint16_t Error_Interrupt_Status; 206: 207:
struct
{ 208:
__IO
uint16_t Command_Timeout_Error : 1; 209:
__IO
uint16_t Command_CRC_Error : 1; 210:
__IO
uint16_t Command_End_Bit_Error : 1; 211:
__IO
uint16_t Command_Index_Error : 1; 212:
__IO
uint16_t Data_Timeout_Error : 1; 213:
__IO
uint16_t Data_CRC_Error : 1; 214:
__IO
uint16_t Data_End_Bit_Error : 1; 215:
__IO
uint16_t Current_Limit_Error : 1; 216:
__IO
uint16_t Auto_CMD_Error : 1; 217:
__IO
uint16_t ADMA_Error : 1; 218:
__IO
uint16_t Tuning_Error : 1; 219: } Error_Interrupt_Status_bits; 220: }; 221: 222:
union
{ 223:
__IO
uint16_t Normal_Interrupt_Status_Enable; 224: 225:
struct
{ 226:
__IO
uint16_t Command_Complete_Status_Enable : 1; 227:
__IO
uint16_t Transfer_Complete_Status_Enable : 1; 228:
__IO
uint16_t Block_Gap_Event_Status_Enable : 1; 229:
__IO
uint16_t DMA_Interrupt_Status_Enable : 1; 230:
__IO
uint16_t Buffer_Write_Ready_Status_Enable : 1; 231:
__IO
uint16_t Buffer_Read_Ready_Status_Enable : 1; 232:
__IO
uint16_t Card_Insertion_Status_Enable : 1; 233:
__IO
uint16_t Card_Removal_Status_Enable : 1; 234:
__IO
uint16_t Card_Interrupt_Status_Enable : 1; 235:
__IO
uint16_t INT_A_Status_Enable : 1; 236:
__IO
uint16_t INT_B_Status_Enable : 1; 237:
__IO
uint16_t INT_C_Status_Enable : 1; 238:
__IO
uint16_t ReTuning_Event_Status_Enable : 1; 239: } Normal_Interrupt_Status_Enable_bits; 240: }; 241: 242:
union
{ 243:
__IO
uint16_t Error_Interrupt_Status_Enable; 244: 245:
struct
{ 246:
__IO
uint16_t Command_Timeout_Error_Status_Enable : 1; 247:
__IO
uint16_t Command_CRC_Error_Status_Enable : 1; 248:
__IO
uint16_t Command_End_Bit_Error_Status_Enable : 1; 249:
__IO
uint16_t Command_Index_Error_Status_Enable : 1; 250:
__IO
uint16_t Data_Timeout_Error_Status_Enable : 1; 251:
__IO
uint16_t Data_CRC_Error_Status_Enable : 1; 252:
__IO
uint16_t Data_End_Bit_Error_Status_Enable : 1; 253:
__IO
uint16_t Current_Limit_Error_Status_Enable : 1; 254:
__IO
uint16_t Auto_CMD_Error_Status_Enable : 1; 255:
__IO
uint16_t ADMA_Error_Status_Enable : 1; 256:
__IO
uint16_t Tuning_Error_Status_Enable : 1; 257: } Error_Interrupt_Status_Enable_bits; 258: }; 259: 260:
union
{ 261:
__IO
uint16_t Normal_Interrupt_Signal_Enable; 262: 263:
struct
{ 264:
__IO
uint16_t Command_Complete_Signal_Enable : 1; 265:
__IO
uint16_t Transfer_Complete_Signal_Enable : 1; 266:
__IO
uint16_t Block_Gap_Event_Signal_Enable : 1; 267:
__IO
uint16_t DMA_Interrupt_Signal_Enable : 1; 268:
__IO
uint16_t Buffer_Write_Ready_Signal_Enable : 1; 269:
__IO
uint16_t Buffer_Read_Ready_Signal_Enable : 1; 270:
__IO
uint16_t Card_Insertion_Signal_Enable : 1; 271:
__IO
uint16_t Card_Removal_Signal_Enable : 1; 272:
__IO
uint16_t Card_Interrupt_Signal_Enable : 1; 273:
__IO
uint16_t INT_A_Signal_Enable : 1; 274:
__IO
uint16_t INT_B_Signal_Enable : 1; 275:
__IO
uint16_t INT_C_Signal_Enable : 1; 276:
__IO
uint16_t ReTuning_Event_Signal_Enable : 1; 277: } Normal_Interrupt_Signal_Enable_bits; 278: }; 279: 280:
union
{ 281:
__IO
uint16_t Error_Interrupt_Signal_Enable; 282: 283:
struct
{ 284:
__IO
uint16_t Command_Timeout_Error_Signal_Enable : 1; 285:
__IO
uint16_t Command_CRC_Error_Signal_Enable : 1; 286:
__IO
uint16_t Command_End_Bit_Error_Signal_Enable : 1; 287:
__IO
uint16_t Command_Index_Error_Signal_Enable : 1; 288:
__IO
uint16_t Data_Timeout_Error_Signal_Enable : 1; 289:
__IO
uint16_t Data_CRC_Error_Signal_Enable : 1; 290:
__IO
uint16_t Data_End_Bit_Error_Signal_Enable : 1; 291:
__IO
uint16_t Current_Limit_Error_Signal_Enable : 1; 292:
__IO
uint16_t Auto_CMD_Error_Signal_Enable : 1; 293:
__IO
uint16_t ADMA_Error_Signal_Enable : 1; 294:
__IO
uint16_t Tuning_Error_Signal_Enable : 1; 295: } Error_Interrupt_Signal_Enable_bits; 296: }; 297: 298:
union
{ 299:
__I
uint16_t Auto_CMD_Error_Status; 300: 301:
struct
{ 302:
__I
uint16_t Auto_CMD12_Npt_Executed : 1; 303:
__I
uint16_t Auto_CMD_Timeout_Error : 1; 304:
__I
uint16_t Auto_CMD_CRC_Error : 1; 305:
__I
uint16_t Auto_CMD_End_Bit_Error : 1; 306:
__I
uint16_t Auto_CMD_Index_Error : 1; 307: uint16_t : 2; 308:
__I
uint16_t Command_Not_Issued_By_Auto_CMD12_Error : 1; 309: } Auto_CMD_Error_Status_bits; 310: }; 311: 312:
union
{ 313:
__IO
uint16_t Host_Control_2; 314: 315:
struct
{ 316:
__IO
uint16_t UHS_Mode_Select : 3; 317:
__IO
uint16_t V1p8_Signaling_Enable : 1; 318:
__IO
uint16_t Driver_Strength_Select : 2; 319:
__IO
uint16_t Execute_Tuning : 1; 320:
__IO
uint16_t Sampling_Clock_Select : 1; 321: uint16_t : 6; 322:
__IO
uint16_t Asynchronous_Interrupt_Enable : 1; 323:
__IO
uint16_t Preset_Value_Enable : 1; 324: } Host_Control_2_bits; 325: }; 326: 327:
union
{ 328:
__I
uint64_t Capabilities; 329: 330:
struct
{ 331:
__I
uint64_t Timeout_Clock_Frequency : 6; 332: uint64_t : 1; 333:
__I
uint64_t Timeout_Clock_Count : 1; 334:
__I
uint64_t Base_Clock_Frequency_For_SD_Clock : 8; 335:
__I
uint64_t Max_Block_Length : 2; 336:
__I
uint64_t B8_Support_for_Embedded_Device : 1; 337:
__I
uint64_t ADMA2_Support : 1; 338:
__I
uint64_t ADMA1_Support : 1; 339:
__I
uint64_t High_Speed_Support : 1; 340:
__I
uint64_t SDMA_Support : 1; 341:
__I
uint64_t Suspend_Resume_Support : 1; 342:
__I
uint64_t Voltage_Support_3p3V : 1; 343:
__I
uint64_t Voltage_Support_3p0V : 1; 344:
__I
uint64_t Voltage_Support_1p8V : 1; 345: uint64_t : 1; 346:
__I
uint64_t B64_System_Bus_Support : 1; 347:
__I
uint64_t Asynchronous_Interrupt_Support : 1; 348:
__I
uint64_t Slot_Type : 2; 349:
__I
uint64_t SDR50_Support : 1; 350:
__I
uint64_t SDR104_Support : 1; 351:
__I
uint64_t DDR50_Support : 1; 352: uint64_t : 1; 353:
__I
uint64_t Driver_Type_A_Support : 1; 354:
__I
uint64_t Driver_Type_C_Support : 1; 355:
__I
uint64_t Driver_Type_D_Support : 1; 356: uint64_t : 1; 357:
__I
uint64_t Timer_Count_for_ReTuning : 4; 358: uint64_t : 1; 359:
__I
uint64_t User_Tuning_for_SDR50 : 1; 360:
__I
uint64_t ReTuning_Modes : 2; 361:
__I
uint64_t Clock_Multiplier : 8; 362: } Capabilities_bits; 363: }; 364: 365:
union
{ 366:
__I
uint64_t Maximum_Current_Capabilities; 367: 368:
struct
{ 369:
__I
uint64_t Maximum_Current_for_3p3V : 8; 370:
__I
uint64_t Maximum_Current_for_3p0V : 8; 371:
__I
uint64_t Maximum_Current_for_1p8V : 8; 372: } Maximum_Current_Capabilities_bits; 373: }; 374: 375:
union
{ 376:
__O
uint16_t Force_Event_for_Auto_CMD_Error_Status; 377: 378:
struct
{ 379:
__O
uint16_t Force_Event_for_Auto_CMD12_Not_Executed : 1; 380:
__O
uint16_t Force_Event_for_Auto_CMD_Timeout_Error : 1; 381:
__O
uint16_t Force_Event_for_Auto_CMD_CRC_Error : 1; 382:
__O
uint16_t Force_Event_for_Auto_CMD_End_Bit_Error : 1; 383:
__O
uint16_t Force_Event_for_Auto_CMD_Index_Error : 1; 384: uint16_t : 2; 385:
__O
uint16_t Force_Event_for_Command_Not_Issued_By_Auto_CMD12_Error : 1; 386: } Force_Event_for_Auto_CMD_Error_Status_bits; 387: }; 388: 389:
union
{ 390:
__O
uint16_t Force_Event_for_Error_Interrupt_Status; 391: 392:
struct
{ 393:
__O
uint16_t Force_Event_for_Command_Timeout_Error : 1; 394:
__O
uint16_t Force_Event_for_Command_CRC_Error : 1; 395:
__O
uint16_t Force_Event_for_Command_End_Bit_Error : 1; 396:
__O
uint16_t Force_Event_for_Command_Index_Error : 1; 397:
__O
uint16_t Force_Event_for_Data_Timeout_Error : 1; 398:
__O
uint16_t Force_Event_for_Data_CRC_Error : 1; 399:
__O
uint16_t Force_Event_for_Data_End_Bit_Error : 1; 400:
__O
uint16_t Force_Event_for_Current_Limit_Error : 1; 401:
__O
uint16_t Force_Event_for_Auto_CMD_Error : 1; 402:
__O
uint16_t Force_Event_for_ADMA_Error : 1; 403: uint16_t : 2; 404:
__O
uint16_t Force_Event_for_AHB_Response_Error : 1; 405: } Force_Event_for_Error_Interrupt_Status_bits; 406: }; 407: 408:
union
{ 409:
__I
uint8_t ADMA_Error_Status; 410: 411:
struct
{ 412:
__I
uint8_t ADMA_Error_State : 2; 413:
__I
uint8_t ADMA_Length_Mismatch_Error : 1; 414: } ADMA_Error_Status_bits; 415: }; 416: 417:
__I
uint8_t RESERVED2[3]; 418: 419:
union
{ 420:
__IO
uint64_t ADMA_System_Address; 421: 422:
struct
{ 423:
__IO
uint64_t ADMA_System_Address : 32; 424: } ADMA_System_Address_bits; 425: }; 426: 427:
union
{ 428:
__I
uint16_t Preset_Value_INIT; 429: 430:
struct
{ 431:
__I
uint16_t SDCLK_Frequency_Select_Value : 10; 432:
__I
uint16_t Clock_Generator_Select_Value : 1; 433: uint16_t : 3; 434:
__I
uint16_t Driver_Strength_Select_Value : 2; 435: } Preset_Value_INIT_bits; 436: }; 437: 438:
union
{ 439:
__I
uint16_t Preset_Value_DS; 440: 441:
struct
{ 442:
__I
uint16_t SDCLK_Frequency_Select_Value : 10; 443:
__I
uint16_t Clock_Generator_Select_Value : 1; 444: uint16_t : 3; 445:
__I
uint16_t Driver_Strength_Select_Value : 2; 446: } Preset_Value_DS_bits; 447: }; 448: 449:
union
{ 450:
__I
uint16_t Preset_Value_HS; 451: 452:
struct
{ 453:
__I
uint16_t SDCLK_Frequency_Select_Value : 10; 454:
__I
uint16_t Clock_Generator_Select_Value : 1; 455: uint16_t : 3; 456:
__I
uint16_t Driver_Strength_Select_Value : 2; 457: } Preset_Value_HS_bits; 458: }; 459: 460:
union
{ 461:
__I
uint16_t Preset_Value_SDR12; 462: 463:
struct
{ 464:
__I
uint16_t SDCLK_Frequency_Select_Value : 10; 465:
__I
uint16_t Clock_Generator_Select_Value : 1; 466: uint16_t : 3; 467:
__I
uint16_t Driver_Strength_Select_Value : 2; 468: } Preset_Value_SDR12_bits; 469: }; 470: 471:
union
{ 472:
__I
uint16_t Preset_Value_SDR25; 473: 474:
struct
{ 475:
__I
uint16_t SDCLK_Frequency_Select_Value : 10; 476:
__I
uint16_t Clock_Generator_Select_Value : 1; 477: uint16_t : 3; 478:
__I
uint16_t Driver_Strength_Select_Value : 2; 479: } Preset_Value_SDR25_bits; 480: }; 481: 482:
union
{ 483:
__I
uint16_t Preset_Value_SDR50; 484: 485:
struct
{ 486:
__I
uint16_t SDCLK_Frequency_Select_Value : 10; 487:
__I
uint16_t Clock_Generator_Select_Value : 1; 488: uint16_t : 3; 489:
__I
uint16_t Driver_Strength_Select_Value : 2; 490: } Preset_Value_SDR50_bits; 491: }; 492: 493:
union
{ 494:
__I
uint16_t Preset_Value_SDR104; 495: 496:
struct
{ 497:
__I
uint16_t SDCLK_Frequency_Select_Value : 10; 498:
__I
uint16_t Clock_Generator_Select_Value : 1; 499: uint16_t : 3; 500:
__I
uint16_t Driver_Strength_Select_Value : 2; 501: } Preset_Value_SDR104_bits; 502: }; 503: 504:
union
{ 505:
__I
uint16_t Preset_Value_DDR50; 506: 507:
struct
{ 508:
__I
uint16_t SDCLK_Frequency_Select_Value : 10; 509:
__I
uint16_t Clock_Generator_Select_Value : 1; 510: uint16_t : 3; 511:
__I
uint16_t Driver_Strength_Select_Value : 2; 512: } Preset_Value_DDR50_bits; 513: }; 514: 515:
__I
uint32_t RESERVED3[35]; 516:
__I
uint8_t RESERVED4[2]; 517: 518:
union
{ 519:
__I
uint16_t Host_Controller_Version; 520: 521:
struct
{ 522:
__I
uint16_t Specification_Version_Number : 8; 523:
__I
uint16_t Vendor_Version_Number : 8; 524: } Host_Controller_Version_bits; 525: }; 526: 527:
union
{ 528:
__IO
uint32_t Vendor_defined_0; 529: 530:
struct
{ 531:
__IO
uint32_t p_lat_en : 1; 532: uint32_t : 7; 533:
__IO
uint32_t p_lat_off : 6; 534: uint32_t : 2; 535:
__IO
uint32_t int_edge_sel : 1; 536: uint32_t : 7; 537:
__IO
uint32_t NCRC : 4; 538: } Vendor_defined_0_bits; 539: }; 540: 541:
union
{ 542:
__IO
uint32_t Vendor_defined_1; 543: 544:
struct
{ 545:
__IO
uint32_t mmc_boot : 2; 546:
__IO
uint32_t mmc_boot_ack_en : 1; 547: uint32_t : 5; 548:
__IO
uint32_t NCR : 4; 549: uint32_t : 4; 550:
__IO
uint32_t NSB : 3; 551: uint32_t : 5; 552:
__IO
uint32_t cmd_conflict_en : 1; 553: } Vendor_defined_1_bits; 554: }; 555: 556:
union
{ 557:
__IO
uint32_t Vendor_defined_2; 558: 559:
struct
{ 560:
__IO
uint32_t clk_ctrl_sw_rst : 1; 561: } Vendor_defined_2_bits; 562: }; 563: 564:
union
{ 565:
__IO
uint32_t Vendor_defined_3; 566: 567:
struct
{ 568:
__IO
uint32_t tuning_success_thres : 5; 569: uint32_t : 3; 570:
__IO
uint32_t crc16_error_thres : 5; 571: uint32_t : 3; 572:
__IO
uint32_t sd_delay_val : 5; 573: uint32_t : 3; 574:
__IO
uint32_t sd_delay_sel_bound : 5; 575: } Vendor_defined_3_bits; 576: }; 577: 578:
union
{ 579:
__I
uint32_t Vendor_defined_4; 580: }; 581: 582:
union
{ 583:
__IO
uint32_t Vendor_defined_5; 584: 585:
struct
{ 586:
__IO
uint32_t db_timeout : 4; 587: } Vendor_defined_5_bits; 588: }; 589: 590:
union
{ 591:
__IO
uint32_t Vendor_defined_6; 592: 593:
struct
{ 594:
__IO
uint32_t hburst_incr : 1; 595: } Vendor_defined_6_bits; 596: }; 597: 598:
union
{ 599:
__IO
uint32_t Vendor_defined_7; 600: 601:
struct
{ 602:
__IO
uint32_t ahb_resp_err_sts : 1; 603: } Vendor_defined_7_bits; 604: }; 605: 606:
union
{ 607:
__IO
uint32_t Vendor_defined_8; 608: 609:
struct
{ 610:
__IO
uint32_t ahb_resp_err_sts_en : 1; 611: } Vendor_defined_8_bits; 612: }; 613: 614:
union
{ 615:
__IO
uint32_t Vendor_defined_9; 616: 617:
struct
{ 618:
__IO
uint32_t ahb_resp_err_sts : 1; 619: } Vendor_defined_9_bits; 620: }; 621: 622:
union
{ 623:
__IO
uint32_t DMA_handshake_enable; 624: 625:
struct
{ 626:
__IO
uint32_t dma_hsk_en : 1; 627: } DMA_handshake_enable_bits; 628: }; 629: 630:
__I
uint32_t RESERVED5[19]; 631: 632:
union
{ 633:
__I
uint32_t Hardware_attributes; 634: 635:
struct
{ 636:
__I
uint32_t hw_config : 9; 637: } Hardware_attributes_bits; 638: }; 639: 640:
union
{ 641:
__I
uint32_t IP_revision; 642: }; 643: 644: 645: }
AG903_SDC_Type
; 646: 647:
#define
AG903_SDC
((
volatile
AG903_SDC_Type
*)
AG903_SDC_BASE
) 648: 649: 650:
#define
AG903_SDC_SDMA_System_Address_SDMA_System_Address_POS
0 651:
#define
AG903_SDC_SDMA_System_Address_SDMA_System_Address_MSK
(0xffffffffUL <<
AG903_SDC_SDMA_System_Address_SDMA_System_Address_POS
) 652: 653:
#define
AG903_SDC_Argument_2_Argument_2_POS
0 654:
#define
AG903_SDC_Argument_2_Argument_2_MSK
(0xffffffffUL <<
AG903_SDC_Argument_2_Argument_2_POS
) 655: 656:
#define
AG903_SDC_Block_Size_Transfer_Block_Size_POS
0 657:
#define
AG903_SDC_Block_Size_Transfer_Block_Size_MSK
(0xfffU <<
AG903_SDC_Block_Size_Transfer_Block_Size_POS
) 658:
#define
AG903_SDC_Block_Size_Host_SDMA_Buffer_Boundary_POS
12 659:
#define
AG903_SDC_Block_Size_Host_SDMA_Buffer_Boundary_MSK
(0x7U <<
AG903_SDC_Block_Size_Host_SDMA_Buffer_Boundary_POS
) 660: 661:
#define
AG903_SDC_Block_Count_Blocks_Count_For_Current_Transfer_POS
0 662:
#define
AG903_SDC_Block_Count_Blocks_Count_For_Current_Transfer_MSK
(0xffffU <<
AG903_SDC_Block_Count_Blocks_Count_For_Current_Transfer_POS
) 663: 664:
#define
AG903_SDC_Argument_1_Command_Argument_1_POS
0 665:
#define
AG903_SDC_Argument_1_Command_Argument_1_MSK
(0xffffffffUL <<
AG903_SDC_Argument_1_Command_Argument_1_POS
) 666: 667:
#define
AG903_SDC_Transfer_Mode_DMA_Enable_POS
0 668:
#define
AG903_SDC_Transfer_Mode_DMA_Enable_MSK
(0x1U <<
AG903_SDC_Transfer_Mode_DMA_Enable_POS
) 669:
#define
AG903_SDC_Transfer_Mode_Block_Count_Enable_POS
1 670:
#define
AG903_SDC_Transfer_Mode_Block_Count_Enable_MSK
(0x1U <<
AG903_SDC_Transfer_Mode_Block_Count_Enable_POS
) 671:
#define
AG903_SDC_Transfer_Mode_Auto_CMD_Enable_POS
2 672:
#define
AG903_SDC_Transfer_Mode_Auto_CMD_Enable_MSK
(0x3U <<
AG903_SDC_Transfer_Mode_Auto_CMD_Enable_POS
) 673:
#define
AG903_SDC_Transfer_Mode_Data_Transfer_Direction_Select_POS
4 674:
#define
AG903_SDC_Transfer_Mode_Data_Transfer_Direction_Select_MSK
(0x1U <<
AG903_SDC_Transfer_Mode_Data_Transfer_Direction_Select_POS
) 675:
#define
AG903_SDC_Transfer_Mode_Multi_Single_Block_Select_POS
5 676:
#define
AG903_SDC_Transfer_Mode_Multi_Single_Block_Select_MSK
(0x1U <<
AG903_SDC_Transfer_Mode_Multi_Single_Block_Select_POS
) 677: 678:
#define
AG903_SDC_Command_Response_Type_Select_POS
0 679:
#define
AG903_SDC_Command_Response_Type_Select_MSK
(0x3U <<
AG903_SDC_Command_Response_Type_Select_POS
) 680:
#define
AG903_SDC_Command_Command_CRC_Check_Enable_POS
3 681:
#define
AG903_SDC_Command_Command_CRC_Check_Enable_MSK
(0x1U <<
AG903_SDC_Command_Command_CRC_Check_Enable_POS
) 682:
#define
AG903_SDC_Command_Command_Index_Check_Enable_POS
4 683:
#define
AG903_SDC_Command_Command_Index_Check_Enable_MSK
(0x1U <<
AG903_SDC_Command_Command_Index_Check_Enable_POS
) 684:
#define
AG903_SDC_Command_Data_Present_Select_POS
5 685:
#define
AG903_SDC_Command_Data_Present_Select_MSK
(0x1U <<
AG903_SDC_Command_Data_Present_Select_POS
) 686:
#define
AG903_SDC_Command_Command_Type_POS
6 687:
#define
AG903_SDC_Command_Command_Type_MSK
(0x3U <<
AG903_SDC_Command_Command_Type_POS
) 688:
#define
AG903_SDC_Command_Command_Index_POS
8 689:
#define
AG903_SDC_Command_Command_Index_MSK
(0x3fU <<
AG903_SDC_Command_Command_Index_POS
) 690: 691:
#define
AG903_SDC_Response_Command_Response_POS
0 692:
#define
AG903_SDC_Response_Command_Response_MSK
(0xffffffffUL <<
AG903_SDC_Response_Command_Response_POS
) 693: 694:
#define
AG903_SDC_Buffer_Data_Port_Buffer_Data_POS
0 695:
#define
AG903_SDC_Buffer_Data_Port_Buffer_Data_MSK
(0xffffffffUL <<
AG903_SDC_Buffer_Data_Port_Buffer_Data_POS
) 696: 697:
#define
AG903_SDC_Present_State_Command_Inhibit_CMD_POS
0 698:
#define
AG903_SDC_Present_State_Command_Inhibit_CMD_MSK
(0x1UL <<
AG903_SDC_Present_State_Command_Inhibit_CMD_POS
) 699:
#define
AG903_SDC_Present_State_Command_Inhibit_LINE_POS
1 700:
#define
AG903_SDC_Present_State_Command_Inhibit_LINE_MSK
(0x1UL <<
AG903_SDC_Present_State_Command_Inhibit_LINE_POS
) 701:
#define
AG903_SDC_Present_State_DAT_Line_Active_POS
2 702:
#define
AG903_SDC_Present_State_DAT_Line_Active_MSK
(0x1UL <<
AG903_SDC_Present_State_DAT_Line_Active_POS
) 703:
#define
AG903_SDC_Present_State_Write_Transfer_Active_POS
8 704:
#define
AG903_SDC_Present_State_Write_Transfer_Active_MSK
(0x1UL <<
AG903_SDC_Present_State_Write_Transfer_Active_POS
) 705:
#define
AG903_SDC_Present_State_Read_Transfer_Active_POS
9 706:
#define
AG903_SDC_Present_State_Read_Transfer_Active_MSK
(0x1UL <<
AG903_SDC_Present_State_Read_Transfer_Active_POS
) 707:
#define
AG903_SDC_Present_State_Buffer_Write_Enable_POS
10 708:
#define
AG903_SDC_Present_State_Buffer_Write_Enable_MSK
(0x1UL <<
AG903_SDC_Present_State_Buffer_Write_Enable_POS
) 709:
#define
AG903_SDC_Present_State_Buffer_Read_Enable_POS
11 710:
#define
AG903_SDC_Present_State_Buffer_Read_Enable_MSK
(0x1UL <<
AG903_SDC_Present_State_Buffer_Read_Enable_POS
) 711:
#define
AG903_SDC_Present_State_Card_Inserted_POS
16 712:
#define
AG903_SDC_Present_State_Card_Inserted_MSK
(0x1UL <<
AG903_SDC_Present_State_Card_Inserted_POS
) 713:
#define
AG903_SDC_Present_State_Card_State_Stable_POS
17 714:
#define
AG903_SDC_Present_State_Card_State_Stable_MSK
(0x1UL <<
AG903_SDC_Present_State_Card_State_Stable_POS
) 715:
#define
AG903_SDC_Present_State_Card_Detect_Pin_Level_POS
18 716:
#define
AG903_SDC_Present_State_Card_Detect_Pin_Level_MSK
(0x1UL <<
AG903_SDC_Present_State_Card_Detect_Pin_Level_POS
) 717:
#define
AG903_SDC_Present_State_Write_Protect_Switch_Pin_Level_POS
19 718:
#define
AG903_SDC_Present_State_Write_Protect_Switch_Pin_Level_MSK
(0x1UL <<
AG903_SDC_Present_State_Write_Protect_Switch_Pin_Level_POS
) 719:
#define
AG903_SDC_Present_State_DAT_Line_Signal_Level_POS
20 720:
#define
AG903_SDC_Present_State_DAT_Line_Signal_Level_MSK
(0xfUL <<
AG903_SDC_Present_State_DAT_Line_Signal_Level_POS
) 721:
#define
AG903_SDC_Present_State_CMD_Line_Signal_Level_POS
24 722:
#define
AG903_SDC_Present_State_CMD_Line_Signal_Level_MSK
(0x1UL <<
AG903_SDC_Present_State_CMD_Line_Signal_Level_POS
) 723: 724:
#define
AG903_SDC_Host_Control_1_LED_Control_POS
0 725:
#define
AG903_SDC_Host_Control_1_LED_Control_MSK
(0x1U <<
AG903_SDC_Host_Control_1_LED_Control_POS
) 726:
#define
AG903_SDC_Host_Control_1_Data_Transfer_Width_POS
1 727:
#define
AG903_SDC_Host_Control_1_Data_Transfer_Width_MSK
(0x1U <<
AG903_SDC_Host_Control_1_Data_Transfer_Width_POS
) 728:
#define
AG903_SDC_Host_Control_1_High_Speed_Enable_POS
2 729:
#define
AG903_SDC_Host_Control_1_High_Speed_Enable_MSK
(0x1U <<
AG903_SDC_Host_Control_1_High_Speed_Enable_POS
) 730:
#define
AG903_SDC_Host_Control_1_DMA_Select_POS
3 731:
#define
AG903_SDC_Host_Control_1_DMA_Select_MSK
(0x3U <<
AG903_SDC_Host_Control_1_DMA_Select_POS
) 732:
#define
AG903_SDC_Host_Control_1_Extended_Sata_Transfer_Width_POS
5 733:
#define
AG903_SDC_Host_Control_1_Extended_Sata_Transfer_Width_MSK
(0x1U <<
AG903_SDC_Host_Control_1_Extended_Sata_Transfer_Width_POS
) 734:
#define
AG903_SDC_Host_Control_1_Card_Detect_Test_Level_POS
6 735:
#define
AG903_SDC_Host_Control_1_Card_Detect_Test_Level_MSK
(0x1U <<
AG903_SDC_Host_Control_1_Card_Detect_Test_Level_POS
) 736:
#define
AG903_SDC_Host_Control_1_Card_Detect_Signal_Selection_POS
7 737:
#define
AG903_SDC_Host_Control_1_Card_Detect_Signal_Selection_MSK
(0x1U <<
AG903_SDC_Host_Control_1_Card_Detect_Signal_Selection_POS
) 738: 739:
#define
AG903_SDC_Power_Control_Register_SD_Bus_Power_POS
0 740:
#define
AG903_SDC_Power_Control_Register_SD_Bus_Power_MSK
(0x1U <<
AG903_SDC_Power_Control_Register_SD_Bus_Power_POS
) 741:
#define
AG903_SDC_Power_Control_Register_SD_Bus_Voltage_Select_POS
1 742:
#define
AG903_SDC_Power_Control_Register_SD_Bus_Voltage_Select_MSK
(0x7U <<
AG903_SDC_Power_Control_Register_SD_Bus_Voltage_Select_POS
) 743: 744:
#define
AG903_SDC_Block_Gap_Control_Stop_At_Block_Gap_Request_POS
0 745:
#define
AG903_SDC_Block_Gap_Control_Stop_At_Block_Gap_Request_MSK
(0x1U <<
AG903_SDC_Block_Gap_Control_Stop_At_Block_Gap_Request_POS
) 746:
#define
AG903_SDC_Block_Gap_Control_Continue_Request_POS
1 747:
#define
AG903_SDC_Block_Gap_Control_Continue_Request_MSK
(0x1U <<
AG903_SDC_Block_Gap_Control_Continue_Request_POS
) 748:
#define
AG903_SDC_Block_Gap_Control_Read_Wait_Control_POS
2 749:
#define
AG903_SDC_Block_Gap_Control_Read_Wait_Control_MSK
(0x1U <<
AG903_SDC_Block_Gap_Control_Read_Wait_Control_POS
) 750:
#define
AG903_SDC_Block_Gap_Control_Interrupt_At_Block_Gap_POS
3 751:
#define
AG903_SDC_Block_Gap_Control_Interrupt_At_Block_Gap_MSK
(0x1U <<
AG903_SDC_Block_Gap_Control_Interrupt_At_Block_Gap_POS
) 752: 753:
#define
AG903_SDC_Clock_control_Internal_Clock_Enable_POS
0 754:
#define
AG903_SDC_Clock_control_Internal_Clock_Enable_MSK
(0x1U <<
AG903_SDC_Clock_control_Internal_Clock_Enable_POS
) 755:
#define
AG903_SDC_Clock_control_Internal_Clock_Stable_POS
1 756:
#define
AG903_SDC_Clock_control_Internal_Clock_Stable_MSK
(0x1U <<
AG903_SDC_Clock_control_Internal_Clock_Stable_POS
) 757:
#define
AG903_SDC_Clock_control_SD_Clock_Enable_POS
2 758:
#define
AG903_SDC_Clock_control_SD_Clock_Enable_MSK
(0x1U <<
AG903_SDC_Clock_control_SD_Clock_Enable_POS
) 759:
#define
AG903_SDC_Clock_control_Clock_Generator_Select_POS
5 760:
#define
AG903_SDC_Clock_control_Clock_Generator_Select_MSK
(0x1U <<
AG903_SDC_Clock_control_Clock_Generator_Select_POS
) 761:
#define
AG903_SDC_Clock_control_Upper_Bits_of_SDCLK_Frequency_Select_POS
6 762:
#define
AG903_SDC_Clock_control_Upper_Bits_of_SDCLK_Frequency_Select_MSK
(0x3U <<
AG903_SDC_Clock_control_Upper_Bits_of_SDCLK_Frequency_Select_POS
) 763:
#define
AG903_SDC_Clock_control_SDCLK_Frequency_Select_POS
8 764:
#define
AG903_SDC_Clock_control_SDCLK_Frequency_Select_MSK
(0xffU <<
AG903_SDC_Clock_control_SDCLK_Frequency_Select_POS
) 765: 766:
#define
AG903_SDC_Timeout_Control_Data_Timeout_Counter_Value_POS
0 767:
#define
AG903_SDC_Timeout_Control_Data_Timeout_Counter_Value_MSK
(0xfU <<
AG903_SDC_Timeout_Control_Data_Timeout_Counter_Value_POS
) 768: 769:
#define
AG903_SDC_Software_Reset_Software_Reset_For_All_POS
0 770:
#define
AG903_SDC_Software_Reset_Software_Reset_For_All_MSK
(0x1U <<
AG903_SDC_Software_Reset_Software_Reset_For_All_POS
) 771:
#define
AG903_SDC_Software_Reset_Software_Reset_For_CMD_Line_POS
1 772:
#define
AG903_SDC_Software_Reset_Software_Reset_For_CMD_Line_MSK
(0x1U <<
AG903_SDC_Software_Reset_Software_Reset_For_CMD_Line_POS
) 773:
#define
AG903_SDC_Software_Reset_Software_Reset_For_DAT_Line_POS
2 774:
#define
AG903_SDC_Software_Reset_Software_Reset_For_DAT_Line_MSK
(0x1U <<
AG903_SDC_Software_Reset_Software_Reset_For_DAT_Line_POS
) 775: 776:
#define
AG903_SDC_Normal_Interrupt_Status_Command_Complete_POS
0 777:
#define
AG903_SDC_Normal_Interrupt_Status_Command_Complete_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Command_Complete_POS
) 778:
#define
AG903_SDC_Normal_Interrupt_Status_Transfer_Complete_POS
1 779:
#define
AG903_SDC_Normal_Interrupt_Status_Transfer_Complete_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Transfer_Complete_POS
) 780:
#define
AG903_SDC_Normal_Interrupt_Status_Block_Gap_Event_POS
2 781:
#define
AG903_SDC_Normal_Interrupt_Status_Block_Gap_Event_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Block_Gap_Event_POS
) 782:
#define
AG903_SDC_Normal_Interrupt_Status_DMA_Interrupt_POS
3 783:
#define
AG903_SDC_Normal_Interrupt_Status_DMA_Interrupt_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_DMA_Interrupt_POS
) 784:
#define
AG903_SDC_Normal_Interrupt_Status_Butter_Write_Ready_POS
4 785:
#define
AG903_SDC_Normal_Interrupt_Status_Butter_Write_Ready_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Butter_Write_Ready_POS
) 786:
#define
AG903_SDC_Normal_Interrupt_Status_Buffer_Read_Ready_POS
5 787:
#define
AG903_SDC_Normal_Interrupt_Status_Buffer_Read_Ready_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Buffer_Read_Ready_POS
) 788:
#define
AG903_SDC_Normal_Interrupt_Status_Card_Insertion_POS
6 789:
#define
AG903_SDC_Normal_Interrupt_Status_Card_Insertion_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Card_Insertion_POS
) 790:
#define
AG903_SDC_Normal_Interrupt_Status_Card_Removal_POS
7 791:
#define
AG903_SDC_Normal_Interrupt_Status_Card_Removal_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Card_Removal_POS
) 792:
#define
AG903_SDC_Normal_Interrupt_Status_Card_Interrupt_POS
8 793:
#define
AG903_SDC_Normal_Interrupt_Status_Card_Interrupt_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Card_Interrupt_POS
) 794:
#define
AG903_SDC_Normal_Interrupt_Status_INT_A_POS
9 795:
#define
AG903_SDC_Normal_Interrupt_Status_INT_A_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_INT_A_POS
) 796:
#define
AG903_SDC_Normal_Interrupt_Status_INT_B_POS
10 797:
#define
AG903_SDC_Normal_Interrupt_Status_INT_B_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_INT_B_POS
) 798:
#define
AG903_SDC_Normal_Interrupt_Status_INT_C_POS
11 799:
#define
AG903_SDC_Normal_Interrupt_Status_INT_C_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_INT_C_POS
) 800:
#define
AG903_SDC_Normal_Interrupt_Status_ReTuning_Event_POS
12 801:
#define
AG903_SDC_Normal_Interrupt_Status_ReTuning_Event_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_ReTuning_Event_POS
) 802:
#define
AG903_SDC_Normal_Interrupt_Status_Error_Interrupt_POS
15 803:
#define
AG903_SDC_Normal_Interrupt_Status_Error_Interrupt_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Error_Interrupt_POS
) 804: 805:
#define
AG903_SDC_Error_Interrupt_Status_Command_Timeout_Error_POS
0 806:
#define
AG903_SDC_Error_Interrupt_Status_Command_Timeout_Error_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Command_Timeout_Error_POS
) 807:
#define
AG903_SDC_Error_Interrupt_Status_Command_CRC_Error_POS
1 808:
#define
AG903_SDC_Error_Interrupt_Status_Command_CRC_Error_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Command_CRC_Error_POS
) 809:
#define
AG903_SDC_Error_Interrupt_Status_Command_End_Bit_Error_POS
2 810:
#define
AG903_SDC_Error_Interrupt_Status_Command_End_Bit_Error_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Command_End_Bit_Error_POS
) 811:
#define
AG903_SDC_Error_Interrupt_Status_Command_Index_Error_POS
3 812:
#define
AG903_SDC_Error_Interrupt_Status_Command_Index_Error_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Command_Index_Error_POS
) 813:
#define
AG903_SDC_Error_Interrupt_Status_Data_Timeout_Error_POS
4 814:
#define
AG903_SDC_Error_Interrupt_Status_Data_Timeout_Error_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Data_Timeout_Error_POS
) 815:
#define
AG903_SDC_Error_Interrupt_Status_Data_CRC_Error_POS
5 816:
#define
AG903_SDC_Error_Interrupt_Status_Data_CRC_Error_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Data_CRC_Error_POS
) 817:
#define
AG903_SDC_Error_Interrupt_Status_Data_End_Bit_Error_POS
6 818:
#define
AG903_SDC_Error_Interrupt_Status_Data_End_Bit_Error_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Data_End_Bit_Error_POS
) 819:
#define
AG903_SDC_Error_Interrupt_Status_Current_Limit_Error_POS
7 820:
#define
AG903_SDC_Error_Interrupt_Status_Current_Limit_Error_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Current_Limit_Error_POS
) 821:
#define
AG903_SDC_Error_Interrupt_Status_Auto_CMD_Error_POS
8 822:
#define
AG903_SDC_Error_Interrupt_Status_Auto_CMD_Error_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Auto_CMD_Error_POS
) 823:
#define
AG903_SDC_Error_Interrupt_Status_ADMA_Error_POS
9 824:
#define
AG903_SDC_Error_Interrupt_Status_ADMA_Error_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_ADMA_Error_POS
) 825:
#define
AG903_SDC_Error_Interrupt_Status_Tuning_Error_POS
10 826:
#define
AG903_SDC_Error_Interrupt_Status_Tuning_Error_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Tuning_Error_POS
) 827: 828:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Command_Complete_Status_Enable_POS
0 829:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Command_Complete_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_Command_Complete_Status_Enable_POS
) 830:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Transfer_Complete_Status_Enable_POS
1 831:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Transfer_Complete_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_Transfer_Complete_Status_Enable_POS
) 832:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Block_Gap_Event_Status_Enable_POS
2 833:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Block_Gap_Event_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_Block_Gap_Event_Status_Enable_POS
) 834:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_DMA_Interrupt_Status_Enable_POS
3 835:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_DMA_Interrupt_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_DMA_Interrupt_Status_Enable_POS
) 836:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Buffer_Write_Ready_Status_Enable_POS
4 837:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Buffer_Write_Ready_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_Buffer_Write_Ready_Status_Enable_POS
) 838:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Buffer_Read_Ready_Status_Enable_POS
5 839:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Buffer_Read_Ready_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_Buffer_Read_Ready_Status_Enable_POS
) 840:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Card_Insertion_Status_Enable_POS
6 841:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Card_Insertion_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_Card_Insertion_Status_Enable_POS
) 842:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Card_Removal_Status_Enable_POS
7 843:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Card_Removal_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_Card_Removal_Status_Enable_POS
) 844:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Card_Interrupt_Status_Enable_POS
8 845:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_Card_Interrupt_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_Card_Interrupt_Status_Enable_POS
) 846:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_INT_A_Status_Enable_POS
9 847:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_INT_A_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_INT_A_Status_Enable_POS
) 848:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_INT_B_Status_Enable_POS
10 849:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_INT_B_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_INT_B_Status_Enable_POS
) 850:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_INT_C_Status_Enable_POS
11 851:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_INT_C_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_INT_C_Status_Enable_POS
) 852:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_ReTuning_Event_Status_Enable_POS
12 853:
#define
AG903_SDC_Normal_Interrupt_Status_Enable_ReTuning_Event_Status_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Status_Enable_ReTuning_Event_Status_Enable_POS
) 854: 855:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Command_Timeout_Error_Status_Enable_POS
0 856:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Command_Timeout_Error_Status_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Enable_Command_Timeout_Error_Status_Enable_POS
) 857:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Command_CRC_Error_Status_Enable_POS
1 858:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Command_CRC_Error_Status_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Enable_Command_CRC_Error_Status_Enable_POS
) 859:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Command_End_Bit_Error_Status_Enable_POS
2 860:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Command_End_Bit_Error_Status_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Enable_Command_End_Bit_Error_Status_Enable_POS
) 861:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Command_Index_Error_Status_Enable_POS
3 862:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Command_Index_Error_Status_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Enable_Command_Index_Error_Status_Enable_POS
) 863:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Data_Timeout_Error_Status_Enable_POS
4 864:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Data_Timeout_Error_Status_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Enable_Data_Timeout_Error_Status_Enable_POS
) 865:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Data_CRC_Error_Status_Enable_POS
5 866:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Data_CRC_Error_Status_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Enable_Data_CRC_Error_Status_Enable_POS
) 867:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Data_End_Bit_Error_Status_Enable_POS
6 868:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Data_End_Bit_Error_Status_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Enable_Data_End_Bit_Error_Status_Enable_POS
) 869:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Current_Limit_Error_Status_Enable_POS
7 870:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Current_Limit_Error_Status_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Enable_Current_Limit_Error_Status_Enable_POS
) 871:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Auto_CMD_Error_Status_Enable_POS
8 872:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Auto_CMD_Error_Status_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Enable_Auto_CMD_Error_Status_Enable_POS
) 873:
#define
AG903_SDC_Error_Interrupt_Status_Enable_ADMA_Error_Status_Enable_POS
9 874:
#define
AG903_SDC_Error_Interrupt_Status_Enable_ADMA_Error_Status_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Enable_ADMA_Error_Status_Enable_POS
) 875:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Tuning_Error_Status_Enable_POS
10 876:
#define
AG903_SDC_Error_Interrupt_Status_Enable_Tuning_Error_Status_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Status_Enable_Tuning_Error_Status_Enable_POS
) 877: 878:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Command_Complete_Signal_Enable_POS
0 879:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Command_Complete_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_Command_Complete_Signal_Enable_POS
) 880:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Transfer_Complete_Signal_Enable_POS
1 881:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Transfer_Complete_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_Transfer_Complete_Signal_Enable_POS
) 882:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Block_Gap_Event_Signal_Enable_POS
2 883:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Block_Gap_Event_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_Block_Gap_Event_Signal_Enable_POS
) 884:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_DMA_Interrupt_Signal_Enable_POS
3 885:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_DMA_Interrupt_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_DMA_Interrupt_Signal_Enable_POS
) 886:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Buffer_Write_Ready_Signal_Enable_POS
4 887:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Buffer_Write_Ready_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_Buffer_Write_Ready_Signal_Enable_POS
) 888:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Buffer_Read_Ready_Signal_Enable_POS
5 889:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Buffer_Read_Ready_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_Buffer_Read_Ready_Signal_Enable_POS
) 890:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Card_Insertion_Signal_Enable_POS
6 891:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Card_Insertion_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_Card_Insertion_Signal_Enable_POS
) 892:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Card_Removal_Signal_Enable_POS
7 893:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Card_Removal_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_Card_Removal_Signal_Enable_POS
) 894:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Card_Interrupt_Signal_Enable_POS
8 895:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_Card_Interrupt_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_Card_Interrupt_Signal_Enable_POS
) 896:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_INT_A_Signal_Enable_POS
9 897:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_INT_A_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_INT_A_Signal_Enable_POS
) 898:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_INT_B_Signal_Enable_POS
10 899:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_INT_B_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_INT_B_Signal_Enable_POS
) 900:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_INT_C_Signal_Enable_POS
11 901:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_INT_C_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_INT_C_Signal_Enable_POS
) 902:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_ReTuning_Event_Signal_Enable_POS
12 903:
#define
AG903_SDC_Normal_Interrupt_Signal_Enable_ReTuning_Event_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Normal_Interrupt_Signal_Enable_ReTuning_Event_Signal_Enable_POS
) 904: 905:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Command_Timeout_Error_Signal_Enable_POS
0 906:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Command_Timeout_Error_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Signal_Enable_Command_Timeout_Error_Signal_Enable_POS
) 907:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Command_CRC_Error_Signal_Enable_POS
1 908:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Command_CRC_Error_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Signal_Enable_Command_CRC_Error_Signal_Enable_POS
) 909:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Command_End_Bit_Error_Signal_Enable_POS
2 910:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Command_End_Bit_Error_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Signal_Enable_Command_End_Bit_Error_Signal_Enable_POS
) 911:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Command_Index_Error_Signal_Enable_POS
3 912:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Command_Index_Error_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Signal_Enable_Command_Index_Error_Signal_Enable_POS
) 913:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Data_Timeout_Error_Signal_Enable_POS
4 914:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Data_Timeout_Error_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Signal_Enable_Data_Timeout_Error_Signal_Enable_POS
) 915:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Data_CRC_Error_Signal_Enable_POS
5 916:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Data_CRC_Error_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Signal_Enable_Data_CRC_Error_Signal_Enable_POS
) 917:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Data_End_Bit_Error_Signal_Enable_POS
6 918:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Data_End_Bit_Error_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Signal_Enable_Data_End_Bit_Error_Signal_Enable_POS
) 919:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Current_Limit_Error_Signal_Enable_POS
7 920:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Current_Limit_Error_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Signal_Enable_Current_Limit_Error_Signal_Enable_POS
) 921:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Auto_CMD_Error_Signal_Enable_POS
8 922:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Auto_CMD_Error_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Signal_Enable_Auto_CMD_Error_Signal_Enable_POS
) 923:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_ADMA_Error_Signal_Enable_POS
9 924:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_ADMA_Error_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Signal_Enable_ADMA_Error_Signal_Enable_POS
) 925:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Tuning_Error_Signal_Enable_POS
10 926:
#define
AG903_SDC_Error_Interrupt_Signal_Enable_Tuning_Error_Signal_Enable_MSK
(0x1U <<
AG903_SDC_Error_Interrupt_Signal_Enable_Tuning_Error_Signal_Enable_POS
) 927: 928:
#define
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD12_Npt_Executed_POS
0 929:
#define
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD12_Npt_Executed_MSK
(0x1U <<
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD12_Npt_Executed_POS
) 930:
#define
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD_Timeout_Error_POS
1 931:
#define
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD_Timeout_Error_MSK
(0x1U <<
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD_Timeout_Error_POS
) 932:
#define
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD_CRC_Error_POS
2 933:
#define
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD_CRC_Error_MSK
(0x1U <<
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD_CRC_Error_POS
) 934:
#define
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD_End_Bit_Error_POS
3 935:
#define
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD_End_Bit_Error_MSK
(0x1U <<
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD_End_Bit_Error_POS
) 936:
#define
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD_Index_Error_POS
4 937:
#define
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD_Index_Error_MSK
(0x1U <<
AG903_SDC_Auto_CMD_Error_Status_Auto_CMD_Index_Error_POS
) 938:
#define
AG903_SDC_Auto_CMD_Error_Status_Command_Not_Issued_By_Auto_CMD12_Error_POS
7 939:
#define
AG903_SDC_Auto_CMD_Error_Status_Command_Not_Issued_By_Auto_CMD12_Error_MSK
(0x1U <<
AG903_SDC_Auto_CMD_Error_Status_Command_Not_Issued_By_Auto_CMD12_Error_POS
) 940: 941:
#define
AG903_SDC_Host_Control_2_UHS_Mode_Select_POS
0 942:
#define
AG903_SDC_Host_Control_2_UHS_Mode_Select_MSK
(0x7U <<
AG903_SDC_Host_Control_2_UHS_Mode_Select_POS
) 943:
#define
AG903_SDC_Host_Control_2_V1p8_Signaling_Enable_POS
3 944:
#define
AG903_SDC_Host_Control_2_V1p8_Signaling_Enable_MSK
(0x1U <<
AG903_SDC_Host_Control_2_V1p8_Signaling_Enable_POS
) 945:
#define
AG903_SDC_Host_Control_2_Driver_Strength_Select_POS
4 946:
#define
AG903_SDC_Host_Control_2_Driver_Strength_Select_MSK
(0x3U <<
AG903_SDC_Host_Control_2_Driver_Strength_Select_POS
) 947:
#define
AG903_SDC_Host_Control_2_Execute_Tuning_POS
6 948:
#define
AG903_SDC_Host_Control_2_Execute_Tuning_MSK
(0x1U <<
AG903_SDC_Host_Control_2_Execute_Tuning_POS
) 949:
#define
AG903_SDC_Host_Control_2_Sampling_Clock_Select_POS
7 950:
#define
AG903_SDC_Host_Control_2_Sampling_Clock_Select_MSK
(0x1U <<
AG903_SDC_Host_Control_2_Sampling_Clock_Select_POS
) 951:
#define
AG903_SDC_Host_Control_2_Asynchronous_Interrupt_Enable_POS
14 952:
#define
AG903_SDC_Host_Control_2_Asynchronous_Interrupt_Enable_MSK
(0x1U <<
AG903_SDC_Host_Control_2_Asynchronous_Interrupt_Enable_POS
) 953:
#define
AG903_SDC_Host_Control_2_Preset_Value_Enable_POS
15 954:
#define
AG903_SDC_Host_Control_2_Preset_Value_Enable_MSK
(0x1U <<
AG903_SDC_Host_Control_2_Preset_Value_Enable_POS
) 955: 956:
#define
AG903_SDC_Capabilities_Timeout_Clock_Frequency_POS
0 957:
#define
AG903_SDC_Capabilities_Timeout_Clock_Frequency_MSK
(0x3fULL <<
AG903_SDC_Capabilities_Timeout_Clock_Frequency_POS
) 958:
#define
AG903_SDC_Capabilities_Timeout_Clock_Count_POS
7 959:
#define
AG903_SDC_Capabilities_Timeout_Clock_Count_MSK
(0x1ULL <<
AG903_SDC_Capabilities_Timeout_Clock_Count_POS
) 960:
#define
AG903_SDC_Capabilities_Base_Clock_Frequency_For_SD_Clock_POS
8 961:
#define
AG903_SDC_Capabilities_Base_Clock_Frequency_For_SD_Clock_MSK
(0xffULL <<
AG903_SDC_Capabilities_Base_Clock_Frequency_For_SD_Clock_POS
) 962:
#define
AG903_SDC_Capabilities_Max_Block_Length_POS
16 963:
#define
AG903_SDC_Capabilities_Max_Block_Length_MSK
(0x3ULL <<
AG903_SDC_Capabilities_Max_Block_Length_POS
) 964:
#define
AG903_SDC_Capabilities_B8_Support_for_Embedded_Device_POS
18 965:
#define
AG903_SDC_Capabilities_B8_Support_for_Embedded_Device_MSK
(0x1ULL <<
AG903_SDC_Capabilities_B8_Support_for_Embedded_Device_POS
) 966:
#define
AG903_SDC_Capabilities_ADMA2_Support_POS
19 967:
#define
AG903_SDC_Capabilities_ADMA2_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_ADMA2_Support_POS
) 968:
#define
AG903_SDC_Capabilities_ADMA1_Support_POS
20 969:
#define
AG903_SDC_Capabilities_ADMA1_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_ADMA1_Support_POS
) 970:
#define
AG903_SDC_Capabilities_High_Speed_Support_POS
21 971:
#define
AG903_SDC_Capabilities_High_Speed_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_High_Speed_Support_POS
) 972:
#define
AG903_SDC_Capabilities_SDMA_Support_POS
22 973:
#define
AG903_SDC_Capabilities_SDMA_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_SDMA_Support_POS
) 974:
#define
AG903_SDC_Capabilities_Suspend_Resume_Support_POS
23 975:
#define
AG903_SDC_Capabilities_Suspend_Resume_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_Suspend_Resume_Support_POS
) 976:
#define
AG903_SDC_Capabilities_Voltage_Support_3p3V_POS
24 977:
#define
AG903_SDC_Capabilities_Voltage_Support_3p3V_MSK
(0x1ULL <<
AG903_SDC_Capabilities_Voltage_Support_3p3V_POS
) 978:
#define
AG903_SDC_Capabilities_Voltage_Support_3p0V_POS
25 979:
#define
AG903_SDC_Capabilities_Voltage_Support_3p0V_MSK
(0x1ULL <<
AG903_SDC_Capabilities_Voltage_Support_3p0V_POS
) 980:
#define
AG903_SDC_Capabilities_Voltage_Support_1p8V_POS
26 981:
#define
AG903_SDC_Capabilities_Voltage_Support_1p8V_MSK
(0x1ULL <<
AG903_SDC_Capabilities_Voltage_Support_1p8V_POS
) 982:
#define
AG903_SDC_Capabilities_B64_System_Bus_Support_POS
28 983:
#define
AG903_SDC_Capabilities_B64_System_Bus_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_B64_System_Bus_Support_POS
) 984:
#define
AG903_SDC_Capabilities_Asynchronous_Interrupt_Support_POS
29 985:
#define
AG903_SDC_Capabilities_Asynchronous_Interrupt_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_Asynchronous_Interrupt_Support_POS
) 986:
#define
AG903_SDC_Capabilities_Slot_Type_POS
30 987:
#define
AG903_SDC_Capabilities_Slot_Type_MSK
(0x3ULL <<
AG903_SDC_Capabilities_Slot_Type_POS
) 988:
#define
AG903_SDC_Capabilities_SDR50_Support_POS
32 989:
#define
AG903_SDC_Capabilities_SDR50_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_SDR50_Support_POS
) 990:
#define
AG903_SDC_Capabilities_SDR104_Support_POS
33 991:
#define
AG903_SDC_Capabilities_SDR104_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_SDR104_Support_POS
) 992:
#define
AG903_SDC_Capabilities_DDR50_Support_POS
34 993:
#define
AG903_SDC_Capabilities_DDR50_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_DDR50_Support_POS
) 994:
#define
AG903_SDC_Capabilities_Driver_Type_A_Support_POS
36 995:
#define
AG903_SDC_Capabilities_Driver_Type_A_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_Driver_Type_A_Support_POS
) 996:
#define
AG903_SDC_Capabilities_Driver_Type_C_Support_POS
37 997:
#define
AG903_SDC_Capabilities_Driver_Type_C_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_Driver_Type_C_Support_POS
) 998:
#define
AG903_SDC_Capabilities_Driver_Type_D_Support_POS
38 999:
#define
AG903_SDC_Capabilities_Driver_Type_D_Support_MSK
(0x1ULL <<
AG903_SDC_Capabilities_Driver_Type_D_Support_POS
) 1000:
#define
AG903_SDC_Capabilities_Timer_Count_for_ReTuning_POS
40 1001:
#define
AG903_SDC_Capabilities_Timer_Count_for_ReTuning_MSK
(0xfULL <<
AG903_SDC_Capabilities_Timer_Count_for_ReTuning_POS
) 1002:
#define
AG903_SDC_Capabilities_User_Tuning_for_SDR50_POS
45 1003:
#define
AG903_SDC_Capabilities_User_Tuning_for_SDR50_MSK
(0x1ULL <<
AG903_SDC_Capabilities_User_Tuning_for_SDR50_POS
) 1004:
#define
AG903_SDC_Capabilities_ReTuning_Modes_POS
46 1005:
#define
AG903_SDC_Capabilities_ReTuning_Modes_MSK
(0x3ULL <<
AG903_SDC_Capabilities_ReTuning_Modes_POS
) 1006:
#define
AG903_SDC_Capabilities_Clock_Multiplier_POS
48 1007:
#define
AG903_SDC_Capabilities_Clock_Multiplier_MSK
(0xffULL <<
AG903_SDC_Capabilities_Clock_Multiplier_POS
) 1008: 1009:
#define
AG903_SDC_Maximum_Current_Capabilities_Maximum_Current_for_3p3V_POS
0 1010:
#define
AG903_SDC_Maximum_Current_Capabilities_Maximum_Current_for_3p3V_MSK
(0xffULL <<
AG903_SDC_Maximum_Current_Capabilities_Maximum_Current_for_3p3V_POS
) 1011:
#define
AG903_SDC_Maximum_Current_Capabilities_Maximum_Current_for_3p0V_POS
8 1012:
#define
AG903_SDC_Maximum_Current_Capabilities_Maximum_Current_for_3p0V_MSK
(0xffULL <<
AG903_SDC_Maximum_Current_Capabilities_Maximum_Current_for_3p0V_POS
) 1013:
#define
AG903_SDC_Maximum_Current_Capabilities_Maximum_Current_for_1p8V_POS
16 1014:
#define
AG903_SDC_Maximum_Current_Capabilities_Maximum_Current_for_1p8V_MSK
(0xffULL <<
AG903_SDC_Maximum_Current_Capabilities_Maximum_Current_for_1p8V_POS
) 1015: 1016:
#define
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD12_Not_Executed_POS
0 1017:
#define
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD12_Not_Executed_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD12_Not_Executed_POS
) 1018:
#define
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD_Timeout_Error_POS
1 1019:
#define
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD_Timeout_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD_Timeout_Error_POS
) 1020:
#define
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD_CRC_Error_POS
2 1021:
#define
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD_CRC_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD_CRC_Error_POS
) 1022:
#define
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD_End_Bit_Error_POS
3 1023:
#define
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD_End_Bit_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD_End_Bit_Error_POS
) 1024:
#define
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD_Index_Error_POS
4 1025:
#define
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD_Index_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Auto_CMD_Index_Error_POS
) 1026:
#define
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Command_Not_Issued_By_Auto_CMD12_Error_POS
7 1027:
#define
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Command_Not_Issued_By_Auto_CMD12_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Auto_CMD_Error_Status_Force_Event_for_Command_Not_Issued_By_Auto_CMD12_Error_POS
) 1028: 1029:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Command_Timeout_Error_POS
0 1030:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Command_Timeout_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Command_Timeout_Error_POS
) 1031:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Command_CRC_Error_POS
1 1032:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Command_CRC_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Command_CRC_Error_POS
) 1033:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Command_End_Bit_Error_POS
2 1034:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Command_End_Bit_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Command_End_Bit_Error_POS
) 1035:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Command_Index_Error_POS
3 1036:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Command_Index_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Command_Index_Error_POS
) 1037:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Data_Timeout_Error_POS
4 1038:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Data_Timeout_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Data_Timeout_Error_POS
) 1039:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Data_CRC_Error_POS
5 1040:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Data_CRC_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Data_CRC_Error_POS
) 1041:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Data_End_Bit_Error_POS
6 1042:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Data_End_Bit_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Data_End_Bit_Error_POS
) 1043:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Current_Limit_Error_POS
7 1044:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Current_Limit_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Current_Limit_Error_POS
) 1045:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Auto_CMD_Error_POS
8 1046:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Auto_CMD_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_Auto_CMD_Error_POS
) 1047:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_ADMA_Error_POS
9 1048:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_ADMA_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_ADMA_Error_POS
) 1049:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_AHB_Response_Error_POS
12 1050:
#define
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_AHB_Response_Error_MSK
(0x1U <<
AG903_SDC_Force_Event_for_Error_Interrupt_Status_Force_Event_for_AHB_Response_Error_POS
) 1051: 1052:
#define
AG903_SDC_ADMA_Error_Status_ADMA_Error_State_POS
0 1053:
#define
AG903_SDC_ADMA_Error_Status_ADMA_Error_State_MSK
(0x3U <<
AG903_SDC_ADMA_Error_Status_ADMA_Error_State_POS
) 1054:
#define
AG903_SDC_ADMA_Error_Status_ADMA_Length_Mismatch_Error_POS
2 1055:
#define
AG903_SDC_ADMA_Error_Status_ADMA_Length_Mismatch_Error_MSK
(0x1U <<
AG903_SDC_ADMA_Error_Status_ADMA_Length_Mismatch_Error_POS
) 1056: 1057:
#define
AG903_SDC_ADMA_System_Address_ADMA_System_Address_POS
0 1058:
#define
AG903_SDC_ADMA_System_Address_ADMA_System_Address_MSK
(0xffffffffULL <<
AG903_SDC_ADMA_System_Address_ADMA_System_Address_POS
) 1059: 1060:
#define
AG903_SDC_Preset_Value_INIT_SDCLK_Frequency_Select_Value_POS
0 1061:
#define
AG903_SDC_Preset_Value_INIT_SDCLK_Frequency_Select_Value_MSK
(0x3ffU <<
AG903_SDC_Preset_Value_INIT_SDCLK_Frequency_Select_Value_POS
) 1062:
#define
AG903_SDC_Preset_Value_INIT_Clock_Generator_Select_Value_POS
10 1063:
#define
AG903_SDC_Preset_Value_INIT_Clock_Generator_Select_Value_MSK
(0x1U <<
AG903_SDC_Preset_Value_INIT_Clock_Generator_Select_Value_POS
) 1064:
#define
AG903_SDC_Preset_Value_INIT_Driver_Strength_Select_Value_POS
14 1065:
#define
AG903_SDC_Preset_Value_INIT_Driver_Strength_Select_Value_MSK
(0x3U <<
AG903_SDC_Preset_Value_INIT_Driver_Strength_Select_Value_POS
) 1066: 1067:
#define
AG903_SDC_Preset_Value_DS_SDCLK_Frequency_Select_Value_POS
0 1068:
#define
AG903_SDC_Preset_Value_DS_SDCLK_Frequency_Select_Value_MSK
(0x3ffU <<
AG903_SDC_Preset_Value_DS_SDCLK_Frequency_Select_Value_POS
) 1069:
#define
AG903_SDC_Preset_Value_DS_Clock_Generator_Select_Value_POS
10 1070:
#define
AG903_SDC_Preset_Value_DS_Clock_Generator_Select_Value_MSK
(0x1U <<
AG903_SDC_Preset_Value_DS_Clock_Generator_Select_Value_POS
) 1071:
#define
AG903_SDC_Preset_Value_DS_Driver_Strength_Select_Value_POS
14 1072:
#define
AG903_SDC_Preset_Value_DS_Driver_Strength_Select_Value_MSK
(0x3U <<
AG903_SDC_Preset_Value_DS_Driver_Strength_Select_Value_POS
) 1073: 1074:
#define
AG903_SDC_Preset_Value_HS_SDCLK_Frequency_Select_Value_POS
0 1075:
#define
AG903_SDC_Preset_Value_HS_SDCLK_Frequency_Select_Value_MSK
(0x3ffU <<
AG903_SDC_Preset_Value_HS_SDCLK_Frequency_Select_Value_POS
) 1076:
#define
AG903_SDC_Preset_Value_HS_Clock_Generator_Select_Value_POS
10 1077:
#define
AG903_SDC_Preset_Value_HS_Clock_Generator_Select_Value_MSK
(0x1U <<
AG903_SDC_Preset_Value_HS_Clock_Generator_Select_Value_POS
) 1078:
#define
AG903_SDC_Preset_Value_HS_Driver_Strength_Select_Value_POS
14 1079:
#define
AG903_SDC_Preset_Value_HS_Driver_Strength_Select_Value_MSK
(0x3U <<
AG903_SDC_Preset_Value_HS_Driver_Strength_Select_Value_POS
) 1080: 1081:
#define
AG903_SDC_Preset_Value_SDR12_SDCLK_Frequency_Select_Value_POS
0 1082:
#define
AG903_SDC_Preset_Value_SDR12_SDCLK_Frequency_Select_Value_MSK
(0x3ffU <<
AG903_SDC_Preset_Value_SDR12_SDCLK_Frequency_Select_Value_POS
) 1083:
#define
AG903_SDC_Preset_Value_SDR12_Clock_Generator_Select_Value_POS
10 1084:
#define
AG903_SDC_Preset_Value_SDR12_Clock_Generator_Select_Value_MSK
(0x1U <<
AG903_SDC_Preset_Value_SDR12_Clock_Generator_Select_Value_POS
) 1085:
#define
AG903_SDC_Preset_Value_SDR12_Driver_Strength_Select_Value_POS
14 1086:
#define
AG903_SDC_Preset_Value_SDR12_Driver_Strength_Select_Value_MSK
(0x3U <<
AG903_SDC_Preset_Value_SDR12_Driver_Strength_Select_Value_POS
) 1087: 1088:
#define
AG903_SDC_Preset_Value_SDR25_SDCLK_Frequency_Select_Value_POS
0 1089:
#define
AG903_SDC_Preset_Value_SDR25_SDCLK_Frequency_Select_Value_MSK
(0x3ffU <<
AG903_SDC_Preset_Value_SDR25_SDCLK_Frequency_Select_Value_POS
) 1090:
#define
AG903_SDC_Preset_Value_SDR25_Clock_Generator_Select_Value_POS
10 1091:
#define
AG903_SDC_Preset_Value_SDR25_Clock_Generator_Select_Value_MSK
(0x1U <<
AG903_SDC_Preset_Value_SDR25_Clock_Generator_Select_Value_POS
) 1092:
#define
AG903_SDC_Preset_Value_SDR25_Driver_Strength_Select_Value_POS
14 1093:
#define
AG903_SDC_Preset_Value_SDR25_Driver_Strength_Select_Value_MSK
(0x3U <<
AG903_SDC_Preset_Value_SDR25_Driver_Strength_Select_Value_POS
) 1094: 1095:
#define
AG903_SDC_Preset_Value_SDR50_SDCLK_Frequency_Select_Value_POS
0 1096:
#define
AG903_SDC_Preset_Value_SDR50_SDCLK_Frequency_Select_Value_MSK
(0x3ffU <<
AG903_SDC_Preset_Value_SDR50_SDCLK_Frequency_Select_Value_POS
) 1097:
#define
AG903_SDC_Preset_Value_SDR50_Clock_Generator_Select_Value_POS
10 1098:
#define
AG903_SDC_Preset_Value_SDR50_Clock_Generator_Select_Value_MSK
(0x1U <<
AG903_SDC_Preset_Value_SDR50_Clock_Generator_Select_Value_POS
) 1099:
#define
AG903_SDC_Preset_Value_SDR50_Driver_Strength_Select_Value_POS
14 1100:
#define
AG903_SDC_Preset_Value_SDR50_Driver_Strength_Select_Value_MSK
(0x3U <<
AG903_SDC_Preset_Value_SDR50_Driver_Strength_Select_Value_POS
) 1101: 1102:
#define
AG903_SDC_Preset_Value_SDR104_SDCLK_Frequency_Select_Value_POS
0 1103:
#define
AG903_SDC_Preset_Value_SDR104_SDCLK_Frequency_Select_Value_MSK
(0x3ffU <<
AG903_SDC_Preset_Value_SDR104_SDCLK_Frequency_Select_Value_POS
) 1104:
#define
AG903_SDC_Preset_Value_SDR104_Clock_Generator_Select_Value_POS
10 1105:
#define
AG903_SDC_Preset_Value_SDR104_Clock_Generator_Select_Value_MSK
(0x1U <<
AG903_SDC_Preset_Value_SDR104_Clock_Generator_Select_Value_POS
) 1106:
#define
AG903_SDC_Preset_Value_SDR104_Driver_Strength_Select_Value_POS
14 1107:
#define
AG903_SDC_Preset_Value_SDR104_Driver_Strength_Select_Value_MSK
(0x3U <<
AG903_SDC_Preset_Value_SDR104_Driver_Strength_Select_Value_POS
) 1108: 1109:
#define
AG903_SDC_Preset_Value_DDR50_SDCLK_Frequency_Select_Value_POS
0 1110:
#define
AG903_SDC_Preset_Value_DDR50_SDCLK_Frequency_Select_Value_MSK
(0x3ffU <<
AG903_SDC_Preset_Value_DDR50_SDCLK_Frequency_Select_Value_POS
) 1111:
#define
AG903_SDC_Preset_Value_DDR50_Clock_Generator_Select_Value_POS
10 1112:
#define
AG903_SDC_Preset_Value_DDR50_Clock_Generator_Select_Value_MSK
(0x1U <<
AG903_SDC_Preset_Value_DDR50_Clock_Generator_Select_Value_POS
) 1113:
#define
AG903_SDC_Preset_Value_DDR50_Driver_Strength_Select_Value_POS
14 1114:
#define
AG903_SDC_Preset_Value_DDR50_Driver_Strength_Select_Value_MSK
(0x3U <<
AG903_SDC_Preset_Value_DDR50_Driver_Strength_Select_Value_POS
) 1115: 1116:
#define
AG903_SDC_Host_Controller_Version_Specification_Version_Number_POS
0 1117:
#define
AG903_SDC_Host_Controller_Version_Specification_Version_Number_MSK
(0xffU <<
AG903_SDC_Host_Controller_Version_Specification_Version_Number_POS
) 1118:
#define
AG903_SDC_Host_Controller_Version_Vendor_Version_Number_POS
8 1119:
#define
AG903_SDC_Host_Controller_Version_Vendor_Version_Number_MSK
(0xffU <<
AG903_SDC_Host_Controller_Version_Vendor_Version_Number_POS
) 1120: 1121:
#define
AG903_SDC_Vendor_defined_0_p_lat_en_POS
0 1122:
#define
AG903_SDC_Vendor_defined_0_p_lat_en_MSK
(0x1UL <<
AG903_SDC_Vendor_defined_0_p_lat_en_POS
) 1123:
#define
AG903_SDC_Vendor_defined_0_p_lat_off_POS
8 1124:
#define
AG903_SDC_Vendor_defined_0_p_lat_off_MSK
(0x3fUL <<
AG903_SDC_Vendor_defined_0_p_lat_off_POS
) 1125:
#define
AG903_SDC_Vendor_defined_0_int_edge_sel_POS
16 1126:
#define
AG903_SDC_Vendor_defined_0_int_edge_sel_MSK
(0x1UL <<
AG903_SDC_Vendor_defined_0_int_edge_sel_POS
) 1127:
#define
AG903_SDC_Vendor_defined_0_NCRC_POS
24 1128:
#define
AG903_SDC_Vendor_defined_0_NCRC_MSK
(0xfUL <<
AG903_SDC_Vendor_defined_0_NCRC_POS
) 1129: 1130:
#define
AG903_SDC_Vendor_defined_1_mmc_boot_POS
0 1131:
#define
AG903_SDC_Vendor_defined_1_mmc_boot_MSK
(0x3UL <<
AG903_SDC_Vendor_defined_1_mmc_boot_POS
) 1132:
#define
AG903_SDC_Vendor_defined_1_mmc_boot_ack_en_POS
2 1133:
#define
AG903_SDC_Vendor_defined_1_mmc_boot_ack_en_MSK
(0x1UL <<
AG903_SDC_Vendor_defined_1_mmc_boot_ack_en_POS
) 1134:
#define
AG903_SDC_Vendor_defined_1_NCR_POS
8 1135:
#define
AG903_SDC_Vendor_defined_1_NCR_MSK
(0xfUL <<
AG903_SDC_Vendor_defined_1_NCR_POS
) 1136:
#define
AG903_SDC_Vendor_defined_1_NSB_POS
16 1137:
#define
AG903_SDC_Vendor_defined_1_NSB_MSK
(0x7UL <<
AG903_SDC_Vendor_defined_1_NSB_POS
) 1138:
#define
AG903_SDC_Vendor_defined_1_cmd_conflict_en_POS
24 1139:
#define
AG903_SDC_Vendor_defined_1_cmd_conflict_en_MSK
(0x1UL <<
AG903_SDC_Vendor_defined_1_cmd_conflict_en_POS
) 1140: 1141:
#define
AG903_SDC_Vendor_defined_2_clk_ctrl_sw_rst_POS
0 1142:
#define
AG903_SDC_Vendor_defined_2_clk_ctrl_sw_rst_MSK
(0x1UL <<
AG903_SDC_Vendor_defined_2_clk_ctrl_sw_rst_POS
) 1143: 1144:
#define
AG903_SDC_Vendor_defined_3_tuning_success_thres_POS
0 1145:
#define
AG903_SDC_Vendor_defined_3_tuning_success_thres_MSK
(0x1fUL <<
AG903_SDC_Vendor_defined_3_tuning_success_thres_POS
) 1146:
#define
AG903_SDC_Vendor_defined_3_crc16_error_thres_POS
8 1147:
#define
AG903_SDC_Vendor_defined_3_crc16_error_thres_MSK
(0x1fUL <<
AG903_SDC_Vendor_defined_3_crc16_error_thres_POS
) 1148:
#define
AG903_SDC_Vendor_defined_3_sd_delay_val_POS
16 1149:
#define
AG903_SDC_Vendor_defined_3_sd_delay_val_MSK
(0x1fUL <<
AG903_SDC_Vendor_defined_3_sd_delay_val_POS
) 1150:
#define
AG903_SDC_Vendor_defined_3_sd_delay_sel_bound_POS
24 1151:
#define
AG903_SDC_Vendor_defined_3_sd_delay_sel_bound_MSK
(0x1fUL <<
AG903_SDC_Vendor_defined_3_sd_delay_sel_bound_POS
) 1152: 1153:
#define
AG903_SDC_Vendor_defined_4_tuning_record_POS
0 1154:
#define
AG903_SDC_Vendor_defined_4_tuning_record_MSK
(0xffffffffUL <<
AG903_SDC_Vendor_defined_4_tuning_record_POS
) 1155: 1156:
#define
AG903_SDC_Vendor_defined_5_db_timeout_POS
0 1157:
#define
AG903_SDC_Vendor_defined_5_db_timeout_MSK
(0xfUL <<
AG903_SDC_Vendor_defined_5_db_timeout_POS
) 1158: 1159:
#define
AG903_SDC_Vendor_defined_6_hburst_incr_POS
0 1160:
#define
AG903_SDC_Vendor_defined_6_hburst_incr_MSK
(0x1UL <<
AG903_SDC_Vendor_defined_6_hburst_incr_POS
) 1161: 1162:
#define
AG903_SDC_Vendor_defined_7_ahb_resp_err_sts_POS
0 1163:
#define
AG903_SDC_Vendor_defined_7_ahb_resp_err_sts_MSK
(0x1UL <<
AG903_SDC_Vendor_defined_7_ahb_resp_err_sts_POS
) 1164: 1165:
#define
AG903_SDC_Vendor_defined_8_ahb_resp_err_sts_en_POS
0 1166:
#define
AG903_SDC_Vendor_defined_8_ahb_resp_err_sts_en_MSK
(0x1UL <<
AG903_SDC_Vendor_defined_8_ahb_resp_err_sts_en_POS
) 1167: 1168:
#define
AG903_SDC_Vendor_defined_9_ahb_resp_err_sts_POS
0 1169:
#define
AG903_SDC_Vendor_defined_9_ahb_resp_err_sts_MSK
(0x1UL <<
AG903_SDC_Vendor_defined_9_ahb_resp_err_sts_POS
) 1170: 1171:
#define
AG903_SDC_DMA_handshake_enable_dma_hsk_en_POS
0 1172:
#define
AG903_SDC_DMA_handshake_enable_dma_hsk_en_MSK
(0x1UL <<
AG903_SDC_DMA_handshake_enable_dma_hsk_en_POS
) 1173: 1174:
#define
AG903_SDC_Hardware_attributes_hw_config_POS
0 1175:
#define
AG903_SDC_Hardware_attributes_hw_config_MSK
(0x1ffUL <<
AG903_SDC_Hardware_attributes_hw_config_POS
) 1176: 1177:
#define
AG903_SDC_IP_revision_Rev_num_POS
0 1178:
#define
AG903_SDC_IP_revision_Rev_num_MSK
(0xffffffffUL <<
AG903_SDC_IP_revision_Rev_num_POS
) 1179: 1180: 1181:
#endif
1182:
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