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AG903_timreg.h

TIM Register Definition

TIM Register Definition

none

AXELL CORPORATION

2017_10_20 Auto-generated.

1: 8: 9: 13: 14: #ifndef _AG903_TIM_REGMAP_H_ 15: #define _AG903_TIM_REGMAP_H_ 16: 17: 18: #include "AG903_regmap.h" 19: 20: #ifndef __I 21: 22: #define __I volatile const 23: #endif 24: #ifndef __O 25: 26: #define __O volatile 27: #endif 28: #ifndef __IO 29: 30: #define __IO volatile 31: #endif 32: 33: 34: typedef struct { 35: 36: union { 37: __IO uint32_t CTRL; 38: 39: struct { 40: __IO uint32_t MOD : 3; 41: __IO uint32_t OS : 1; 42: } CTRL_bits; 43: }; 44: 45: union { 46: __IO uint32_t RSTTRG; 47: 48: struct { 49: __IO uint32_t EN : 2; 50: __IO uint32_t BOOT : 2; 51: __IO uint32_t RES : 2; 52: uint32_t : 2; 53: __IO uint32_t POL : 1; 54: uint32_t : 7; 55: __IO uint32_t CH : 2; 56: __IO uint32_t LO : 1; 57: uint32_t : 5; 58: __IO uint32_t EVE : 6; 59: } RSTTRG_bits; 60: }; 61: 62: union { 63: __IO uint32_t INMOD; 64: 65: struct { 66: __IO uint32_t RES : 2; 67: uint32_t : 6; 68: __IO uint32_t POL : 1; 69: uint32_t : 7; 70: __IO uint32_t CH : 2; 71: __IO uint32_t LO : 1; 72: uint32_t : 5; 73: __IO uint32_t EVE : 6; 74: } INMOD_bits; 75: }; 76: 77: union { 78: __IO uint32_t OUTMOD; 79: 80: struct { 81: __IO uint32_t MOD : 2; 82: uint32_t : 6; 83: __IO uint32_t POL : 1; 84: uint32_t : 7; 85: __IO uint32_t CH : 2; 86: uint32_t : 6; 87: __IO uint32_t OVF : 1; 88: __IO uint32_t CM : 1; 89: } OUTMOD_bits; 90: }; 91: 92: union { 93: __IO uint32_t CNT; 94: }; 95: 96: union { 97: __IO uint32_t PERIOD; 98: }; 99: 100: union { 101: __IO uint32_t MATCH; 102: }; 103: 104: union { 105: __IO uint32_t PULWID; 106: 107: struct { 108: __IO uint32_t VAL : 20; 109: } PULWID_bits; 110: }; 111: 112: union { 113: __I uint32_t STAT; 114: 115: struct { 116: __I uint32_t OVF : 1; 117: __I uint32_t CM : 1; 118: uint32_t : 14; 119: __I uint32_t DR : 1; 120: } STAT_bits; 121: }; 122: 123: union { 124: __O uint32_t CLR; 125: 126: struct { 127: __O uint32_t OVF : 1; 128: __O uint32_t CM : 1; 129: } CLR_bits; 130: }; 131: 132: __I uint32_t RESERVED1[2]; 133: 134: union { 135: __IO uint32_t INTMASK; 136: 137: struct { 138: __IO uint32_t OVF : 1; 139: __IO uint32_t CM : 1; 140: } INTMASK_bits; 141: }; 142: 143: union { 144: __IO uint32_t DMAREQ; 145: 146: struct { 147: __IO uint32_t OVF : 1; 148: __IO uint32_t CM : 1; 149: } DMAREQ_bits; 150: }; 151: 152: union { 153: __IO uint32_t TRIGGER; 154: 155: struct { 156: __IO uint32_t OVF : 1; 157: __IO uint32_t CM : 1; 158: } TRIGGER_bits; 159: }; 160: 161: 162: }AG903_TIMn_Type; 163: 164: 165: typedef struct { 166: 167: union { 168: __O uint32_t BOOTTRG; 169: 170: struct { 171: __O uint32_t CH0 : 1; 172: __O uint32_t CH1 : 1; 173: __O uint32_t CH2 : 1; 174: __O uint32_t CH3 : 1; 175: __O uint32_t CH4 : 1; 176: __O uint32_t CH5 : 1; 177: __O uint32_t CH6 : 1; 178: __O uint32_t CH7 : 1; 179: } BOOTTRG_bits; 180: }; 181: 182: 183: }AG903_TIM_Type; 184: 185: #define AG903_TIMn(ch) ((volatile AG903_TIMn_Type *)(AG903_TIM0_BASE + 0x40 * ch)) 186: #define AG903_TIMn_CTRL(ch) AG903_TIMn(ch)->CTRL 187: #define AG903_TIMn_RSTTRG(ch) AG903_TIMn(ch)->RSTTRG 188: #define AG903_TIMn_INMOD(ch) AG903_TIMn(ch)->INMOD 189: #define AG903_TIMn_OUTMOD(ch) AG903_TIMn(ch)->OUTMOD 190: #define AG903_TIMn_CNT(ch) AG903_TIMn(ch)->CNT 191: #define AG903_TIMn_PERIOD(ch) AG903_TIMn(ch)->PERIOD 192: #define AG903_TIMn_MATCH(ch) AG903_TIMn(ch)->MATCH 193: #define AG903_TIMn_PULWID(ch) AG903_TIMn(ch)->PULWID 194: #define AG903_TIMn_STAT(ch) AG903_TIMn(ch)->STAT 195: #define AG903_TIMn_CLR(ch) AG903_TIMn(ch)->CLR 196: #define AG903_TIMn_INTMASK(ch) AG903_TIMn(ch)->INTMASK 197: #define AG903_TIMn_DMAREQ(ch) AG903_TIMn(ch)->DMAREQ 198: #define AG903_TIMn_TRIGGER(ch) AG903_TIMn(ch)->TRIGGER 199: 200: #define AG903_TIM0 ((volatile AG903_TIMn_Type *) AG903_TIM0_BASE) 201: #define AG903_TIM1 ((volatile AG903_TIMn_Type *) AG903_TIM1_BASE) 202: #define AG903_TIM2 ((volatile AG903_TIMn_Type *) AG903_TIM2_BASE) 203: #define AG903_TIM3 ((volatile AG903_TIMn_Type *) AG903_TIM3_BASE) 204: #define AG903_TIM4 ((volatile AG903_TIMn_Type *) AG903_TIM4_BASE) 205: #define AG903_TIM5 ((volatile AG903_TIMn_Type *) AG903_TIM5_BASE) 206: #define AG903_TIM6 ((volatile AG903_TIMn_Type *) AG903_TIM6_BASE) 207: #define AG903_TIM7 ((volatile AG903_TIMn_Type *) AG903_TIM7_BASE) 208: #define AG903_TIM ((volatile AG903_TIM_Type *) AG903_TIM_BASE) 209: 210: 211: #define AG903_TIMn_CTRL_MOD_POS 0 212: #define AG903_TIMn_CTRL_MOD_MSK (0x7UL << AG903_TIMn_CTRL_MOD_POS) 213: #define AG903_TIMn_CTRL_OS_POS 3 214: #define AG903_TIMn_CTRL_OS_MSK (0x1UL << AG903_TIMn_CTRL_OS_POS) 215: 216: #define AG903_TIMn_RSTTRG_EN_POS 0 217: #define AG903_TIMn_RSTTRG_EN_MSK (0x3UL << AG903_TIMn_RSTTRG_EN_POS) 218: #define AG903_TIMn_RSTTRG_BOOT_POS 2 219: #define AG903_TIMn_RSTTRG_BOOT_MSK (0x3UL << AG903_TIMn_RSTTRG_BOOT_POS) 220: #define AG903_TIMn_RSTTRG_RES_POS 4 221: #define AG903_TIMn_RSTTRG_RES_MSK (0x3UL << AG903_TIMn_RSTTRG_RES_POS) 222: #define AG903_TIMn_RSTTRG_POL_POS 8 223: #define AG903_TIMn_RSTTRG_POL_MSK (0x1UL << AG903_TIMn_RSTTRG_POL_POS) 224: #define AG903_TIMn_RSTTRG_CH_POS 16 225: #define AG903_TIMn_RSTTRG_CH_MSK (0x3UL << AG903_TIMn_RSTTRG_CH_POS) 226: #define AG903_TIMn_RSTTRG_LO_POS 18 227: #define AG903_TIMn_RSTTRG_LO_MSK (0x1UL << AG903_TIMn_RSTTRG_LO_POS) 228: #define AG903_TIMn_RSTTRG_EVE_POS 24 229: #define AG903_TIMn_RSTTRG_EVE_MSK (0x3fUL << AG903_TIMn_RSTTRG_EVE_POS) 230: 231: #define AG903_TIMn_INMOD_RES_POS 0 232: #define AG903_TIMn_INMOD_RES_MSK (0x3UL << AG903_TIMn_INMOD_RES_POS) 233: #define AG903_TIMn_INMOD_POL_POS 8 234: #define AG903_TIMn_INMOD_POL_MSK (0x1UL << AG903_TIMn_INMOD_POL_POS) 235: #define AG903_TIMn_INMOD_CH_POS 16 236: #define AG903_TIMn_INMOD_CH_MSK (0x3UL << AG903_TIMn_INMOD_CH_POS) 237: #define AG903_TIMn_INMOD_LO_POS 18 238: #define AG903_TIMn_INMOD_LO_MSK (0x1UL << AG903_TIMn_INMOD_LO_POS) 239: #define AG903_TIMn_INMOD_EVE_POS 24 240: #define AG903_TIMn_INMOD_EVE_MSK (0x3fUL << AG903_TIMn_INMOD_EVE_POS) 241: 242: #define AG903_TIMn_OUTMOD_MOD_POS 0 243: #define AG903_TIMn_OUTMOD_MOD_MSK (0x3UL << AG903_TIMn_OUTMOD_MOD_POS) 244: #define AG903_TIMn_OUTMOD_POL_POS 8 245: #define AG903_TIMn_OUTMOD_POL_MSK (0x1UL << AG903_TIMn_OUTMOD_POL_POS) 246: #define AG903_TIMn_OUTMOD_CH_POS 16 247: #define AG903_TIMn_OUTMOD_CH_MSK (0x3UL << AG903_TIMn_OUTMOD_CH_POS) 248: #define AG903_TIMn_OUTMOD_OVF_POS 24 249: #define AG903_TIMn_OUTMOD_OVF_MSK (0x1UL << AG903_TIMn_OUTMOD_OVF_POS) 250: #define AG903_TIMn_OUTMOD_CM_POS 25 251: #define AG903_TIMn_OUTMOD_CM_MSK (0x1UL << AG903_TIMn_OUTMOD_CM_POS) 252: 253: #define AG903_TIMn_CNT_VAL_POS 0 254: #define AG903_TIMn_CNT_VAL_MSK (0xffffffffUL << AG903_TIMn_CNT_VAL_POS) 255: 256: #define AG903_TIMn_PERIOD_VAL_POS 0 257: #define AG903_TIMn_PERIOD_VAL_MSK (0xffffffffUL << AG903_TIMn_PERIOD_VAL_POS) 258: 259: #define AG903_TIMn_MATCH_VAL_POS 0 260: #define AG903_TIMn_MATCH_VAL_MSK (0xffffffffUL << AG903_TIMn_MATCH_VAL_POS) 261: 262: #define AG903_TIMn_PULWID_VAL_POS 0 263: #define AG903_TIMn_PULWID_VAL_MSK (0xfffffUL << AG903_TIMn_PULWID_VAL_POS) 264: 265: #define AG903_TIMn_STAT_OVF_POS 0 266: #define AG903_TIMn_STAT_OVF_MSK (0x1UL << AG903_TIMn_STAT_OVF_POS) 267: #define AG903_TIMn_STAT_CM_POS 1 268: #define AG903_TIMn_STAT_CM_MSK (0x1UL << AG903_TIMn_STAT_CM_POS) 269: #define AG903_TIMn_STAT_DR_POS 16 270: #define AG903_TIMn_STAT_DR_MSK (0x1UL << AG903_TIMn_STAT_DR_POS) 271: 272: #define AG903_TIMn_CLR_OVF_POS 0 273: #define AG903_TIMn_CLR_OVF_MSK (0x1UL << AG903_TIMn_CLR_OVF_POS) 274: #define AG903_TIMn_CLR_CM_POS 1 275: #define AG903_TIMn_CLR_CM_MSK (0x1UL << AG903_TIMn_CLR_CM_POS) 276: 277: #define AG903_TIMn_INTMASK_OVF_POS 0 278: #define AG903_TIMn_INTMASK_OVF_MSK (0x1UL << AG903_TIMn_INTMASK_OVF_POS) 279: #define AG903_TIMn_INTMASK_CM_POS 1 280: #define AG903_TIMn_INTMASK_CM_MSK (0x1UL << AG903_TIMn_INTMASK_CM_POS) 281: 282: #define AG903_TIMn_DMAREQ_OVF_POS 0 283: #define AG903_TIMn_DMAREQ_OVF_MSK (0x1UL << AG903_TIMn_DMAREQ_OVF_POS) 284: #define AG903_TIMn_DMAREQ_CM_POS 1 285: #define AG903_TIMn_DMAREQ_CM_MSK (0x1UL << AG903_TIMn_DMAREQ_CM_POS) 286: 287: #define AG903_TIMn_TRIGGER_OVF_POS 0 288: #define AG903_TIMn_TRIGGER_OVF_MSK (0x1UL << AG903_TIMn_TRIGGER_OVF_POS) 289: #define AG903_TIMn_TRIGGER_CM_POS 1 290: #define AG903_TIMn_TRIGGER_CM_MSK (0x1UL << AG903_TIMn_TRIGGER_CM_POS) 291: 292: #define AG903_TIM_BOOTTRG_CH0_POS 0 293: #define AG903_TIM_BOOTTRG_CH0_MSK (0x1UL << AG903_TIM_BOOTTRG_CH0_POS) 294: #define AG903_TIM_BOOTTRG_CH1_POS 1 295: #define AG903_TIM_BOOTTRG_CH1_MSK (0x1UL << AG903_TIM_BOOTTRG_CH1_POS) 296: #define AG903_TIM_BOOTTRG_CH2_POS 2 297: #define AG903_TIM_BOOTTRG_CH2_MSK (0x1UL << AG903_TIM_BOOTTRG_CH2_POS) 298: #define AG903_TIM_BOOTTRG_CH3_POS 3 299: #define AG903_TIM_BOOTTRG_CH3_MSK (0x1UL << AG903_TIM_BOOTTRG_CH3_POS) 300: #define AG903_TIM_BOOTTRG_CH4_POS 4 301: #define AG903_TIM_BOOTTRG_CH4_MSK (0x1UL << AG903_TIM_BOOTTRG_CH4_POS) 302: #define AG903_TIM_BOOTTRG_CH5_POS 5 303: #define AG903_TIM_BOOTTRG_CH5_MSK (0x1UL << AG903_TIM_BOOTTRG_CH5_POS) 304: #define AG903_TIM_BOOTTRG_CH6_POS 6 305: #define AG903_TIM_BOOTTRG_CH6_MSK (0x1UL << AG903_TIM_BOOTTRG_CH6_POS) 306: #define AG903_TIM_BOOTTRG_CH7_POS 7 307: #define AG903_TIM_BOOTTRG_CH7_MSK (0x1UL << AG903_TIM_BOOTTRG_CH7_POS) 308: 309: #endif 310:
名前 
説明 
TIM Base Address 
TIMBOOTTRG CH0-bit mask 
TIMBOOTTRG CH0-bit position 
TIMBOOTTRG CH1-bit mask 
TIMBOOTTRG CH1-bit position 
TIMBOOTTRG CH2-bit mask 
TIMBOOTTRG CH2-bit position 
TIMBOOTTRG CH3-bit mask 
TIMBOOTTRG CH3-bit position 
TIMBOOTTRG CH4-bit mask 
TIMBOOTTRG CH4-bit position 
TIMBOOTTRG CH5-bit mask 
TIMBOOTTRG CH5-bit position 
TIMBOOTTRG CH6-bit mask 
TIMBOOTTRG CH6-bit position 
TIMBOOTTRG CH7-bit mask 
TIMBOOTTRG CH7-bit position 
TIMn Base Address 
TIMn Base Address 
TIMn Base Address 
TIMn Base Address 
TIMn Base Address 
TIMn Base Address 
TIMn Base Address 
TIMn Base Address 
TIMn Base Address (n=0..7) 
TIMnCLR Address (n=0..7) 
TIMnCLR CM-bit mask 
TIMnCLR CM-bit position 
TIMnCLR OVF-bit mask 
TIMnCLR OVF-bit position 
TIMnCNT Address (n=0..7) 
TIMnCNT VAL-bit mask 
TIMnCNT VAL-bit position 
TIMnCTRL Address (n=0..7) 
TIMnCTRL MOD-bit mask 
TIMnCTRL MOD-bit position 
TIMnCTRL OS-bit mask 
TIMnCTRL OS-bit position 
TIMnDMAREQ Address (n=0..7) 
TIMnDMAREQ CM-bit mask 
TIMnDMAREQ CM-bit position 
TIMnDMAREQ OVF-bit mask 
TIMnDMAREQ OVF-bit position 
TIMnINMOD Address (n=0..7) 
TIMnINMOD CH-bit mask 
TIMnINMOD CH-bit position 
TIMnINMOD EVE-bit mask 
TIMnINMOD EVE-bit position 
TIMnINMOD LO-bit mask 
TIMnINMOD LO-bit position 
TIMnINMOD POL-bit mask 
TIMnINMOD POL-bit position 
TIMnINMOD RES-bit mask 
TIMnINMOD RES-bit position 
TIMnINTMASK Address (n=0..7) 
TIMnINTMASK CM-bit mask 
TIMnINTMASK CM-bit position 
TIMnINTMASK OVF-bit mask 
TIMnINTMASK OVF-bit position 
TIMnMATCH Address (n=0..7) 
TIMnMATCH VAL-bit mask 
TIMnMATCH VAL-bit position 
TIMnOUTMOD Address (n=0..7) 
TIMnOUTMOD CH-bit mask 
TIMnOUTMOD CH-bit position 
TIMnOUTMOD CM-bit mask 
TIMnOUTMOD CM-bit position 
TIMnOUTMOD MOD-bit mask 
TIMnOUTMOD MOD-bit position 
TIMnOUTMOD OVF-bit mask 
TIMnOUTMOD OVF-bit position 
TIMnOUTMOD POL-bit mask 
TIMnOUTMOD POL-bit position 
TIMnPERIOD Address (n=0..7) 
TIMnPERIOD VAL-bit mask 
TIMnPERIOD VAL-bit position 
TIMnPULWID Address (n=0..7) 
TIMnPULWID VAL-bit mask 
TIMnPULWID VAL-bit position 
TIMnRSTTRG Address (n=0..7) 
TIMnRSTTRG BOOT-bit mask 
TIMnRSTTRG BOOT-bit position 
TIMnRSTTRG CH-bit mask 
TIMnRSTTRG CH-bit position 
TIMnRSTTRG EN-bit mask 
TIMnRSTTRG EN-bit position 
TIMnRSTTRG EVE-bit mask 
TIMnRSTTRG EVE-bit position 
TIMnRSTTRG LO-bit mask 
TIMnRSTTRG LO-bit position 
TIMnRSTTRG POL-bit mask 
TIMnRSTTRG POL-bit position 
TIMnRSTTRG RES-bit mask 
TIMnRSTTRG RES-bit position 
TIMnSTAT Address (n=0..7) 
TIMnSTAT CM-bit mask 
TIMnSTAT CM-bit position 
TIMnSTAT DR-bit mask 
TIMnSTAT DR-bit position 
TIMnSTAT OVF-bit mask 
TIMnSTAT OVF-bit position 
TIMnTRIGGER Address (n=0..7) 
TIMnTRIGGER CM-bit mask 
TIMnTRIGGER CM-bit position 
TIMnTRIGGER OVF-bit mask 
TIMnTRIGGER OVF-bit position 
名前 
説明 
TIM Type 
TIMn Type 
Copyright (c) 2017-2025 Axell Corporation. All rights reserved.