1:
10:
11:
15:
16:
17:
#include "AG903_errno.h"
18:
#include "AG903_intno.h"
19:
#include "i2c/i2cmgr.h"
20:
#include "i2c/i2cprm.h"
21:
#include "i2c.h"
22:
#include "int/intmgr.h"
23:
24:
25:
typedef void (*AG903_I2CMgrIntHdr)(
void);
26:
27:
typedef union _AG903_I2CMgrArg{
28:
AG903_I2CMgrWriteParam wr;
29:
AG903_I2CMgrReadParam rd;
30: } AG903_I2CMgrArg;
31:
32:
typedef struct _AG903_I2CMgrQue{
33: AG903_I2CMgrArg arg;
34: uint32_t proc;
35: uint32_t hdlnum;
36: } AG903_I2CMgrQue;
37:
38:
typedef struct _AG903_I2CMgrQueStat{
39: AG903_I2CMgrQue que[
AG903_I2C_QUENUM];
40: uint32_t wp;
41: uint32_t rp;
42: } AG903_I2CMgrQueStat;
43:
44:
typedef struct _AG903_I2CMgrChStat{
45: AG903_I2CMgrArg arg;
46: uint32_t hdlnum;
47: uint32_t stat;
48: uint32_t sequence;
49: uint32_t cnt;
50: int32_t hdrid;
51: } AG903_I2CMgrChStat;
52:
53:
typedef struct _AG903_I2CMgrHandleStat{
54:
AG903_I2CMgrClbk clbk;
55: uint32_t stat;
56: uint8_t lock;
57: uint8_t reserve[3];
58: } AG903_I2CMgrHandleStat;
59:
60:
static AG903_I2CMgrChStat I2cChStat[
AG903_I2C_CH_NUM];
61:
static AG903_I2CMgrHandleStat I2cHandleStat[
AG903_I2C_CH_NUM][
AG903_I2C_HANDLE_NUM];
62:
static AG903_I2CMgrQueStat I2cQue[
AG903_I2C_CH_NUM];
63:
64:
static void I2CMgr_InitState(uint8_t ch);
65:
static void I2CMgr_MainProcess(uint8_t ch);
66:
static int32_t I2CMgr_ExecuteProcess(uint8_t ch, uint32_t hdlnum, uint32_t proc, AG903_I2CMgrArg* arg);
67:
static int32_t I2CMgr_MasterWrite(uint8_t ch, uint32_t hdlnum,
AG903_I2CMgrWriteParam* param);
68:
static int32_t I2CMgr_MasterRead(uint8_t ch, uint32_t hdlnum,
AG903_I2CMgrReadParam* param);
69:
static int32_t I2CMgr_SlaveWrite(uint8_t ch, uint32_t hdlnum,
AG903_I2CMgrWriteParam* param);
70:
static int32_t I2CMgr_SlaveRead(uint8_t ch, uint32_t hdlnum,
AG903_I2CMgrReadParam* param);
71:
static int32_t I2CMgr_SetFrequency(uint8_t ch, uint32_t freq);
72:
static int32_t I2CMgr_SetClock(uint8_t ch, uint32_t cdr, uint16_t tsr, uint8_t gsr);
73:
static int32_t I2CMgr_CheckHandle(
AG903_I2CMgrHandle* handle, uint8_t* ch, uint32_t* hdlnum);
74:
static int32_t I2CMgr_SetQue(uint8_t ch, AG903_I2CMgrQue* que);
75:
static int32_t I2CMgr_GetQue(uint8_t ch, AG903_I2CMgrQue* que);
76:
static uint32_t I2CMgr_GetNextQuePoint(uint32_t current);
77:
static int32_t I2CMgr_GetQueCount(uint8_t ch, uint32_t* count);
78:
static void I2CMgr_Inthdr0(
void);
79:
static void I2CMgr_Inthdr1(
void);
80:
static void I2CMgr_IntProcess(uint8_t ch);
81:
static int32_t I2CMgr_IntMasterWrite(uint8_t ch, uint32_t* event);
82:
static int32_t I2CMgr_IntMasterRead(uint8_t ch, uint32_t* event);
83:
static int32_t I2CMgr_IntSlaveWrite(uint8_t ch, uint32_t* event);
84:
static int32_t I2CMgr_IntSlaveRead(uint8_t ch, uint32_t* event);
85:
86:
87:
static const AG903_I2CMgrIntHdr I2cIntHdr[
AG903_I2C_CH_NUM] =
88: { I2CMgr_Inthdr0, I2CMgr_Inthdr1 };
89:
90:
102: int32_t
AG903_I2CMgrInit(uint8_t ch)
103: {
104:
AG903_INTMgrHdrPrm inthdr;
105: int32_t retval =
AG903_ENONE;
106: int32_t hdrid;
107:
108:
if(
AG903_I2C_CH_NUM <= ch) {
109:
return -
AG903_EINVAL;
110: }
111:
112: I2CMgr_InitState(ch);
113:
114:
if(0 >= I2cChStat[ch].hdrid) {
115: inthdr.atr =
AG903_INT_HLNG;
116: inthdr.intno =
AG903_IRQ44_IIC0+ch;
117: inthdr.func = (
void*)I2cIntHdr[ch];
118: hdrid =
AG903_INTMgrSetHandler(&inthdr);
119:
if(0 >= hdrid) {
120:
return -
AG903_EFAULT;
121: }
122: I2cChStat[ch].hdrid = hdrid;
123: }
124:
125:
AG903_INTMgrEnableInt(
AG903_IRQ44_IIC0+ch);
126:
127: retval = I2CMgr_SetFrequency(ch,
AG903_I2C_DFLT_SCL);
128:
129:
return retval;
130: }
131:
132:
143: int32_t
AG903_I2CMgrSetClock(uint8_t ch,
AG903_I2CMgrClkPrm* param)
144: {
145: int32_t retval =
AG903_ENONE;
146:
147:
if( (
AG903_I2C_CH_NUM <= ch) ||
148: (NULL == param) ) {
149:
return -
AG903_EINVAL;
150: }
151:
152: retval = I2CMgr_SetClock(ch, param->cdr_val, param->tsr_val, param->gsr_val);
153:
154:
return retval;
155: }
156:
157:
166: int32_t
AG903_I2CMgrSetSlaveAddress(uint8_t ch, uint16_t saddr)
167: {
168: int32_t retval =
AG903_ENONE;
169:
170:
if( (
AG903_I2C_CH_NUM <= ch) ||
171: (0xFC00 & saddr) ){
172:
return -
AG903_EINVAL;
173: }
174:
175:
AG903_I2CPrmSetSlaveAddr(ch, saddr);
176:
177:
return retval;
178: }
179:
180:
193: int32_t
AG903_I2CMgrGetHandle(uint8_t ch,
AG903_I2CMgrHandle** handle)
194: {
195: int32_t retval =
AG903_ENONE;
196: uint32_t loop;
197:
198:
if( (
AG903_I2C_CH_NUM <= ch) ||
199: (NULL == handle) ) {
200:
return -
AG903_EINVAL;
201: }
202:
203:
for(loop=0; loop<
AG903_I2C_HANDLE_NUM; loop++) {
204:
if(
false == I2cHandleStat[ch][loop].lock) {
205: I2cHandleStat[ch][loop].lock =
true;
206:
break;
207: }
208: }
209:
if(
AG903_I2C_HANDLE_NUM <= loop) {
210:
return -
AG903_EBUSY;
211: }
212:
213: I2cHandleStat[ch][loop].stat = AG903_I2C_HANDLE_IDLE;
214: I2cHandleStat[ch][loop].clbk = NULL;
215:
216: (*handle) = (
AG903_I2CMgrHandle*)&I2cHandleStat[ch][loop];
217:
218:
return retval;
219: }
220:
221:
230: int32_t
AG903_I2CMgrReleaseHandle(
AG903_I2CMgrHandle* handle)
231: {
232: int32_t retval =
AG903_ENONE;
233: int32_t result;
234: uint32_t hdlnum;
235: uint8_t ch;
236:
237: result = I2CMgr_CheckHandle(handle, &ch, &hdlnum);
238:
if(
AG903_ENONE != result) {
239:
return -
AG903_EINVAL;
240: }
241:
if(AG903_I2C_HANDLE_IDLE != I2cHandleStat[ch][hdlnum].stat) {
242:
return -
AG903_EBUSY;
243: }
244:
245: I2cHandleStat[ch][hdlnum].clbk = NULL;
246: I2cHandleStat[ch][hdlnum].lock =
false;
247:
248:
return retval;
249: }
250:
251:
260: int32_t
AG903_I2CMgrSetCallback(
AG903_I2CMgrHandle* handle,
AG903_I2CMgrClbk clbk)
261: {
262: int32_t retval =
AG903_ENONE;
263: int32_t result;
264: uint32_t hdlnum;
265: uint8_t ch;
266:
267: result = I2CMgr_CheckHandle(handle, &ch, &hdlnum);
268:
if(
AG903_ENONE != result) {
269:
return -
AG903_EINVAL;
270: }
271:
272: I2cHandleStat[ch][hdlnum].clbk = clbk;
273:
274:
return retval;
275: }
276:
277:
291: int32_t
AG903_I2CMgrMasterWrite(
AG903_I2CMgrHandle* handle,
AG903_I2CMgrWriteParam* param)
292: {
293: AG903_I2CMgrQue que;
294: int32_t retval =
AG903_ENONE;
295: int32_t result;
296: uint32_t hdlnum;
297: uint8_t ch;
298:
299: result = I2CMgr_CheckHandle(handle, &ch, &hdlnum);
300:
if(
AG903_ENONE != result) {
301:
return -
AG903_EINVAL;
302: }
303:
if(NULL == param) {
304:
return -
AG903_EINVAL;
305: }
306:
if( (NULL == param->buf) ||
307: (0 == param->size) ) {
308:
return -
AG903_EINVAL;
309: }
310:
if(0xFF00 & param->addr) {
311:
if( (
AG903_I2C_10BITADDR_SIG != (param->addr>>11)) ||
312: (0x0100 & param->addr) ) {
313:
return -
AG903_EINVAL;
314: }
315: }
316:
else {
317:
if(0x0001 & param->addr) {
318:
return -
AG903_EINVAL;
319: }
320: }
321:
322: que.proc = AG903_I2C_PROC_MASTER_WRITE;
323: que.hdlnum = hdlnum;
324: que.arg.wr = (*param);
325: retval = I2CMgr_SetQue(ch, &que);
326:
if(
AG903_ENONE == retval) {
327: I2cHandleStat[ch][hdlnum].stat = AG903_I2C_HANDLE_QUEUING;
328: I2CMgr_MainProcess(ch);
329: }
330:
331:
return retval;
332: }
333:
334:
345: int32_t
AG903_I2CMgrMasterRead(
AG903_I2CMgrHandle* handle,
AG903_I2CMgrReadParam* param)
346: {
347: AG903_I2CMgrQue que;
348: int32_t retval =
AG903_ENONE;
349: int32_t result;
350: uint32_t hdlnum;
351: uint8_t ch;
352:
353: result = I2CMgr_CheckHandle(handle, &ch, &hdlnum);
354:
if(
AG903_ENONE != result) {
355:
return -
AG903_EINVAL;
356: }
357:
if(NULL == param) {
358:
return -
AG903_EINVAL;
359: }
360:
if( (NULL == param->buf) ||
361: (0 == param->size) ) {
362:
return -
AG903_EINVAL;
363: }
364:
if(0xFF00 & param->addr) {
365:
if( (
AG903_I2C_10BITADDR_SIG != (param->addr>>11)) ||
366: (0x0100 & ~param->addr) ) {
367:
return -
AG903_EINVAL;
368: }
369: }
370:
else {
371:
if(0x0001 & ~param->addr) {
372:
return -
AG903_EINVAL;
373: }
374: }
375:
376: que.proc = AG903_I2C_PROC_MASTER_READ;
377: que.hdlnum = hdlnum;
378: que.arg.rd = (*param);
379: retval = I2CMgr_SetQue(ch, &que);
380:
if(
AG903_ENONE == retval) {
381: I2cHandleStat[ch][hdlnum].stat = AG903_I2C_HANDLE_QUEUING;
382: I2CMgr_MainProcess(ch);
383: }
384:
385:
return retval;
386: }
387:
388:
400: int32_t
AG903_I2CMgrSlaveWrite(
AG903_I2CMgrHandle* handle, uint8_t* buf, uint32_t size)
401: {
402: AG903_I2CMgrQue que;
403: int32_t retval =
AG903_ENONE;
404: int32_t result;
405: uint32_t hdlnum;
406: uint8_t ch;
407:
408: result = I2CMgr_CheckHandle(handle, &ch, &hdlnum);
409:
if(
AG903_ENONE != result) {
410:
return -
AG903_EINVAL;
411: }
412:
if((NULL == buf) || (0 == size)) {
413:
return -
AG903_EINVAL;
414: }
415:
416: que.proc = AG903_I2C_PROC_SLAVE_WRITE;
417: que.hdlnum = hdlnum;
418: que.arg.wr.buf = buf;
419: que.arg.wr.size = size;
420: que.arg.wr.addr = 0;
421: retval = I2CMgr_SetQue(ch, &que);
422:
if(
AG903_ENONE == retval) {
423: I2cHandleStat[ch][hdlnum].stat = AG903_I2C_HANDLE_QUEUING;
424: I2CMgr_MainProcess(ch);
425: }
426:
427:
return retval;
428: }
429:
430:
442: int32_t
AG903_I2CMgrSlaveRead(
AG903_I2CMgrHandle* handle, uint8_t* buf, uint32_t size)
443: {
444: AG903_I2CMgrQue que;
445: int32_t retval =
AG903_ENONE;
446: int32_t result;
447: uint32_t hdlnum;
448: uint8_t ch;
449:
450: result = I2CMgr_CheckHandle(handle, &ch, &hdlnum);
451:
if(
AG903_ENONE != result) {
452:
return -
AG903_EINVAL;
453: }
454:
if((NULL == buf) || (0 == size)) {
455:
return -
AG903_EINVAL;
456: }
457:
458: que.proc = AG903_I2C_PROC_SLAVE_READ;
459: que.hdlnum = hdlnum;
460: que.arg.wr.buf = buf;
461: que.arg.wr.size = size;
462: que.arg.wr.addr = 0;
463: retval = I2CMgr_SetQue(ch, &que);
464:
if(
AG903_ENONE == retval) {
465: I2cHandleStat[ch][hdlnum].stat = AG903_I2C_HANDLE_QUEUING;
466: I2CMgr_MainProcess(ch);
467: }
468:
469:
return retval;
470: }
471:
472:
481: int32_t
AG903_I2CMgrReset(
AG903_I2CMgrHandle* handle)
482: {
483: int32_t retval =
AG903_ENONE;
484: int32_t result;
485: uint32_t hdlnum;
486: uint32_t status;
487: uint32_t loop;
488: uint8_t ch;
489:
490: result = I2CMgr_CheckHandle(handle, &ch, &hdlnum);
491:
if(
AG903_ENONE != result) {
492:
return -
AG903_EINVAL;
493: }
494:
495:
AG903_I2CPrmResetController(ch);
496:
497: I2cQue[ch].wp = 0;
498: I2cQue[ch].rp = 0;
499:
500: I2cChStat[ch].stat = AG903_I2C_CH_IDLE;
501:
for(loop=0; loop<
AG903_I2C_HANDLE_NUM; loop++) {
502: I2cHandleStat[ch][loop].stat = AG903_I2C_HANDLE_IDLE;
503: }
504:
505:
AG903_I2CPrmGetStatus(ch, &status);
506: retval = I2CMgr_SetFrequency(ch,
AG903_I2C_DFLT_SCL);
507:
508:
return retval;
509: }
510:
511:
512:
521: int32_t
AG903_I2CMgrGetQueCount(
AG903_I2CMgrHandle* handle, uint32_t* count)
522: {
523: int32_t retval =
AG903_ENONE;
524: int32_t result;
525: uint32_t hdlnum;
526: uint8_t ch;
527:
528: result = I2CMgr_CheckHandle(handle, &ch, &hdlnum);
529:
if(
AG903_ENONE != result) {
530:
return -
AG903_EINVAL;
531: }
532:
if(NULL == count) {
533:
return -
AG903_EINVAL;
534: }
535:
536: retval = I2CMgr_GetQueCount(ch, count);
537:
538:
return retval;
539: }
540:
541:
542:
546:
static void I2CMgr_InitState(uint8_t ch)
547: {
548: uint32_t loop;
549:
550: I2cChStat[ch].hdlnum = 0;
551: I2cChStat[ch].stat = AG903_I2C_CH_IDLE;
552: I2cChStat[ch].sequence = AG903_I2C_SEQ_NONE;
553: I2cChStat[ch].cnt = 0;
554: I2cQue[ch].wp = 0;
555: I2cQue[ch].rp = 0;
556:
for(loop=0; loop<
AG903_I2C_HANDLE_NUM; loop++) {
557: I2cHandleStat[ch][loop].clbk = NULL;
558: I2cHandleStat[ch][loop].stat = AG903_I2C_HANDLE_IDLE;
559: I2cHandleStat[ch][loop].lock =
false;
560: }
561:
562:
return;
563: }
564:
565:
569:
static void I2CMgr_MainProcess(uint8_t ch)
570: {
571: AG903_I2CMgrQue que;
572: int32_t result;
573:
574:
if(AG903_I2C_CH_IDLE != I2cChStat[ch].stat) {
575:
return;
576: }
577:
578: result = I2CMgr_GetQue(ch, &que);
579:
if(
AG903_ENONE != result) {
580:
return;
581: }
582:
583: I2cHandleStat[ch][que.hdlnum].stat = AG903_I2C_HANDLE_EXECUTE;
584: result = I2CMgr_ExecuteProcess(ch, que.hdlnum, que.proc, &que.arg);
585:
if(
AG903_ENONE != result) {
586: I2cHandleStat[ch][que.hdlnum].stat = AG903_I2C_HANDLE_IDLE;
587: }
588:
589:
return;
590: }
591:
592:
599:
static int32_t I2CMgr_ExecuteProcess(uint8_t ch, uint32_t hdlnum, uint32_t proc, AG903_I2CMgrArg* arg)
600: {
601: int32_t retval =
AG903_ENONE;
602:
603:
switch(proc) {
604:
case AG903_I2C_PROC_MASTER_WRITE:
605: retval = I2CMgr_MasterWrite(ch, hdlnum, &arg->wr);
606:
break;
607:
case AG903_I2C_PROC_MASTER_READ:
608: retval = I2CMgr_MasterRead(ch, hdlnum, &arg->rd);
609:
break;
610:
case AG903_I2C_PROC_SLAVE_WRITE:
611: retval = I2CMgr_SlaveWrite(ch, hdlnum, &arg->wr);
612:
break;
613:
case AG903_I2C_PROC_SLAVE_READ:
614: retval = I2CMgr_SlaveRead(ch, hdlnum, &arg->rd);
615:
break;
616:
default:
617:
618: retval = -
AG903_EINVAL;
619:
break;
620: }
621:
622:
return retval;
623: }
624:
625:
631:
static int32_t I2CMgr_MasterWrite(uint8_t ch, uint32_t hdlnum,
AG903_I2CMgrWriteParam* param)
632: {
633: int32_t retval =
AG903_ENONE;
634:
635:
if( (
AG903_I2C_CH_NUM <= ch) ||
636: (
AG903_I2C_HANDLE_NUM <= hdlnum) ||
637: (NULL == param) ) {
638:
return -
AG903_EINVAL;
639: }
640:
641:
if(AG903_I2C_CH_IDLE != I2cChStat[ch].stat) {
642:
return -
AG903_EBUSY;
643: }
644:
645: I2cChStat[ch].stat = AG903_I2C_CH_MASTER_WRITE;
646: I2cChStat[ch].arg.wr = (*param);
647: I2cChStat[ch].cnt = 0;
648: I2cChStat[ch].hdlnum = hdlnum;
649:
if(0xFF00 & param->addr) {
650: I2cChStat[ch].sequence = AG903_I2C_SEQ_SND_SADDR_H;
651:
AG903_I2CPrmSetExtAddrMode(ch);
652:
AG903_I2CPrmWriteData(ch, (uint8_t)(I2cChStat[ch].arg.wr.addr>>8));
653: }
654:
else {
655: I2cChStat[ch].sequence = AG903_I2C_SEQ_SND_SADDR_L;
656:
AG903_I2CPrmClearExtAddrMode(ch);
657:
AG903_I2CPrmWriteData(ch, (uint8_t)(I2cChStat[ch].arg.wr.addr));
658: }
659:
AG903_I2CPrmClearControl(ch, (
AG903_I2C_CR_STOP_BIT|
AG903_I2C_CR_ACKNACK_BIT));
660:
AG903_I2CPrmSetControl(ch,
AG903_I2C_CR_ALLINT_BIT|
AG903_I2C_CR_I2CEN_BIT|
AG903_I2C_CR_SCLEN_BIT|
661:
AG903_I2C_CR_START_BIT|
AG903_I2C_CR_TBEN_BIT);
662:
663:
return retval;
664: }
665:
666:
672:
static int32_t I2CMgr_MasterRead(uint8_t ch, uint32_t hdlnum,
AG903_I2CMgrReadParam* param)
673: {
674: int32_t retval =
AG903_ENONE;
675:
676:
if( (
AG903_I2C_CH_NUM <= ch) ||
677: (
AG903_I2C_HANDLE_NUM <= hdlnum) ||
678: (NULL == param) ) {
679:
return -
AG903_EINVAL;
680: }
681:
682:
if(AG903_I2C_CH_IDLE != I2cChStat[ch].stat) {
683:
return -
AG903_EBUSY;
684: }
685:
686: I2cChStat[ch].stat = AG903_I2C_CH_MASTER_READ;
687: I2cChStat[ch].arg.rd = (*param);
688: I2cChStat[ch].cnt = 0;
689: I2cChStat[ch].hdlnum = hdlnum;
690:
if(0xFF00 & param->addr) {
691: I2cChStat[ch].sequence = AG903_I2C_SEQ_SND_SADDR_H;
692:
AG903_I2CPrmSetExtAddrMode(ch);
693:
AG903_I2CPrmWriteData(ch, (uint8_t)(I2cChStat[ch].arg.wr.addr>>8));
694: }
695:
else {
696: I2cChStat[ch].sequence = AG903_I2C_SEQ_SND_SADDR_L;
697:
AG903_I2CPrmClearExtAddrMode(ch);
698:
AG903_I2CPrmWriteData(ch, (uint8_t)(I2cChStat[ch].arg.wr.addr));
699: }
700:
AG903_I2CPrmClearControl(ch,
AG903_I2C_CR_STOP_BIT|
AG903_I2C_CR_ACKNACK_BIT);
701:
AG903_I2CPrmSetControl(ch,
AG903_I2C_CR_ALLINT_BIT|
AG903_I2C_CR_I2CEN_BIT|
AG903_I2C_CR_SCLEN_BIT|
702:
AG903_I2C_CR_START_BIT|
AG903_I2C_CR_TBEN_BIT);
703:
704:
return retval;
705: }
706:
707:
713:
static int32_t I2CMgr_SlaveWrite(uint8_t ch, uint32_t hdlnum,
AG903_I2CMgrWriteParam* param)
714: {
715: int32_t retval =
AG903_ENONE;
716:
717:
if( (
AG903_I2C_CH_NUM <= ch) ||
718: (
AG903_I2C_HANDLE_NUM <= hdlnum) ||
719: (NULL == param) ) {
720:
return -
AG903_EINVAL;
721: }
722:
723:
if(AG903_I2C_CH_IDLE != I2cChStat[ch].stat) {
724:
return -
AG903_EBUSY;
725: }
726:
727: I2cChStat[ch].stat = AG903_I2C_CH_SLAVE_WRITE;
728: I2cChStat[ch].arg.wr = (*param);
729: I2cChStat[ch].cnt = 0;
730: I2cChStat[ch].hdlnum = hdlnum;
731: I2cChStat[ch].sequence = AG903_I2C_SEQ_RCV_SADDR;
732:
733:
AG903_I2CPrmClearControl(ch,
AG903_I2C_CR_SCLEN_BIT|
AG903_I2C_CR_ACKNACK_BIT);
734:
AG903_I2CPrmSetControl(ch,
AG903_I2C_CR_ALLINT_BIT|
AG903_I2C_CR_I2CEN_BIT);
735:
736:
return retval;
737: }
738:
739:
745:
static int32_t I2CMgr_SlaveRead(uint8_t ch, uint32_t hdlnum,
AG903_I2CMgrReadParam* param)
746: {
747: int32_t retval =
AG903_ENONE;
748:
749:
if( (
AG903_I2C_CH_NUM <= ch) ||
750: (
AG903_I2C_HANDLE_NUM <= hdlnum) ||
751: (NULL == param) ) {
752:
return -
AG903_EINVAL;
753: }
754:
755:
if(AG903_I2C_CH_IDLE != I2cChStat[ch].stat) {
756:
return -
AG903_EBUSY;
757: }
758:
759: I2cChStat[ch].stat = AG903_I2C_CH_SLAVE_READ;
760: I2cChStat[ch].arg.rd = (*param);
761: I2cChStat[ch].cnt = 0;
762: I2cChStat[ch].hdlnum = hdlnum;
763: I2cChStat[ch].sequence = AG903_I2C_SEQ_RCV_SADDR;
764:
765:
AG903_I2CPrmClearControl(ch,
AG903_I2C_CR_SCLEN_BIT);
766:
AG903_I2CPrmSetControl(ch,
AG903_I2C_CR_ALLINT_BIT|
AG903_I2C_CR_I2CEN_BIT|
AG903_I2C_CR_ACKNACK_BIT);
767:
768:
return retval;
769: }
770:
771:
776:
static int32_t I2CMgr_SetFrequency(uint8_t ch, uint32_t freq)
777: {
778: int32_t retval =
AG903_ENONE;
779: int32_t val;
780: int32_t cdr;
781:
782:
if(
AG903_I2C_CH_NUM <= ch) {
783:
return -
AG903_EINVAL;
784: }
785:
786: val = (
AG903_I2C_DFLT_GSR >> 1);
787: cdr = ((
AG903_I2C_CLK >> 1) / freq) - (2 + val);
788:
789: retval = I2CMgr_SetClock(ch, cdr,
AG903_I2C_DFLT_TSR,
AG903_I2C_DFLT_GSR);
790:
791:
return retval;
792: }
793:
794:
801:
static int32_t I2CMgr_SetClock(uint8_t ch, uint32_t cdr, uint16_t tsr, uint8_t gsr)
802: {
803:
if( (
AG903_I2C_CH_NUM <= ch) ||
804: (0 >= tsr) ||
805: (0xFC00 & tsr) ||
806: (0xF0 & gsr) ||
807: (cdr <= (3U+gsr+tsr)) ) {
808:
return -
AG903_EINVAL;
809: }
810:
811:
AG903_I2CPrmSetClockDivision(ch, cdr);
812:
AG903_I2CPrmSetGlitchSuppression(ch, tsr, gsr);
813:
814:
return AG903_ENONE;
815: }
816:
817:
823:
static int32_t I2CMgr_CheckHandle(
AG903_I2CMgrHandle* handle, uint8_t* ch, uint32_t* hdlnum)
824: {
825: int32_t retval =
AG903_ENONE;
826: uint32_t val;
827: uint32_t get_num;
828: uint32_t get_ch;
829:
830: val = ((uint32_t)handle - (uint32_t)I2cHandleStat) /
sizeof(AG903_I2CMgrHandleStat);
831: get_ch = val /
AG903_I2C_HANDLE_NUM;
832: get_num = val %
AG903_I2C_HANDLE_NUM;
833:
834:
if( (
AG903_I2C_CH_NUM <= get_ch) ||
835: (&I2cHandleStat[get_ch][get_num] != (AG903_I2CMgrHandleStat*)handle) ) {
836:
return -
AG903_EINVAL;
837: }
838:
839: (*ch) = (uint8_t)get_ch;
840: (*hdlnum) = get_num;
841:
842:
return retval;
843: }
844:
845:
850:
static int32_t I2CMgr_SetQue(uint8_t ch, AG903_I2CMgrQue* que)
851: {
852: int32_t retval =
AG903_ENONE;
853: uint32_t next_wp;
854:
855:
if( (
AG903_I2C_CH_NUM <= ch) ||
856: (NULL == que) ){
857:
return -
AG903_EINVAL;
858: }
859:
860:
if(1 >=
AG903_I2C_QUENUM) {
861:
if(0 < I2cQue[ch].wp) {
862: retval = -
AG903_EBUSY;
863: }
864:
else {
865: I2cQue[ch].que[0] = (*que);
866: I2cQue[ch].wp++;
867: }
868: }
869:
else {
870: next_wp = I2CMgr_GetNextQuePoint(I2cQue[ch].wp);
871:
if(next_wp == I2cQue[ch].rp) {
872: retval = -
AG903_EBUSY;
873: }
874:
else {
875: I2cQue[ch].que[next_wp] = (*que);
876: I2cQue[ch].wp = next_wp;
877: }
878: }
879:
880:
return retval;
881: }
882:
883:
888:
static int32_t I2CMgr_GetQue(uint8_t ch, AG903_I2CMgrQue* que)
889: {
890: int32_t retval =
AG903_ENONE;
891: uint32_t next_rp;
892:
893:
if( (
AG903_I2C_CH_NUM <= ch) ||
894: (NULL == que) ){
895:
return -
AG903_EINVAL;
896: }
897:
898:
if(1 >=
AG903_I2C_QUENUM) {
899:
if(0 >= I2cQue[ch].wp) {
900: retval = -
AG903_ENOMSG;
901: }
902:
else {
903: (*que) = I2cQue[ch].que[0];
904: I2cQue[ch].wp--;
905: }
906: }
907:
else {
908:
if(I2cQue[ch].wp == I2cQue[ch].rp) {
909: retval = -
AG903_ENOMSG;
910: }
911:
else {
912: next_rp = I2CMgr_GetNextQuePoint(I2cQue[ch].rp);
913: (*que) = I2cQue[ch].que[next_rp];
914: I2cQue[ch].rp = next_rp;
915: }
916: }
917:
918:
return retval;
919: }
920:
921:
926:
static uint32_t I2CMgr_GetNextQuePoint(uint32_t current)
927: {
928: uint32_t next;
929:
930: next = current+1;
931:
if(
AG903_I2C_QUENUM <= next) {
932: next = 0;
933: }
934:
935:
return next;
936: }
937:
938:
943:
static int32_t I2CMgr_GetQueCount(uint8_t ch, uint32_t* count)
944: {
945: int32_t retval =
AG903_ENONE;
946:
947:
if( (
AG903_I2C_CH_NUM <= ch) ||
948: (NULL == count) ) {
949:
return -
AG903_EINVAL;
950: }
951:
952:
if(I2cQue[ch].rp <= I2cQue[ch].wp) {
953: (*count) = I2cQue[ch].wp - I2cQue[ch].rp;
954: }
955:
else {
956: (*count) =
AG903_I2C_QUENUM - I2cQue[ch].rp + I2cQue[ch].wp + 1;
957: }
958:
959:
return retval;
960: }
961:
962:
963:
966:
static void I2CMgr_Inthdr0(
void)
967: {
968: I2CMgr_IntProcess(0);
969:
return;
970: }
971:
972:
975:
static void I2CMgr_Inthdr1(
void)
976: {
977: I2CMgr_IntProcess(1);
978:
return;
979: }
980:
981:
985:
static void I2CMgr_IntProcess(uint8_t ch)
986: {
987: int32_t result =
AG903_ENONE;
988: uint32_t event = 0;
989:
990:
switch(I2cChStat[ch].stat) {
991:
case AG903_I2C_CH_MASTER_WRITE:
992: result = I2CMgr_IntMasterWrite(ch, &event);
993:
if(
AG903_ENONE != result) {
994:
995: }
996:
break;
997:
case AG903_I2C_CH_MASTER_READ:
998: result = I2CMgr_IntMasterRead(ch, &event);
999:
if(
AG903_ENONE != result) {
1000:
1001: }
1002:
break;
1003:
case AG903_I2C_CH_SLAVE_WRITE:
1004: result = I2CMgr_IntSlaveWrite(ch, &event);
1005:
if(
AG903_ENONE != result) {
1006:
1007: }
1008:
break;
1009:
case AG903_I2C_CH_SLAVE_READ:
1010: result = I2CMgr_IntSlaveRead(ch, &event);
1011:
if(
AG903_ENONE != result) {
1012:
1013: }
1014:
break;
1015:
default:
1016:
1017:
break;
1018: }
1019:
1020:
if(0 != event) {
1021: I2cHandleStat[ch][I2cChStat[ch].hdlnum].stat = AG903_I2C_HANDLE_IDLE;
1022:
if(NULL != I2cHandleStat[ch][I2cChStat[ch].hdlnum].clbk) {
1023: I2cHandleStat[ch][I2cChStat[ch].hdlnum].clbk
1024: ((
AG903_I2CMgrHandle*)&I2cHandleStat[ch][I2cChStat[ch].hdlnum], event);
1025: }
1026: }
1027:
1028: I2CMgr_MainProcess(ch);
1029:
1030:
return;
1031: }
1032:
1033:
1038:
static int32_t I2CMgr_IntMasterWrite(uint8_t ch, uint32_t* event)
1039: {
1040: int32_t retval =
AG903_ENONE;
1041: uint32_t status;
1042: uint32_t set_bit = 0;
1043: uint8_t nextdata = 0;
1044:
1045: (*event) = 0;
1046:
1047:
if( (
AG903_I2C_CH_NUM <= ch) ||
1048: (NULL == event) ) {
1049:
return -
AG903_EINVAL;
1050: }
1051:
1052:
AG903_I2CPrmGetStatus(ch, &status);
1053:
1054:
if(status&
AG903_I2C_SR_AL_BIT) {
1055: (*event) |=
AG903_I2C_EVENT_LOSES_ARBITRATION;
1056: }
1057:
if(status&
AG903_I2C_SR_BERR_BIT) {
1058: (*event) |=
AG903_I2C_EVENT_SEQUENCE_ERR;
1059: }
1060:
1061:
if((0 == (*event)) && (status&
AG903_I2C_SR_DT_BIT)) {
1062:
switch(I2cChStat[ch].sequence) {
1063:
case AG903_I2C_SEQ_SND_SADDR_H:
1064: nextdata = (uint8_t)I2cChStat[ch].arg.wr.addr;
1065: set_bit =
AG903_I2C_CR_TBEN_BIT;
1066: I2cChStat[ch].sequence = AG903_I2C_SEQ_SND_SADDR_L;
1067:
break;
1068:
case AG903_I2C_SEQ_SND_SADDR_L:
1069: nextdata = (*(I2cChStat[ch].arg.wr.buf+I2cChStat[ch].cnt));
1070: set_bit =
AG903_I2C_CR_TBEN_BIT;
1071:
if(((I2cChStat[ch].cnt+1) >= I2cChStat[ch].arg.wr.size) && (
true == I2cChStat[ch].arg.wr.stop)){
1072: set_bit |=
AG903_I2C_CR_STOP_BIT;
1073: }
1074: I2cChStat[ch].sequence = AG903_I2C_SEQ_SND;
1075:
break;
1076:
case AG903_I2C_SEQ_SND:
1077: I2cChStat[ch].cnt++;
1078:
if(I2cChStat[ch].arg.wr.size <= I2cChStat[ch].cnt) {
1079: (*event) |=
AG903_I2C_EVENT_WRITE_END;
1080: }
1081:
else {
1082: nextdata = (*(I2cChStat[ch].arg.wr.buf+I2cChStat[ch].cnt));
1083: set_bit =
AG903_I2C_CR_TBEN_BIT;
1084:
if(((I2cChStat[ch].cnt+1) >= I2cChStat[ch].arg.wr.size) && (
true == I2cChStat[ch].arg.wr.stop)){
1085: set_bit |=
AG903_I2C_CR_STOP_BIT;
1086: }
1087: }
1088:
break;
1089:
default:
1090: (*event) |=
AG903_I2C_EVENT_WRITE_ERR;
1091:
break;
1092: }
1093:
if(0 == (*event)) {
1094:
AG903_I2CPrmWriteData(ch, nextdata);
1095:
AG903_I2CPrmClearControl(ch, (
AG903_I2C_CR_START_BIT|
AG903_I2C_CR_STOP_BIT));
1096:
AG903_I2CPrmSetControl(ch, set_bit);
1097: }
1098: }
1099:
1100:
if(0 != (*event)) {
1101:
AG903_I2CPrmClearControl(ch, (
AG903_I2C_CR_ALLINT_BIT|
AG903_I2C_CR_ALLCTRL_BIT));
1102: I2cChStat[ch].stat = AG903_I2C_CH_IDLE;
1103: }
1104:
1105:
return retval;
1106: }
1107:
1108:
1113:
static int32_t I2CMgr_IntMasterRead(uint8_t ch, uint32_t* event)
1114: {
1115: int32_t retval =
AG903_ENONE;
1116: uint32_t status;
1117:
1118: (*event) = 0;
1119:
1120:
if( (
AG903_I2C_CH_NUM <= ch) ||
1121: (NULL == event) ) {
1122:
return -
AG903_EINVAL;
1123: }
1124:
1125:
AG903_I2CPrmGetStatus(ch, &status);
1126:
1127:
if(status&
AG903_I2C_SR_AL_BIT) {
1128: (*event) |=
AG903_I2C_EVENT_LOSES_ARBITRATION;
1129: }
1130:
1131:
switch(I2cChStat[ch].sequence) {
1132:
case AG903_I2C_SEQ_SND_SADDR_H:
1133:
if(status&
AG903_I2C_SR_BERR_BIT) {
1134: (*event) |=
AG903_I2C_EVENT_SEQUENCE_ERR;
1135: }
1136:
if((0 == (*event)) && (status&
AG903_I2C_SR_DT_BIT)) {
1137:
AG903_I2CPrmWriteData(ch, (uint8_t)I2cChStat[ch].arg.rd.addr);
1138:
AG903_I2CPrmClearControl(ch, (
AG903_I2C_CR_START_BIT|
AG903_I2C_CR_STOP_BIT));
1139:
AG903_I2CPrmSetControl(ch,
AG903_I2C_CR_TBEN_BIT);
1140: I2cChStat[ch].sequence = AG903_I2C_SEQ_SND_SADDR_L;
1141: }
1142:
break;
1143:
case AG903_I2C_SEQ_SND_SADDR_L:
1144:
if(status&
AG903_I2C_SR_BERR_BIT) {
1145: (*event) |=
AG903_I2C_EVENT_SEQUENCE_ERR;
1146: }
1147:
if((0 == (*event)) && (status&
AG903_I2C_SR_DT_BIT)) {
1148:
AG903_I2CPrmClearControl(ch, (
AG903_I2C_CR_START_BIT|
AG903_I2C_CR_STOP_BIT));
1149:
if(1 >= I2cChStat[ch].arg.rd.size) {
1150:
AG903_I2CPrmSetControl(ch, (
AG903_I2C_CR_TBEN_BIT|
AG903_I2C_CR_ACKNACK_BIT|
AG903_I2C_CR_STOP_BIT));
1151: I2cChStat[ch].sequence = AG903_I2C_SEQ_RCV_LAST;
1152: }
1153:
else {
1154:
AG903_I2CPrmSetControl(ch,
AG903_I2C_CR_TBEN_BIT);
1155: I2cChStat[ch].sequence = AG903_I2C_SEQ_RCV;
1156: }
1157: }
1158:
break;
1159:
case AG903_I2C_SEQ_RCV:
1160:
if((0 == (*event)) && (status&
AG903_I2C_SR_DR_BIT)) {
1161:
AG903_I2CPrmReadData(ch, (uint8_t*)(I2cChStat[ch].arg.rd.buf+I2cChStat[ch].cnt));
1162: I2cChStat[ch].cnt++;
1163:
AG903_I2CPrmClearControl(ch, (
AG903_I2C_CR_START_BIT|
AG903_I2C_CR_STOP_BIT));
1164:
if((I2cChStat[ch].arg.rd.size-1) <= I2cChStat[ch].cnt) {
1165:
AG903_I2CPrmSetControl(ch, (
AG903_I2C_CR_TBEN_BIT|
AG903_I2C_CR_ACKNACK_BIT|
AG903_I2C_CR_STOP_BIT));
1166: I2cChStat[ch].sequence = AG903_I2C_SEQ_RCV_LAST;
1167: }
1168:
else {
1169:
AG903_I2CPrmSetControl(ch,
AG903_I2C_CR_TBEN_BIT);
1170: I2cChStat[ch].sequence = AG903_I2C_SEQ_RCV;
1171: }
1172: }
1173:
break;
1174:
case AG903_I2C_SEQ_RCV_LAST:
1175:
if(0 == (status&
AG903_I2C_SR_ACK_BIT)) {
1176: (*event) |=
AG903_I2C_EVENT_SEQUENCE_ERR;
1177: }
1178:
if((0 == (*event)) && (status&
AG903_I2C_SR_DR_BIT)) {
1179:
AG903_I2CPrmReadData(ch, (uint8_t*)(I2cChStat[ch].arg.rd.buf+I2cChStat[ch].cnt));
1180: I2cChStat[ch].cnt++;
1181: (*event) |=
AG903_I2C_EVENT_READ_END;
1182: }
1183:
break;
1184:
default:
1185: (*event) |=
AG903_I2C_EVENT_READ_ERR;
1186:
break;
1187: }
1188:
1189:
if(0 != (*event)) {
1190:
AG903_I2CPrmClearControl(ch, (
AG903_I2C_CR_ALLINT_BIT|
AG903_I2C_CR_ALLCTRL_BIT));
1191: I2cChStat[ch].stat = AG903_I2C_CH_IDLE;
1192: }
1193:
1194:
return retval;
1195: }
1196:
1197:
1202:
static int32_t I2CMgr_IntSlaveWrite(uint8_t ch, uint32_t* event)
1203: {
1204: int32_t retval =
AG903_ENONE;
1205: uint32_t status;
1206:
1207: (*event) = 0;
1208:
1209:
if( (
AG903_I2C_CH_NUM <= ch) ||
1210: (NULL == event) ) {
1211:
return -
AG903_EINVAL;
1212: }
1213:
1214:
AG903_I2CPrmGetStatus(ch, &status);
1215:
1216:
switch(I2cChStat[ch].sequence) {
1217:
case AG903_I2C_SEQ_RCV_SADDR:
1218:
if((status&
AG903_I2C_SR_SAM_BIT) && (status&
AG903_I2C_SR_DR_BIT) && (status&
AG903_I2C_SR_I2CB_BIT)) {
1219:
AG903_I2CPrmWriteData(ch, (uint8_t)(*(I2cChStat[ch].arg.wr.buf+I2cChStat[ch].cnt)));
1220:
AG903_I2CPrmSetControl(ch,
AG903_I2C_CR_TBEN_BIT);
1221: I2cChStat[ch].sequence = AG903_I2C_SEQ_SND;
1222: }
1223:
break;
1224:
case AG903_I2C_SEQ_SND:
1225:
if(status&
AG903_I2C_SR_DT_BIT) {
1226: I2cChStat[ch].cnt++;
1227:
if(I2cChStat[ch].arg.wr.size <= I2cChStat[ch].cnt) {
1228: (*event) |=
AG903_I2C_EVENT_WRITE_END;
1229: }
1230:
else {
1231:
if((status&
AG903_I2C_SR_ACK_BIT) || (status&
AG903_I2C_SR_STOP_BIT)) {
1232: I2cChStat[ch].sequence = AG903_I2C_SEQ_RCV_SADDR;
1233: }
1234:
else {
1235:
AG903_I2CPrmWriteData(ch, (uint8_t)(*(I2cChStat[ch].arg.wr.buf+I2cChStat[ch].cnt)));
1236:
AG903_I2CPrmSetControl(ch,
AG903_I2C_CR_TBEN_BIT);
1237: }
1238: }
1239: }
1240:
break;
1241:
default:
1242: (*event) |=
AG903_I2C_EVENT_WRITE_ERR;
1243:
break;
1244: }
1245:
1246:
if(0 != (*event)) {
1247:
AG903_I2CPrmClearControl(ch, (
AG903_I2C_CR_ALLINT_BIT|
AG903_I2C_CR_ALLCTRL_BIT));
1248: I2cChStat[ch].stat = AG903_I2C_CH_IDLE;
1249: }
1250:
1251:
return retval;
1252: }
1253:
1254:
1259:
static int32_t I2CMgr_IntSlaveRead(uint8_t ch, uint32_t* event)
1260: {
1261: int32_t retval =
AG903_ENONE;
1262: uint32_t status;
1263:
1264: (*event) = 0;
1265:
1266:
if( (
AG903_I2C_CH_NUM <= ch) ||
1267: (NULL == event) ) {
1268:
return -
AG903_EINVAL;
1269: }
1270:
1271:
AG903_I2CPrmGetStatus(ch, &status);
1272:
1273:
switch(I2cChStat[ch].sequence) {
1274:
case AG903_I2C_SEQ_RCV_SADDR:
1275:
if((status&
AG903_I2C_SR_SAM_BIT) && (status&
AG903_I2C_SR_DR_BIT) && (status&
AG903_I2C_SR_I2CB_BIT)) {
1276:
AG903_I2CPrmSetControl(ch,
AG903_I2C_CR_TBEN_BIT);
1277: I2cChStat[ch].sequence = AG903_I2C_SEQ_RCV;
1278: }
1279:
break;
1280:
case AG903_I2C_SEQ_RCV:
1281:
if (status&
AG903_I2C_SR_DR_BIT) {
1282:
AG903_I2CPrmReadData(ch, (uint8_t*)(I2cChStat[ch].arg.rd.buf+I2cChStat[ch].cnt));
1283: I2cChStat[ch].cnt++;
1284:
if((I2cChStat[ch].arg.rd.size) <= I2cChStat[ch].cnt) {
1285: (*event) |=
AG903_I2C_EVENT_READ_END;
1286: }
1287:
if(status&
AG903_I2C_SR_STOP_BIT) {
1288: I2cChStat[ch].sequence = AG903_I2C_SEQ_RCV_SADDR;
1289: }
1290:
if((0==(*event)) && (AG903_I2C_SEQ_RCV==I2cChStat[ch].sequence)) {
1291:
AG903_I2CPrmSetControl(ch,
AG903_I2C_CR_TBEN_BIT);
1292: }
1293: }
1294:
break;
1295:
default:
1296: (*event) |=
AG903_I2C_EVENT_WRITE_ERR;
1297:
break;
1298: }
1299:
1300:
if(0 != (*event)) {
1301:
AG903_I2CPrmClearControl(ch, (
AG903_I2C_CR_ALLINT_BIT|
AG903_I2C_CR_ALLCTRL_BIT));
1302: I2cChStat[ch].stat = AG903_I2C_CH_IDLE;
1303: }
1304:
1305:
return retval;
1306: }