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#include "AG903_errno.h"
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#include "AG903_common.h"
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#include "timr/timrprm.h"
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#include "register/AG903_timreg.h"
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#define AG903_TIMR_READ_REGn(CH,REG) (
AG903_TIMn(CH)->REG)
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#define AG903_TIMR_READ_FLDn(CH,REG,POS,MSK) ( ( (
AG903_TIMn(CH)->REG) & MSK ) >> POS )
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#define AG903_TIMR_WRITE_REGn(CH,REG,VAL) (
AG903_TIMn(CH)->REG = (uint32_t)(VAL))
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#define AG903_TIMR_CLR_REGn(CH,REG,VAL) (
AG903_TIMn(CH)->REG &= (uint32_t)(~VAL))
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#define AG903_TIMR_SET_REGn(CH,REG,VAL) (
AG903_TIMn(CH)->REG |= (uint32_t)(VAL))
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#define AG903_TIMR_WRITE_REG(REG,VAL) (
AG903_TIM->REG = (uint32_t)(VAL))
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void AG903_TIMRPrmSetInMode(uint8_t ch,
AG903_TIMRPrmInModeParam* param)
39: {
40: uint32_t val=0;
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ASSERT(
AG903_TIMR_CH_NUM > ch);
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ASSERT(NULL != param);
44:
45: val |= (param->eve&0x3F);
46: val <<= 6;
47: val |= (param->lo&0x01);
48: val <<= 2;
49: val |= (param->ch&0x03);
50: val <<= 8;
51: val |= (param->pol&0x01);
52: val <<= 8;
53: val |= (param->res&0x03);
54:
55: AG903_TIMR_WRITE_REGn(ch,INMOD,val);
56:
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return;
58: }
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void AG903_TIMRPrmSetOutMode(uint8_t ch,
AG903_TIMRPrmOutModeParam* param)
68: {
69: uint32_t val=0;
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ASSERT(
AG903_TIMR_CH_NUM > ch);
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ASSERT(NULL != param);
73:
74: val |= (param->cm&0x01);
75: val <<= 1;
76: val |= (param->ovf&0x01);
77: val <<= 8;
78: val |= (param->ch&0x03);
79: val <<= 8;
80: val |= (param->pol&0x01);
81: val <<= 8;
82: val |= (param->mod&0x03);
83:
84: AG903_TIMR_WRITE_REGn(ch,OUTMOD,val);
85:
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return;
87: }
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void AG903_TIMRPrmSetResetTrigger(uint8_t ch,
AG903_TIMRPrmResetTriggerParam* param)
97: {
98: uint32_t val=0;
99:
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ASSERT(
AG903_TIMR_CH_NUM > ch);
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ASSERT(NULL != param);
102:
103: val |= (param->eve&0x3F);
104: val <<= 6;
105: val |= (param->lo&0x01);
106: val <<= 2;
107: val |= (param->ch&0x03);
108: val <<= 8;
109: val |= (param->pol&0x01);
110: val <<= 4;
111: val |= (param->res&0x03);
112: val <<= 2;
113: val |= (param->boot&0x03);
114: val <<= 2;
115: val |= (param->en&0x03);
116:
117: AG903_TIMR_WRITE_REGn(ch,RSTTRG,val);
118:
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return;
120: }
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void AG903_TIMRPrmEnableOneshot(uint8_t ch)
130: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
132: AG903_TIMR_SET_REGn(ch,CTRL,(1<<
AG903_TIMn_CTRL_OS_POS));
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return;
134: }
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void AG903_TIMRPrmDisableOneshot(uint8_t ch)
144: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
146: AG903_TIMR_CLR_REGn(ch,CTRL,(1<<
AG903_TIMn_CTRL_OS_POS));
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return;
148: }
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void AG903_TIMRPrmSetCntMode(uint8_t ch, uint8_t mode)
159: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
161: AG903_TIMR_CLR_REGn(ch,CTRL,
AG903_TIMn_CTRL_MOD_MSK);
162: AG903_TIMR_SET_REGn(ch,CTRL,(mode<<
AG903_TIMn_CTRL_MOD_POS));
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return;
164: }
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void AG903_TIMRPrmGetCntMode(uint8_t ch, uint8_t* mode)
174: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
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ASSERT(NULL != mode);
177: (*mode) = AG903_TIMR_READ_FLDn(ch,CTRL,
AG903_TIMn_CTRL_MOD_POS,
AG903_TIMn_CTRL_MOD_MSK);
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return;
179: }
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void AG903_TIMRPrmSetCount(uint8_t ch, uint32_t count)
190: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
192: AG903_TIMR_WRITE_REGn(ch,CNT,count);
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return;
194: }
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void AG903_TIMRPrmGetCount(uint8_t ch, uint32_t* count)
204: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
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ASSERT(NULL != count);
207: (*count) = AG903_TIMR_READ_REGn(ch,CNT);
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return;
209: }
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void AG903_TIMRPrmSetPeriod(uint8_t ch, uint32_t period)
219: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
221: AG903_TIMR_WRITE_REGn(ch,PERIOD,period);
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return;
223: }
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void AG903_TIMRPrmGetPeriod(uint8_t ch, uint32_t* period)
233: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
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ASSERT(NULL != period);
236: (*period) = AG903_TIMR_READ_REGn(ch,PERIOD);
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return;
238: }
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void AG903_TIMRPrmSetMatch(uint8_t ch, uint32_t match)
248: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
250: AG903_TIMR_WRITE_REGn(ch,MATCH,match);
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return;
252: }
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void AG903_TIMRPrmGetMatch(uint8_t ch, uint32_t* match)
262: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
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ASSERT(NULL != match);
265: (*match) = AG903_TIMR_READ_REGn(ch,MATCH);
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return;
267: }
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void AG903_TIMRPrmSetPluseWidth(uint8_t ch, uint32_t width)
277: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
279: AG903_TIMR_WRITE_REGn(ch,PULWID,(width&
AG903_TIMn_PULWID_VAL_MSK));
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return;
281: }
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void AG903_TIMRPrmGetPluseWidth(uint8_t ch, uint32_t* width)
291: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
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ASSERT(NULL != width);
294: (*width) = AG903_TIMR_READ_FLDn(ch,PULWID,
AG903_TIMn_PULWID_VAL_POS,
AG903_TIMn_PULWID_VAL_MSK);
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return;
296: }
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void AG903_TIMRPrmEnableMask(uint8_t ch, uint32_t setbit)
308: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
310: AG903_TIMR_SET_REGn(ch,INTMASK,setbit);
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return;
312: }
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void AG903_TIMRPrmDisableMask(uint8_t ch, uint32_t clrbit)
324: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
326: AG903_TIMR_CLR_REGn(ch,INTMASK,clrbit);
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return;
328: }
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void AG903_TIMRPrmEnableEventTrigger(uint8_t ch, uint32_t setbit)
340: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
342: AG903_TIMR_SET_REGn(ch,TRIGGER,setbit);
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return;
344: }
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void AG903_TIMRPrmDisableEventTrigger(uint8_t ch, uint32_t clrbit)
356: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
358: AG903_TIMR_CLR_REGn(ch,TRIGGER,clrbit);
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return;
360: }
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void AG903_TIMRPrmEnableDmaRequest(uint8_t ch, uint32_t setbit)
372: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
374: AG903_TIMR_SET_REGn(ch,DMAREQ,setbit);
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return;
376: }
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void AG903_TIMRPrmDisableDmaRequest(uint8_t ch, uint32_t clrbit)
388: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
390: AG903_TIMR_CLR_REGn(ch,DMAREQ,clrbit);
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return;
392: }
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void AG903_TIMRPrmGetStatus(uint8_t ch, uint32_t* status)
402: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
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ASSERT(NULL != status);
405: (*status) = AG903_TIMR_READ_REGn(ch,STAT);
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return;
407: }
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void AG903_TIMRPrmClearStatus(uint8_t ch, uint32_t setbit)
420: {
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ASSERT(
AG903_TIMR_CH_NUM > ch);
422: AG903_TIMR_WRITE_REGn(ch,CLR,setbit);
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return;
424: }
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void AG903_TIMRPrmSetBootTrigger(uint8_t chbit)
437: {
438: AG903_TIMR_WRITE_REG(BOOTTRG,chbit);
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return;
440: }