/*
    CF host controller
    Configuration
    
    Copyright (c) 2015, eForce Co.,Ltd.
    
    2015-12-14: Created
*/

#if !defined(DDR_AG903_CF_CFG_H)
#define DDR_AG903_CF_CFG_H

#include "AG903_UC3.h"       /* Register definitions */

#define CFG_CF_CLK_MHZ          133            /* Clock source(CLK_ATA) (100, 133) (MHz) */
#define CFG_CF_IPL              224            /* Interrupt priority (0..255) */

#define CFG_CF_DMA_CH           7     /* DMA channel (0..7)  */
#define CFG_CF_DMA_WT_PF_NUM    0     /* DMA write, peripheral interface number (0..15) */
#define CFG_CF_DMA_RD_PF_NUM    1     /* DMA read,  peripheral interface number (0..15) */
#define CFG_CF_DMA_PRI          1     /* DMA priority (1:High, 0:Low) */

#define CFG_CF_MOD              CF_MOD_UDMA    /* データ転送はUDMAを使用 */
#define CFG_CF_UDMA_MOD         5              /* UDMAモードの上限は6 */

#endif

