/*
    DMA controller
    Configuration
    
    Copyright (c) 2015, eForce Co.,Ltd.
    
    2015-09-28: Created
*/

#if !defined(DDR_AG903_DMA_CFG_H)
#define DDR_AG903_DMA_CFG_H

#include "AG903_UC3.h"    /* Register definitions */
#include "DDR_AG903_CF_cfg.h"

/* Configuration */
#define CFG_DMA_IPL    224     /* Interrupt priority (0..255) */
#define CFG_DMA_CH     CFG_CF_DMA_CH    /* DMA channel (0..7)  */

#endif

