/*
    SD host controller
    Configuration
    
    Copyright (c) 2016, eForce Co.,Ltd.
    
    2016-03-02: Created
*/

#if !defined(DDR_AG903_SD_CFG_H)
#define DDR_AG903_SD_CFG_H

#include "AG903_UC3.h"    /* Register definitions */

/* System */
#define CFG_SD_CLK_SYS         198000000U    /* System clock (sysc_aclk) [198Mhz] */

/* SD0 */
#define CFG_SD_CH0_ENA         1             /* Channel 0 enable */
#define CFG_SD_CH0_IPL         224           /* Interrupt priority (0..255) */
#define CFG_SD_CH0_CLK_SRC     99000000U     /* SD base clock (sdc_clk1) [99Mhz] */
#define CFG_SD_BUF_AREA        (0x83EE0000)
#endif

