/******************************************************************************
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******************************************************************************/
/******************************************************************************
* System Name : RZ/T1 Init(NOR/Serial boot) Sample Program
* File Name   : Description.txt
******************************************************************************/
/******************************************************************************
* History     : Jan. 29, 2015 Rev.1.00.00     Initial documentation
******************************************************************************/

1. Before Use

  This sample program has been written for and tested upon the RZ/T1 evaluation board. 
 

  ****************************** CAUTION ******************************
   This sample program is for reference only. Please use this sample 
   program for technical reference.
  ****************************** CAUTION ******************************


2. Overview & Features
   This module sets initial settings of RZ/T1 group.

   - Sets start up routine and initialize CPU (Cortex-R4F) 
   - Sets interrupt service routine about external interrupt input(IRQ5).
     LED1 is blinking when SW2(IRQ5 pin) is pused.
   - Sets interrupt service routine about external interrupt input(IRQ12).
     LED2 lights when SW3(IRQ12 pin) is pushed (Sets extended pseudo error 35).
   - Sets Clock pulse generator as CPU clock is 450MHz.
   - Refer to reset flag and branch to the each reset sequence.
     If ECM reset is detected, sets LED2 to be lighting.
   - Initialize the bus settings as the following.
      16-bit bus boot(NOR) : CS0 area be connected to NOR flash 1 (boot memory).
                             CS1 area be connected to NOR flash 2.
                             CS2 area be connected to SDRAM 1.
                             CS3 area be connected to SDRAM 2.
      SPI boot (SPIBSC)    : SPIBSC  area be connected to Serial flash (boot memory).
                             CS0 area be connected to NOR flash 1.
                             CS1 area be connected to NOR flash 2.
                             CS2 area be connected to SDRAM 1.
                             CS3 area be connected to SDRAM 2.
   - Sets Error Control module (ECM) as ERROROUT pin output in-actived.
     And extended pseudo error 35 is enabled as trigger of ECM reset. 
   - Sets using I/O port function.
     LED0 is blinking at intervals of about 0.3 sec.

                                          
3. Operation Confirmation Conditions
  
 (1) System
    CPU                      : RZ/T1 groupiR7S910017j
    Evaluation board         : RZ/T1 CPU Board (RTK7910022C00000BR)
    Development environment  : IAR Embedded Workbench for ARM (Ver. 7.30.4)
                               IAR I-jet
    Operation mode           : SPI boot mode (Serial flash),
                               16-bit bus boot mode (NOR flash)
                               

  (2) Operating frequency
      The RZ/T1 evaluation board has the following clock inputs.
      - Main oscillator clock           : 25MHz
      - CPU clock (CPUCLK)              : 450MHz

  (3) Setting for DIP switches and jumpers 
        Set the  DIP switches and jumpers of the RTK7910022C00000BR as follows.

        SW4   - SW4-1 ON, SW4-2 ON, SW4-3 ON, SW4-4 ON, SW4-5 ON, SW4-6 OFF
                (SPI boot mode)
                  or 
                SW4-1 ON, SW4-2 OFF, SW4-3 ON, SW4-4 ON, SW4-5 ON, SW4-6 OFF
                (16-bit bus boot mode)
        JP2   - 2-3
	JP7   - 1-2


4. Other

   None.


        
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